                
                .LSTON
                .page
                .FIN
                .org    $800
                
;****************************************************************************
;*  scc code - resident routines
;****************************************************************************

; enable/disable scc: sets bank switch register output to enable or disable
; scc, depending on state of r0:  $01 to enable; $00 to disable.


edscc:         
                ld       !r3, !r0        ;set up enable/disable bit
                ld       !r2, #.hibyte. sccbank
                lde      @!!r2,!r0                   ;select scc
                ret
                
;========================================================================
;  initscc - initializes all scc on-chip registers
;========================================================================

;first the write registers:

initscc:
; program a hardware reset since Z8 clock out wasn't running at hardware reset
; time - it should be running now if Z8 initialized correctly.

                ld      !r0,#hrst
                ld      !r3,#sw9rst
                lde     @!!r2,!r0               ;issue hardware reset cmd in wr9

; now initialize remainder of write registers

                ld      !r0,#sdlc
                ld      !r3,#sw4mode
                lde     @!!r2,!r0               ;set sdlc mode in wr4
                
                ld      !r0,#tcntrl_init
                ld      !r3,#sw10tcntrl
                lde     @!!r2,!r0               ;set flag idle, crc preset to 1s
                
                ld      !r0,#flag
                ld      !r3,#sw7flg
                lde     @!!r2,!r0               ;set flag byte: 01111110
                
                ld      !r0,#xmtinit
                ld      !r3,#sw5xmt
                lde     @!!r2,!r0               ;initialize transmitter
                
                ld      !r0,#myadr
                ld      !r3,#sw6adr
                lde     @!!r2,!r0               ;set my address ($01)
                
                ld      !r0,#rcvinit
                ld      !r3,#sw3rcv
                lde     @!!r2,!r0               ;init receiver
                
                ld      !r0,#intinit
                ld      !r3,#sw1int
                lde     @!!r2,!r0               ;disable interrupts
                
                ld      !r0,#clkvalt
                ld      !r3,#sw11clk
                lde     @!!r2,!r0               ;set up xmt,rcv clock sources
                ;TRxC out = xmt clock (BR generator)
                
                ld      !r0,#brgenlo
                ld      !r3,#sw12brl
                lde     @!!r2,!r0               ;br generator lo byte
                
                ld      !r0,#brgenhi
                ld      !r3,#sw13brh
                lde     @!!r2,!r0               ;br generator hi ;byte
                
                ld      !r0,#xintdis
                ld      !r3,#sw15xint
                lde     @!!r2,!r0               ;disable transmit interrupts

;set up clock sources for BR generator and digital phase locked loop (dpll)

                ld      !r3,#sw14cgen           ;set up address for next series
                ;of commands
                ld      !r0,#displl
                lde     @!!r2,!r0               ;disable pll, enable br gener.
                
                ld      !r0,#pllclk
                lde     @!!r2,!r0               ;set RTxC = dpll clk
                
                ld      !r0,#setfm
                lde     @!!r2,!r0            ;set fm mode for dpll
                
                ld      !r0,#enpll + enbrg
                lde     @!!r2,!r0               ;enable pll and brgen - sets 
                                                ;sync/hunt bit also
                ret
                
                .page

;===========================================================================
;  T1poll_ab routine - Enable Applebus Timer (T1) for polled operation
;
;  Stops, then starts T1 in continuous mode at 200us, if rpack called, or
;  400us, if tpack called.  This is polled operations; no interrupts are
;  used.
;   
;  The T1 Irq is cleared prior to starting timer since an Irq may have 
;  previously been set.
;
;  INPUTS:  r0: 0 if rpack is caller; 1 if tpack is caller.
;
;  OUTPUTS: Clears T1 Irq and starts T1, set for either 200us or 400us.
;
;  REGISTERS:  r0 - see above.
;
;===========================================================================
                
T1poll_ab:
                ld      Tmr, #Int_Out   ;stop jT1, keep ext clock output going.
                ld      Pre1, #$B       ;prescaler = divide by 2, continuous cnt
                ld      T1, #w_200      ;set up for 200us
                or      !r0, !r0        ;check rpack or tpack calling
                jr      z, start_timer
                ld      T1, #w_400      ;change to 400us for tpack
start_timer:
                and     Irq, #$FF-Timer1        ;clear old Irq if set
                or      Tmr, #T1_CntEn + T1_Load ;start T1
                ret
                
;===========================================================================
;  T1_restore routine
;
;  Stops, then starts T1 at continuous 10 ms intervals, used for rpack 
;  and widget dead man timers via T1 interrupt routine - abwigint  
;  Clears any previous Irq
;
;===========================================================================

T1_restore:
                ld      Tmr, #Int_Out   ;stop T1, keep ext clock going
                ld      Pre1, #$3
                ld      T1, #143        ;set up for 10ms continuous opn.
                and     Irq, #$FF-Timer1        ;clr old Irq
                or      Tmr, #T1_CntEn + T1_Load + T0_CntEn  ;start the timer
                ret
                
                .page
                
;=======================================================================
;  abwigint routine -  interrupt routine for applebus and widget interrupts
;
;  Checks for scc interrupt enable bit to execute widget interrupt routine
;  or scc interrupt routine.  Both decrement the dead man timer counter, clr Irq
;  and return to interrupted routine if non-zero.  If zero, widget pops 
;  flags and return address and aborts.  Applebus does likewise but returns
;  to calling routine with scc_timout bit set and sccinten bit clr.  Irq
;  for T1 is also cleared.
;
;  INPUTS:  sccinten bit in bus_stat1
;           Dmt_Counter set up to proper timeout value in multiples of 10ms
;
;  OUTPUTS:  scc_timout bit set if Dmt_Counter goes to zero for scc mode;
;            call Abort for widget.  Irq cleared.
;============================================================================

abwigint:
                tm      bus_stat1, #sccinten    ;scc interrupt?
                jr      z, wigint               ;no if taken
                decw    Dmt_Counter
                jr      nz, int_ret             ;ret if not timeout
                
                or      bus_stat3, #scc_timout  ;set error status
                and     bus_stat1, #$FF-sccinten ;clr scc int enable
                pop     !r0                     ;pop flags
                pop     !r2
                pop     !r3                     ;and return address
                srp     #wrk_absys              ;restore caller's environment
                ret
wigint:
                Decw    Dmt_Counter
                jr      z, JpVector4            ;abort if zero
int_ret:
                and     Irq, #$FF - Timer1      ;clr this interrupt
                ei
                iret
JpVector4:
                jp      Vector4

;============================================================================
;  rcv_clr routine
;
;  receiver clear routine.  Designed to work with tpack and rpack to initialize
;  the receiver.  scc pointers are assumed set up as indicated below.  
;  Disables the receiver, then flushes the receive FIFO, then resets the status
;  bits in status reg. 1.  Used by tpack to set up receiver ahead of time 
;  to save time in rpack when tpack and rpack are called in sequence.
;
;  INPUTS:  r6   = pointer to hibyte of scc bank - r7 not preset        
;           r8r9 = pointer to scc receive buffer - scc_rbuf
;
;  OUTPUTS:  receiver disabled, FIFO flushed, and status reg 1 cleared.
;
;  REGISTERS:
;
;  r0  : temp. storage - constants for loading into scc registers
;  r6r7: pointer to sw3rcv and sw0cmd (scc cmd register)
;  r8r9: pointer to scc_rbuf, the top of FIFO buffer
;
;==========================================================================

rcv_clr:
                ld      !r7, #sw3rcv    ;ptr to rcvr mode register
                ld      !r0, #rcvinit
                lde     @!!r6, !r0      ;disable receiver
                lde     !r0,@!!scc_rbuf  ;flush the receive FIFO
                lde     !r0,@!!scc_rbuf
                lde     !r0,@!!scc_rbuf

                ld      !r7, #sw0cmd
                ld      !r0, #erres
                lde     @!!r6, !r0      ;clear receive status bits in sts reg 1
                ret

                .page

;=============================================================================
; tpack routine
;
; Transmit packet.  If l_busy = 0, enables rcvr and waits for bus idle (sensed
; by the sync/hunt scc status bit), then waits for backoff count passed by
; higher level in increments of 400us.  After backoff, checks missing clock
; bit for a final check on bus idle; if clear, then can xmit packet.
; Times out if bus does not go idle within 2 sec.  If bus goes non-idle during
; backoff wait, routine returns with bus_busy flag set.
;
; After backoff time, or if l_busy = 1, the receiver is disabled, flushed,
; and reset (rcv_clr), and then the packet is transmitted, preceeded by a
; "pulse" on the line created by turning RTS on and off for > 1 bit time.
; Since the transmitter is idling (transmitting "1's"), this will cause at 
; least one transition on the line which will set the missing clock bits of
; all other devices not transmitting on the bus.  The missing clock status
; is then used as a final "collision detect" at other bus nodes as described
; above.  The packet is now ready to be transmitted.  If in diagnostic mode,
; the RTS and DTR signals are 0 which forces a loopback of transmit data to
; receive data (outside the scc chip) and disables the driver connected to the 
; Applebus cable.  The lap header is taken from the lap storage area in the 
; Z8's registers (their_node, our_node, lap_ctrl); remainder of data taken from
; xmt buffer in RAM.  The byte count is passed to routine.  If zero, only
; the lap header is transmitted.
;
; INPUTS: 1) backoff count in rCrD (boffhi,lo)
;         2) xmt buffer pointer in rErF
;         3) bytecount value in bytecnthi,lo (does not include lap bytes)
;         4) l_busy, sccdiag bits in bus_stat1
;
; OUTPUTS: 1) bus_stat1: msg_sent bit if transmit completes.
;          2) bus_stat3: no_busidle bit set if time out waiting for idle bus
;          3) bus_stat4: bus_busy bit set if bus went busy during backoff
;          Note:  There is no timeout mechanism once transmit data loop starts
;
; REGISTERS:
;
; r0  : temp storage
; r1  : not used (reserved for rpack usage)
; r2r3: ptr to scc status reg 0 (scc_sts0)
; r4r5: counter for bus idle timeout, and ...
; r4  : transmit buffer empty mask (tbuf_emp)
; r5  : reset transmit underrun latch (rturl) constant, and temp storage
; r6r7: ptr to scc xmt reg (sw5xmt), sccrcv reg (sw3rcv), and cmd reg's
;       (sw0cmd and sw14cgen), and missing clock status reg (sr10mclk)
; r8r9: ptr to scc on-chip data buffer (scc_wbuf or scc_rbuf)
; rA  : used for bytecnt hi value passed by calling routine
; rB  :     "            lo             "
; rCrD: backoff count (boffhi,lo) during backoff part of tpack, and ...
; rC  : temp. storage
; rD  : ptr to lap header in Z8 registers
; rErF: ptr to transmit buffer in RAM (xmtbuf)
;
;============================================================================

                .page

tpack:
;load working registers - local variables
                srp     #wrk_abtr               ;set wrkg set for tpack
                ld      !scc_sts0hi, #.hibyte. sccbank
                ld      !scc_sts0lo, #sr0sts     ;ptr to status reg 0
                ld      !r6, #.hibyte. sccbank
                ld      !r7, #sw3rcv            ;ptr to rcvr reg for rcv init
                ld      !scc_wbufhi, #.hibyte. sccbank
                ld      !scc_wbuflo, #sw8buf     ;ptr to scc write buffer
; check for link busy state
                tm      bus_stat1, #l_busy      ;transmit immediately?
                jr      nz, xmt_start           ;yes if taken

; set up bus idle timer after enable receiver to sense bus idle condition
                ld      !r0 , #rcven
                lde     @!!r6, !r0              ;enable receiver
                ld      !r4, #.hibyte. busidl_to
                ld      !r5, #.lowbyte. busidl_to
                ld      !r0, #1                 ;set up for tpack caller
                call    T1poll_ab               ;start timer
chk_busidl:
                lde     !r0,@!!scc_sts0
                tm      !r0, #sync_hunt         ;idle bus?
                jr      nz, boff_start          ;yes if jump
                tm      Irq, #Timer1            ;400us up?
                jr      z, chk_busidl           ;no if jump
                and     Irq, #$FF - Timer1      ;clear T1 Irq
                decw    !!r4                    ;bump fixed timeout value
                jr      nz, chk_busidl
                or      bus_stat3, #no_busidl   ;timed out
tpack_ret:
                srp     #wrk_absys              ;restore regset for caller
                ret
boff_start:
                ld      !r0, #1
                call    T1poll_ab               ;start 400us timer again
                
                ld      !r7, #sw14cgen
                ld      !r0, #rstmck
                lde     @!!r6, !r0              ;reset missing clock latches
boff_loop:
                lde     !r0,@!!scc_sts0          ;check for idle bus
                tm      !r0, #sync_hunt
                jr      nz, bus_stillidle
bus_notidle:
                or      bus_stat4, #bus_busy    ;bus went busy during boff
                jr      tpack_ret
bus_stillidle:
                tm      Irq, #Timer1
                jr      z, boff_loop
                and     Irq, #$FF - Timer1      ;clr the Irq
                decw    boff                    ;bump boff counter (rCrD)
                jr      nz, boff_loop
; check missing clock before transmitting:
                ld      !r7, #sr10mclk
                lde     !r0, @!!r6              ;get missing clk status
                tm      !r0, #onecm
                jr      nz, bus_notidle         ;return if bus went busy
xmt_start:
;ready to transmit the packet!
                tm      bus_stat1, #scc_diag    ;skip rcvr init/disable if diag
                jr      nz, xmt_rdy
                call    rcv_clr         ;disable and init rcvr for subseq rpack
xmt_rdy:
                ld      !rD, #lap_ptr   ;set up ptr to lap header bytes
                ld      !r4, #tbuf_emp
                ld      !r5, #rturl     ;set up masks
;ready to start xmitting - sequence thru sending pulse, then enable xmtr   
                ld      !rC, #xmt_setup ;turn on RTS, xmtr disabled
                tm      bus_stat1, #sccdiag
                jr      z, en_drivr     ;skip diag setup if normal mode   
                and     !rC, #$FF - RTS - DTR  ;setup for diag xmt
en_drivr:
                ld      !r7, #sw5xmt
                ld      !r0, !rC
                lde     @!!r6, !r0      ;driver is now on (unless diag)
                nop
                ld      !r0, #xmtinit   ;wait 1.5 bit times
                lde     @!!r6, !r0      ;turn off driver (pulse was sent)
                ld      !r0, !rC        ;now get xmt setup value again
                or      !r0, #xmten     ;while waiting 1.6 bit times 
                lde     @!!r6, !r0      ;before enabling driver and xmtr for pkt
                ld      !r0, #lead_flgs ;set up constant for leading flg xmt
wlflgs:
                djnz    !r0, wlflgs              ;wait for flags to xmt
                ld      !r7, #sw0cmd            ;r6r7 ptr to cmd reg
                ld      !r0, #rtcrc
                lde     @!!r6, !r0              ;reset xmt crc gen.
;start transmitting bytes here
                ld      !r0, @!rD               ;get 1st byte from lap area
                lde    @!!scc_wbuf, !r0          ;write to scc
                lde     @!!r6, !r5              ;reset xmt undrn ltch so crc can
                                                ;transmit
;check for single byte xmit - diag mode is only case
                tm      bus_stat1, #scc_diag
                jr      nz, w_crcstart          ;go to crc xmit loop
; start write loop for remaining two lap header bytes
                ld      !r5, #2                 ;setup cntr for remaing lap byts
wait_lbufemp:
                lde     !rC,@!!scc_sts0          ;get write status
                tm      !rC, !r4                ;r4 has bufemp mask
                jr      z, wait_lbufemp
;write next chars from lap area - source and control bytes
                inc     !rD                     ;bump lap data ptr
                ld      !r0, @!rD               ;get next byte
                lde    @!!scc_wbuf, !r0          ;to scc
                djnz    !r5, wait_lbufemp
;now write the rest of the data
                tm      bus_stat1, #lap_only    ;only xmt lap?
                jr      nz, w_crcstart           ;yes if jump
wait_dbufemp:
                lde     !rC,@!!scc_sts0
                tm      !rC, !r4
                jr      z, wait_dbufemp
;write data chars
                lde     !r0,@!!xmtbuf            ;get char from RAM
                lde    @!!scc_wbuf, !r0          ;write to scc
                incw    xmtbuf
                decw    bytecnt
                jr      nz, wait_dbufemp
;done with data - now wait for crc to start, then end
w_crcstart:
                lde     !rC,@!!scc_sts0
                tm      !rC, #tur_eom           ;check for xmt undrn/eom -
                                                ;indicates crc has started out
                jr      z, w_crcstart
w_crcend:
                lde     !rC,@!!scc_sts0
                tm      !rC, !r4                ;wait for xmt buf empty -
                jr      z, w_crcend             ;indicates end of crc

;set up to disable xmtr while ending flag transmits
                ld      !r7, #sw5xmt            ;set r6r7 for scc xmt reg
                ld      !r0, #xmtr_off          ;turn off xmtr, leave RTS on
                tm      bus_stat1, #sccdiag
                jr      z, dis_xmtr
                and     !r0, #$FF - DTR - RTS  ;clear DTR,RTS if diag mode
dis_xmtr:
                lde     @!!r6, !r0
                ld      !r0, #twobyt            ;FM0 "1's" now xmitting
w_twobyt:
                djnz    !r0, w_twobyt           ;xmt two bytes of FM0 "1's"
; now shut off RTS, set DTR to disable xmt data for normal and diag modes, resp.
                ld      !r0, #xmtinit           ;initialization val. for xmt reg
                lde     @!!r6, !r0
; enable receiver for subsequent packet 
                ld      !r7, #sw3rcv
                ld      !r0, #rcven
                lde     @!!r6, !r0              ;receiver now enabled
                or      bus_stat1, #msg_sent    ;set status
                jp      tpack_ret

                .page

;===========================================================================
; rpack routine
;
; Receive packet.  Waits for a packet addressed to Widget's node number,
; determined and set by another level.  The amount of time routine waits is set
; by a higher level as a two-byte count value, where each count represents
; 200us.  If a properly addressed packet is received prior to the timeout,
; the first three bytes of the packet (the header) are checked as follows:
; If the first byte indicates a broadcast, the packet is saved if d_busy=0
; (idle state) and dumped if d_busy=1 (not idle).  The 'broadcast' status bit
; is set.  If not a broadcast, and state is not idle, the next byte (source
; node number) is checked for the correct value.  This check is skipped if
; state is idle.  Next the third (control) byte is checked against two possible
; values.  If all checks are correct, the remainder of the packet is saved in
; RAM at the location passed to the routine; otherwise the packet is dumped
; (read but not saved).  In any case the header bytes tested and correctly
; compared are saved in the lap header area of the Z8 registers.  Status
; bits are set to indicate whether packet was saved or dumped.
;
; The packet is checked for crc and overrun errors and there is a 5 sec.
; timeout if the routine gets hung after the 1st character is detected.
; Appropriate status bits are set.  The total byte count may be computed
; from the ending address in rErF (receive buffer ptr), but is not computed
; by rpack.
;
; INPUTS: 
; 1. Widget node number stored in scc chip register
; 2. timeout value for packet reception in rCrD: # of 200us time increments
; 3. d_busy bit in bus_stat1 (idle/not idle state)
; 4. expected source byte in r1
; 5. expected control byte in rA. 
; 6. pointer to receive buffer in rErF
;
; OUTPUTS:
; 1. Bus_stat1: msg_rcvd bit set if all header bytes are as expected and 
;               end of packet is detected.
; 2. bus_stat3: scc_timout if routine hangs
;               rorerr if receiver overrun is detected
; 3. bus_stat4: rcv_timout set if timeout occurs before 1st byte of pkt is rcvd
;               typ_mismatch set if a byte of the header does not match 
;               expected value. (Also set on rejected broadcasts)
;               scc_ crcerr set if one occurs
;
; REGISTERS:
; r0  : temp storage
; r1  : expected value for source byte
; r2r3: ptr to scc status register 0, scc_sts0hi,lo
; r4  : mask for char avail in status reg 0
; r5  : mask for eof or rcvr overrun, and temp storage
; r6r7: ptr to scc cmd reg (sw0cmd), rcv control (sw3rcv), and status reg 1
;       (scc_sts1hi,lo)
; r8r9: ptr to scc on-chip receive buffer, scc_rbuf, (top of rcv FIFO)
; rA  : expected value for control byte
; rCrD: timeout value for packet detection, and temp. storage
; rErF: ptr to receive buffer in RAM
;
;=========================================================================

                .page

rpack:
; load registers
                srp     #wrk_abtr       ;set working set for rpack
                tm      bus_stat1, #l_busy      ;check for link-level busy
                jr      nz, rp_fast     ;skip load of reg's already setup
; by tpack, plus receiver initialization to get fast response when l_busy=1
                ld      !scc_sts0hi, #.hibyte. sccbank
                ld      !scc_sts0lo, #sr0sts     ;scc status reg 0 ptr
                ld      !r6, #.hibyte. sccbank  ;scc pointer, hi byte
                ld      !r7, #sw3rcv            ;rcv mode reg
                ld      !scc_rbufhi, #.hibyte. sccbank
                ld      !scc_rbuflo, #sr8buf     ;scc rcv buffer
; Flush FIFO, disable rcvr, and reset error flags if not diagnostic mode
                tm      bus_stat1, #sccdiag
                jr      nz, rp_fast     ;skip rcvr init if diag.
                call    rcv_clr         ;init rcvr (disabled)
; now enable receiver for incoming packets
                ld      !r7, #sw3rcv
                ld      !r0, #rcven
                lde     @!!r6, !r0      ;enabled            
; enter here if l_busy = 1: rcvr was enabled by tpack
rp_fast:
                ld      !r5, #eof + ror ;set up masks
                ld      !r4, #rchar
                ld      Dmt_Counter, #.hibyte. Dmt_Val
                ld      Dmt_Counter+1, #.lowbyte. Dmt_Val  ;set up 5 sec. dmt
                clr     !r0                                ;for later
                call    T1poll_ab       ;start 200 us timer; r0=0 --> rpack call
                ld      !r7, #sr1sts    ;r7 now points to status reg 1
wait_1stchar:
                lde     !r0,@!!scc_sts0
                tm      !r0, !r4
                jr      nz, got_1st
                tm      Irq, #Timer1
                jr      z, wait_1stchar
                and     Irq, #$FF - Timer1      ;clear old Irq
                decw    !!rC                    ;bump rcv timeout counter
                jr      nz, wait_1stchar
                or      bus_stat4, #rcv_timout  ;set status
                call    T1_restore              ;set T1 for 10ms
                jr      rcv_exit
got_1st:
                lde     !r0, @!!scc_rbuf        ;read 1st char
                call    T1_restore              ;start dead bus timeout
                or      bus_stat1, #sccinten    ;sset inten bit
                ei
                clr     !rD             ;clear reg that will hold scc_sts1 since
;scc_sts1 is not saved during read of lap header.
                ld      our_node, !r0           ;save in lap area
                cp      !r0, #$FF               ;broadcast?
                jr      nz, get_src             ;no if taken
                or      bus_stat1, #broadcast   ;set bit
                tm      bus_stat1, #d_busy
                jr      nz, dump_pkt            ;dump pkt if not idle.broadcast
get_src:
                lde     !r0,@!!scc_rbuf          ;source byte
                ld      their_node, !r0         ;save source byte
                tm      bus_stat1, #d_busy      ;are we in the middle of somthng
                jr      z, get_control          ;no if taken
;check source byte
                cp      !r0, !r1
                jr      nz, dump_pkt            ;dump if source not right
get_control:
                lde     !r0,@!!scc_sts0          ;sync up to control byte
                tm      !r0, !r4
                jr      z, get_control
got_control:
                lde     !rD,@!!scc_sts1          ;save eof+ror for later if diag.
                lde     !r0,@!!scc_rbuf          ;save control
                ld      lap_ctrl, !r0
                cp      !r0, !rA                ;ckeck against exp value
                jr      z, save_pkt
                jr      dump_pkt
;done with lap header - now get data bytes
wait_char:
                lde     !rC,@!!scc_sts0
                tm      !rC, !r4
                jr      z, wait_char
char_rdy:
                lde     !rD,@!!scc_sts1          ;get eof, overrun
                lde     !r0,@!!scc_rbuf          ;get char
                lde     @!!rcvbuf,!r0            ;save in ram
                incw    rcvbuf
save_pkt:
;this is entry point for loop coming from lap data reads
                tm      !rD, !r5                ;check eof or overrun
                jr      z, wait_char
                or      bus_stat1, #msg_rcvd    ;set status if done 
rcv_done:
                tm      !rD, #ror               ;check ovr bit
                jr      z, no_ovr
                or      bus_stat3, #rorerr      ;set bit
no_ovr:
                tm      !rD, #crc               ;check crc error
                jr      z, rcv_exit
                or      bus_stat4, #scc_crcerr
rcv_exit:
                di
                and     bus_stat1, #$FF - sccinten      ;clr inten bit
                srp     #wrk_absys              ;restore caller's reg set
                ret
;below is code for dump packet
wait_dchar:
                lde     !rC,@!!scc_sts0
                tm      !rC, !r4
                jr      z, wait_dchar
dchar_rdy:
                lde     !rD,@!!scc_sts1
                lde     !r0,@!!scc_rbuf
                incw    rcvbuf
dump_pkt:
;this is entry point for packet dump from lap data read code
                tm      !rD, !r5                ;eof+ovr?
                jr      z, wait_dchar
                or      bus_stat4, #typ_mismatch        ;set status for dump pkt
                jr      rcv_done                ;common exit


                .LSTOFF
