Falcon Processor Reworks for V2 artwork RG and DGS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ECO#1 5/26/88 PROC. initialize flop controling address phase to main register memories. Bend up C6-10 Add wire C6-10 to H20-19 RESET ------------------------------------------------------------------------------- ECO#2 MEM. BNU-ADDR0 thru 8 not run to Config PROM ADD D34.2 TO A16.10 ADR0 ADD D34.5 TO A16.9 ADR1 ADD D34.6 TO A16.8 ADR2 ADD D34.9 TO A16.7 ADR3 ADD D34.12 TO A16.6 ADR4 ADD D34.15 TO A16.5 ADR5 ADD D34.16 TO A16.4 ADR6 ADD D34.19 TO A16.3 ADR7 ADD C28.2 TO A16.25 ADR8 ------------------------------------------------------------------------------- ECO#4 MEM ICACHE_XPHASE LIFT PIN 5 OF ALL SPY IREG CHIPS D26,E26,F26,G26,D27,E27,F27,G27 CONNECT ALL TO P5A.30 ICACHE_XPHASE ------------------------------------------------------------------------------- ECO#5 PROC. ICACHE_XPHASE FROM K11 PAL ICSEQ WAS PULLED FROM WRONG PIN, SHOULD BE 14 NOT 18. 5/31/88 LIFT PIN 18 OK K11 AND PIN 2 OF K13. CONNECT TOGETHER LIFTED PINS. CONNECT WIRE TO P5.30 FROM K11.14 ------------------------------------------------------------------------------- PROC CHANGE MFO-PAL NOW MFO-V2 ------------------------------------------------------------------------------- ECO#6 MEM. TERMINATOR SCREWWED UP H9.12 TO J1.10 MAP WRITE H9.11 TO C19.13 GC WE C20.13 TO H9.10 TRANSPORTER WE ------------------------------------------------------------------------------- ECO#7 MEM. GROUND PD_MEMCTL AT SIP (TOO MUCH LOAD) GROUND C17B PIN 2. 6/1/88 ------------------------------------------------------------------------------- ECO#8 MEM. PARALLEL ENTRY COUNTER FOR HISTORY RAM SHOULD GO TO PULLUP CUT PIN 12 ON BOTH J23 AND J24, SHORT PIN TO PIN 14. ------------------------------------------------------------------------------- 6/22/88 MEM prevent traps attempting to happen when spy single stepping machine. It would wedge. ECO#9 Add I13-7 to J22-16 SPY-ENABL Refrotz TRAPE PAL new version is 5. ------------------------------------------------------------------------------- 7/6/88 PROC. widen write pulse to register memories REG-WR~ . It was only 10ns!. Uses 74AS08 section at D7.11 ECO#10 Lift C13.10 Add A7.13 to D7.12 and D7.13 Add D7.11 to C13.10 (pin). ------------------------------------------------------------------------------- 7/13/88 PROC. modify destination return detect comparitor. This was yet another rev1 rework that didnt make it ECO#11 Bendup F19-2, F19-3, F19-4 Add leg F19-2 to leg F19-3 to leg F19-4 to F19-5 (GND) ------------------------------------------------------------------------------- 7/1/88 MEM. ECO#12 bendup D31.15 BNUROPCP bendup D31.14 BNUROPC add D30.15 to D31.15 etch hook back up to correct decoder. add D30.14 to D31.14 etch ------------------------------------------------------------------------------- 7/1/88 MEM. ECO#13 bendup I3.14 FDEST1 PAL this was W-TRAP on prints. add resistor 1K 1/8 or 1/4 watt I10.3 and I10.14 pull up old WTRAP line ------------------------------------------------------------------------------- 6/7/88 PROC HALT ECO not in ECO#14 add H17.7 to P5B.15 (H17.7 and G20.19 are already connected) ------------------------------------------------------------------------------- 6/7/88 MEM HALT ECO not in ECO#15 bendup K28.14 was ground add K28.14 to P5B.15 ------------------------------------------------------------------------------- manufacturing defect proto board set 1. (partial) shorted runs PROC board. D-JUMP* run shorted to C-ALUOP. Rerun D-JUMP* bendup C33.9, bendup G31.4 connect them. Notes re terminator screwup: (this was checked. it is believed ECO#6 is sufficient, BUT keep this around) the dip resistor in h9 somehow got completely the wrong pinout!! This resulted in having the same pin on more than one run!! Fortunately, the vendor pc program ignored one of the runs, thus failing to hook both runs inextricably together. the following pins may be affected: h9.5 one unnamed run to I13.15, ok pal output for map-write* h9.6 one unnamed run to I13.16, ok pal output for gc-we* h9.7 one unnamed run to i13.18, ok pal output for transp-we* h9.10 no connect transp-we* in fact comes out here. h9.11 no connect gc-we* in fact comes out here. h9.12 no connect map-write* in fact comes out here. h9.13 wirelist indicates both on BLM-A9 and MAP-WRITE* Is on BLM-A9. is not on MAP-WRITE* run. h9.14 wirelist indicates both on BLM-A8 and GC-WE* h9.15 wirelist indicates both on ALM-A9 and TRANSP-WE* ;observed marginalities in the design enumerated!! (1) MEM: MFO decode print. 2 AS805 gates (min delay 1 ns!, max 4) used to delay clock input to FDEST1, FDEST2 B series PALs. I/O pin used. Appears to generate negative hold time. (2) MEM: memory-control PALS CD_MMCTL (delayed clock) input to RAS PALS. (3) write pulse width to main data registers needs delay line (4) clock freeze circuit (5) [performace issue] cache. (6) is a better clock driver possible? ;notes re mid-cycle clocking on the MEM board: some clocks are not generated according to standard scheme and thus significantly later and subject to greater clock skew than they should be. However, the critical edge for these is in mid-cycle, which should prevent lossage due to clock skew (potentially, crosstalk could be a problem tho). In particular: ;the following come from the FDEST2 PAL, which is clocked on C2-MFO. ; NB. ;W-VMA destination chips are AS841, required hold time 2.5ns chips clocked by W-VMA which comes off a AS1004 from W-VMA~, which comes from PAL. PAL equation WVMA := . * /C_PROC * This means write pulse happens in first half of processor clock. PAL output delay (B series) is typ 8, max 12. D series is typ 8 max 10. AS1004 min 1 max 6. inputs are MFOn. MFOn are driven by F399s, clock-to-output (3.0 min, 10.0max) on the processor board. They are clocked by C-OUTREG, which is standard. propagation is across connector, directly to VMA, MD. protection against clock skew is due to latch occuring in middle of cycle. ;W-MD destination chips are F374. required hold time 2ns. chips clocked by W-MD~. this asserts in the first half cycle, so clocks on rising edge at mid-cycle. others (usec clock, etc, are not as critical ;notes re usage of MFI bus the MFI bus is used both to read functional sources and to transfer memory data to the processor during a cache miss. Normally the selectors are positioned to read a functional source. If a cache miss occurs: (1) ICACHE-WMODE on processor is asserted via direct input to JK FF. (2) one gate later, ICACHE+LOAD~ asserts (3) DISABLE~ output of MFO pal asserts (4) propagates over connector to MEM board to FSOURCE pal (5) MMFIO+IN~ (an output of the FSOURCE pal) deasserts (6) F244 enables connected to MMFIO+IN~ disable. meantime, ICACHE-LOAD~ goes across connector thru AS806 and AS1004 to enables of 244's