IREG SIGNAL NAMES Bit Number Signal ---- ALU BYTE JUMP DISPATCH ______________________________________________________________________________________________ 63 IREG.63 (Parity.bit.3) IREG.63 (Parity.bit.3) IREG.63 (Parity.bit.3) IREG.63 (Parity.bit.3) ______________________________________________________________________________________________ 62 IREG.62 (Parity.bit.2) IREG.62 (Parity.bit.2) IREG.62 (Parity.bit.2) IREG.62 (Parity.bit.2) ______________________________________________________________________________________________ 61 IREG.61 (Parity.bit.1) IREG.61 (Parity.bit.1) IREG.61 (Parity.bit.1) IREG.61 (Parity.bit.1) ______________________________________________________________________________________________ 60 IREG.60 (Parity.bit.0) IREG.60 (Parity.bit.0) IREG.60 (Parity.bit.0) IREG.60 (Parity.bit.0)) ______________________________________________________________________________________________ 59 UINST.HALT UINST.HALT UINST.HALT UINST.HALT ______________________________________________________________________________________________ 58 IREG.58 (Uinst.clobbers.mem.subr) IREG.58 (Uinst.clobbers.mem.subr) IREG.58 (Uinst.clobbers.mem.subr) IREG.58 (Uinst.clobbers.mem.subr) ____________________________________________________________________________________________ 57 UINST.STATISTICS.BIT UINST.STATISTICS.BIT UINST.STATISTICS.BIT UINST.STATISTICS.BIT ______________________________________________________________________________________________ 56 UINST.ILONG UINST.ILONG UINST.ILONG UINST.ILONG ______________________________________________________________________________________________ 55 UINST.SLOW.DESTINATION UINST.SLOW.DESTINATION UINST.SLOW.DESTINATION UINST.SLOW.DESTINATION ______________________________________________________________________________________________ 54 UINST.MACRO.STREAM.ADVANCE.UNLESS.NOOP UINST.MACRO.STREAM.ADVANCE.UNLESS.NOOP UINST.MACRO.STREAM.ADVANCE.UNLESS.NOOP UINST.MACRO.STREAM.ADVANCE.UNLESS.NOOP ______________________________________________________________________________________________ 53 UINST.MD.TO.MACRO.IR.ENABLE UINST.MD.TO.MACRO.IR.ENABLE UINST.MD.TO.MACRO.IR.ENABLE UINST.MD.TO.MACRO.IR.ENABLE ______________________________________________________________________________________________ 52 UINST.MACRO.IR.DISPATCH.UNLESS.NOOP UINST.MACRO.IR.DISPATCH.UNLESS.NOOP UINST.MACRO.IR.DISPATCH.UNLESS.NOOP UINST.MACRO.IR.DISPATCH.UNLESS.NOOP ______________________________________________________________________________________________ 51 UINST.POP.J.AFTER.NEXT UINST.POP.J.AFTER.NEXT UINST.POP.J.AFTER.NEXT UINST.POP.J.AFTER.NEXT ______________________________________________________________________________________________ 50 Main.Uinst.50 (A.SOURCE.11) Main.Uinst.50 (A.SOURCE.11) Main.Uinst.50 (A.SOURCE.11) Main.Uinst.50 (Dispatch.base.adr.11) ______________________________________________________________________________________________ 49 Main.Uinst.49 (A.SOURCE.10) Main.Uinst.49 (A.SOURCE.10) Main.Uinst.49 (A.SOURCE.10) Main.Uinst.49 (Dispatch.base.adr.10) ______________________________________________________________________________________________ 48 Main.Uinst.48 (A.SOURCE.9) Main.Uinst.48 (A.SOURCE.9) Main.Uinst.48 (A.SOURCE.9) Main.Uinst.48 (Dispatch.base.adr.9) ______________________________________________________________________________________________ 47 Main.Uinst.47 (A.SOURCE.8) Main.Uinst.47 (A.SOURCE.8) Main.Uinst.47 (A.SOURCE.8) Main.Uinst.47 (Dispatch.base.adr.8) ______________________________________________________________________________________________ 46 Main.Uinst.46 (A.SOURCE.7) Main.Uinst.46 (A.SOURCE.7) Main.Uinst.46 (A.SOURCE.7) Main.Uinst.46 (Dispatch.base.adr.7) ______________________________________________________________________________________________ 45 Main.Uinst.45 (A.SOURCE.6) Main.Uinst.45 (A.SOURCE.6) Main.Uinst.45 (A.SOURCE.6) Main.Uinst.45 (Dispatch.base.adr.6) ______________________________________________________________________________________________ 44 Main.Uinst.44 (A.SOURCE.5) Main.Uinst.44 (A.SOURCE.5) Main.Uinst.44 (A.SOURCE.5) Main.Uinst.44 (Dispatch.base.adr.5) ______________________________________________________________________________________________ 43 Main.Uinst.43 (A.SOURCE.4) Main.Uinst.43 (A.SOURCE.4) Main.Uinst.43 (A.SOURCE.4) Main.Uinst.43 (Dispatch.base.adr.4) ______________________________________________________________________________________________ 42 Main.Uinst.42 (A.SOURCE.3) Main.Uinst.42 (A.SOURCE.3) Main.Uinst.42 (A.SOURCE.3) Main.Uinst.42 (Dispatch.base.adr.3) ______________________________________________________________________________________________ 41 Main.Uinst.41 (A.SOURCE.2) Main.Uinst.41 (A.SOURCE.2) Main.Uinst.41 (A.SOURCE.2) Main.Uinst.41 (Dispatch.base.adr.2) ______________________________________________________________________________________________ 40 Main.Uinst.40 (A.SOURCE.1) Main.Uinst.40 (A.SOURCE.1) Main.Uinst.40 (A.SOURCE.1) Main.Uinst.40 (Dispatch.base.adr.1) ______________________________________________________________________________________________ 39 Main.Uinst.39 (A.SOURCE.0) Main.Uinst.39 (A.SOURCE.0) Main.Uinst.39 (A.SOURCE.0) Main.Uinst.39 (Dispatch.base.adr.0) ______________________________________________________________________________________________ 38 Main.Uinst.38 (M.source.6) (M.SOURCE.ADDRESS.6 [M.source.functional]) Main.Uinst.38 (M.source.6) " " Main.Uinst.38 (M.source.6) " " Main.Uinst.38 (M.source.6) " " ______________________________________________________________________________________________ 37 Main.Uinst.37 (M.source.5) (M.SOURCE.ADDRESS.5 [M.source.functional.5]) Main.Uinst.37 (M.source.5) " " Main.Uinst.37 (M.source.5) " " Main.Uinst.38 (M.source.5) " " ______________________________________________________________________________________________ 36 Main.Uinst.36 (M.source.4) (M.SOURCE.ADDRESS.4 [M.source.functional.4]) Main.Uinst.36) M.source.4 " " Main.Uinst.36 (M.source.4) " " Main.Uinst.36 (M.source.4) " " ______________________________________________________________________________________________ 35 Main.Uinst.35 (M.source.3) (M.SOURCE.ADDRESS.3 [M.source.functional.3]) Main.Uinst.35 (M.source.3) " " Main.Uinst.35 (M.source.3) " " Main.Uinst.35 (M.source.3) " " _____________________________________________________________________________________________ 34 Main.Uinst.34 (M.source.2) (M.SOURCE.ADDRESS.2 [M.source.functional.2]) Main.Uinst.34 (M.source.2) " " Main.Uinst.34 (M.source.2) " " Main.Uinst.34 (M.source.2) " " ______________________________________________________________________________________________ 33 Main.Uinst.33 (M.source.1) (M.SOURCE.ADDRESS.1 [M.source.functional.1]) Main.Uinst.33 (M.source.1) " " Main.Uinst.33 (M.source.1) " " Main.Uinst.33 (M.source.1) " " ______________________________________________________________________________________________ 32 Main.Uinst.32 (M.source.0) (M.SOURCE.ADDRESS.0 [M.source.functional.0]) Main.Uinst.32 (M.source.0) " " Main.Uinst.32 (M.source.0) " " Main.Uinst.32 (M.source.0) " " ______________________________________________________________________________________________ 31 Main.Uinst.31 (Uinst.opcode.1) Main.Uinst.31 (Uinst.opcode.1) Main.Uinst.31 (Uinst.opcode.1) Main.Uinst.31 (UINST.OPCODE.1) ______________________________________________________________________________________________ 30 Main.Uinst.30 (Uinst.opcode.0) Main.Uinst.30 (Uinst.opcode.0) Main.Uinst.30 (Uinst.opcode.0) Main.Uinst.30 (UINST.OPCODE.0) ______________________________________________________________________________________________ 29 Main.Uinst.29 (NC) Main.Uinst.29 (Byte.Mask.rotate) Main.Uinst.29 (Jump.adr.15) Main.Uinst.29 (DISPATCH.TEST.MAP.1) ______________________________________________________________________________________________ 28 Main.Uinst.28 (NC) Main.Uinst.28 (Byte.S.rotate) Main.Uinst.28 (Jump.adr.14) Main.Uinst.28 (DISPATCH.TEST.MAP.0) ______________________________________________________________________________________________ 27 Main.Uinst.27 (NC) Main.Uinst.27 (NC) Main.Uinst.27 (Jump.adr.13) Main.Uinst.27 (DISPATCH.WRITE.VMA) ______________________________________________________________________________________________ 26 Main.Uinst.26 (Dest.12) (Dest.A) Main.Uinst.26 (Dest.12) (Dest.A) Main.Uinst.26 (Jump.adr.12) Main.Uinst.26 (DISPATCH.PUSH.OWN.ADDRESS) ______________________________________________________________________________________________ 25 Main.Uinst.25 (Dest.11) (A.dest.address.11 [Dest.funct.aux]) Main.Uinst.25 (Dest.11) " " Main.Uinst.25 (Jump.adr.11) Main.Uinst.25 (DISPATCH.DISPATCH.CONSTANT.11) ______________________________________________________________________________________________ 24 Main.Uinst.24 (Dest.10) (A.dest.address.10 [Dest.function.4]) Main.Uinst.24 (Dest.10) " " Main.Uinst.24 (Jump.adr.10) Main.Uinst.24 (DISPATCH.DISPATCH.CONSTANT.10) ______________________________________________________________________________________________ 23 Main.Uinst.23 (Dest.9) (A.dest.address.9 [Dest.function.3]) Main.Uinst.23 (Dest.9) " " Main.Uinst.23 (Jump.adr.9) Main.Uinst.23 (DISPATCH.DISPATCH.CONSTANT.9) ______________________________________________________________________________________________ 22 Main.Uinst.22 (Dest.8) (A.dest.address.8 [Dest.function.2]) Main.Uinst.22 (Dest.8) " " Main.Uinst.22 (Jump.adr.8) Main.Uinst.22 (DISPATCH.DISPATCH.CONSTANT.8) ______________________________________________________________________________________________ 21 Main.Uinst.21 (Dest.7) (A.dest.address.7 [Dest.function.1]) Main.Uinst.21 (Dest.7) " " Main.Uinst.21 (Jump.adr.7) Main.Uinst.21 (DISPATCH.DISPATCH.CONSTANT.7) ______________________________________________________________________________________________ 20 Main.Uinst.20 (Dest.6) (A.dest.address.6 [Dest.function.0]) Main.Uinst.20 (Dest.6) " " Main.Uinst.20 (Jump.adr.6) Main.Uinst.20 (DISPATCH.DISPATCH.CONSTANT.6) ______________________________________________________________________________________________ 19 Main.Uinst.19 (Dest.5) (A.dest.address.5 [M.dest.address.5]) Main.Uinst.19 (Dest.5) " " Main.Uinst.19 (Jump.adr.5) Main.Uinst.19 (DISPATCH.DISPATCH.CONSTANT.5) ______________________________________________________________________________________________ 18 Main.Uinst.18 (Dest.4) (A.dest.address.4 [M.dest.address.4]) Main.Uinst.18 (Dest.4) " " Main.Uinst.18 (Jump.adr.4) Main.Uinst.19 (DISPATCH.DISPATCH.CONSTANT.4) ______________________________________________________________________________________________ 17 Main.Uinst.17 (Dest.3) (A.dest.address.3 [M.dest.address.3]) Main.Uinst.17 (Dest.3) " " Main.Uinst.17 (Jump.adr.3) Main.Uinst.17 (DISPATCH.DISPATCH.CONSTANT.3) ______________________________________________________________________________________________ 16 Main.Uinst.16 (Dest.2) (A.dest.address.2 [M.dest.address.2]) Main.Uinst.16 (Dest.2) " " Main.Uinst.16 (Jump.adr.2) Main.Uinst.15 (DISPATCH.DISPATCH.CONSTANT.2) ______________________________________________________________________________________________ 15 Main.Uinst.15 (Dest.1) (A.dest.address.1 [M.dest.address.1]) Main.Uinst.15 (Dest.1) " " Main.Uinst.15 (Jump.adr.1) Main.Uinst.15 (DISPATCH.DISPATCH.CONSTANT.1) ______________________________________________________________________________________________ 14 Main.Uinst.14 (Dest.0) (A.dest.address.0 [M.dest.address.0]) Main.Uinst.14 (Dest.0) " " Main.Uinst.14 (Jump.adr.0) Main.Uinst.14 (DISPATCH.DISPATCH.CONSTANT.0) ______________________________________________________________________________________________ 13 Main.Uinst.13 (MISC.FCTN.1) Main.Uinst.13 (MISC.FCTN.1) Main.Uinst.13 (MISC.FCTN.1) Main.Uinst.13 (MISC.FCTN.1) ______________________________________________________________________________________________ 12 Main.Uinst.12 (MISC.FCTN.0) Main.Uinst.12 (MISC.FCTN.0) Main.Uinst.12 (MISC.FCTN.0) Main.Uinst.12 (MISC.FCTN.0) ______________________________________________________________________________________________ 11 Main.Uinst.11 (IR.ALU.output.bus.control.2) Main.Uinst.11 (Byte.length.5) Main.Uinst.11 (Jump.Macro.LC.increment) Main.Uinst.11 (DISPATCH.LEFT) ______________________________________________________________________________________________ 10 Main.Uinst.10 (IR.ALU.output.bus.control.1) Main.Uinst.10 (Byte.length.4) Main.Uinst.10 (Jump.R) Main.Uinst.10 (DISPATCH.LENGTH.4) ______________________________________________________________________________________________ 09 Main.Uinst.9 (IR.ALU.output.bus.control.0) Main.Uinst.9 (Byte.length.3) Main.Uinst.9 (Jump.P) Main.Uinst.9 (DISPATCH.LENGTH.3) ______________________________________________________________________________________________ 08 Main.Uinst.8 (IR.ALU.control.5) Main.Uinst.8 (Byte.length.2) Main.Uinst.8 (Jump.N) Main.Uinst.8 (DISPATCH.LENGTH.2) ______________________________________________________________________________________________ 07 Main.Uinst.7 (IR.ALU.control.4) Main.Uinst.7 (Byte.length.1) Main.Uinst.7 (Jump.invert) Main.Uinst.7 (DISPATCH.LENGTH.1) ______________________________________________________________________________________________ 06 Main.Uinst.6 (IR.ALU.control.3) Main.Uinst.6 (Byte.length.0) Main.Uinst.6 (Jump.test.bit) Main.Uinst.6 (DISPATCH.LENGTH.0) ______________________________________________________________________________________________ 05 Main.Uinst.5 (IR.ALU.control.2) Main.Uinst.5 (Byte.position.5) Main.Uinst.5 (Jump.test.bitnum.5 [Jump.condition.number.5]) Main.Uinst.5 (DISPATCH.POSITION.5) ______________________________________________________________________________________________ 04 Main.Uinst.4 (IR.ALU.control.1) Main.Uinst.4 (Byte.position.4) Main.Uinst.4 (Jump.test.bitnum.4 [Jump.condition.number.4]) Main.Uinst.4 (DISPATCH.POSITION.4) ______________________________________________________________________________________________ 03 Main.Uinst.3 (IR.ALU.control.0) Main.Uinst.3 (Byte.position.3) Main.Uinst.3 (Jump.test.bitnum.3 (Jump.condition.number.3]) Main.Uinst.3 (DISPATCH.POSITION.3) ______________________________________________________________________________________________ 02 Main.Uinst.2 (IR.ALU.carry.in) Main.Uinst.2 (Byte.position.2) Main.Uinst.2 (Jump.test.bitnum.2 (Jump.condition.number.2]) Main.Uinst.2 (DISPATCH.POSITION.2) ______________________________________________________________________________________________ 01 Main.Uinst.1 (IR.ALU.carry.Q.control.1) Main.Uinst.2 (Byte.position.1) Main.Uinst.1 (Jump.test.bitnum.1 (Jump.condition.number.1]) Main.Uinst.2 (DISPATCH.POSITION.1) ______________________________________________________________________________________________ 00 Main.Uinst.0 (IR.ALU.carry.Q.control.0) Main.Uinst.0 (Byte.position.0) Main.Uinst.0 (Jump.test.bitnum.0 [Jump.condition.number.0]) Main.Uinst.0 (DISPATCH.POSITION.0) ______________________________________________________________________________________________