DEF HWORD DEF HPATT DEF HRNT HTEOL DEF *,I SKP *************** HI MEMORY ADDRESS TEST **************************** * * HADRT PERFORMS ADDRESS TEST BY * * (1) WRITING LOC ADDRESS INTO LOCATION FOR * ALL AVAILABLE MEMORY LOCATIONS * (2) READING AND TESTING ALL LOCATIONS * HADRT NOP LDA HB20 STA HHLTS SAVE HALT TYPE CLO INDICATE WRITING MEMORY LDA HFWA STORE ADDRESS INTO HAW1 STA A,I LOCATION CPA HLWA TEST FOR LAST ADDRESS JMP HAR EXIT INA NEXT ADDRESS JMP HAW1 HAR STO INDICATE READING MEMORY LDB HFWA INITIALIZE STB HADDR ADDRESS POINTER STB HHLD2 PATTERN HOLD LDB HADDR,I CPB HADDR ADDRESS = TO ADDRESS CONTENTS RSS JSB HER1 NO JSB HRST TEST FOR PGM RESTART LDB HADDR YES CPB HLWA LAST ADDRESS JMP HAW2 GO TO ADDRESS COMPLIMENT TEST INB INCREMENT JMP HAR+2 CONTINUE HAW2 CLO INDICATE WRITING MEMORY JSB HRST TEST FOR PGM RESTART LDB HFWA LOAD 1ST ADDRESS HAW3 LDA B LOAD A CMA COMPLIMENT ADDRESS STA B,I STORE TO LOCATION CPB HLWA TEST FOR LAST ADDRESS JMP HAR2 GO TO READ INB NEXT ADDRESS JMP HAW3 HAR2 STO INDICATE READING MEMORY LDB HFWA INITIALIZE HAR3 STB HADDR ADDRESS POINTER CMB STB HHLD2 PATTERN HOLD LDB HADDR,I CPB HHLD2 ADDRESS COMP = TO ADDRESS CONTS RSS JSB HER1 NO LDB HADDR RELOAD CURRENT ADDRESS CPB HLWA LAST ADDRESS JMP HADRT,I YES INB NO JMP HAR3 CONTINUE SKP **************** HI MEMORY PATTERN (ALT WD) TEST ******************* * * HSWRD PERFORMS ALTERNATE 1/0 PATTERN TEST * HSWRD NOP LDA HB30 STA HHLTS SAVE HALT TYPE LDA HJC1 SET UP STA HP0 PATTERN STA HR0 SELECTION CALL CCA STA HPFG CLEAR PATTERN CHG FLAG CLA CCB JSB HPTN CCA CLB JSB HPTN JMP HSWRD,I SKP **************** HI MEMORY PATTERN (WORD) TEST ********************* * * HWORD PERFORMS WORD PATTERN TESTING BY * * (1) WRITING PATTERN (WORSE CASE NOISE) INTO * MEMORY. PATTERN BASED ON CPU/MEMORY TYPE. * * (2) READING AND TESTING EACH LOCATION FOR * CORRECT PATTERN * * (3) SAVING PATTERN,WRITING,READING TESTING * COMPLIMENT OF ORIGNAL PATTERN AND RESTORING * ORIGNAL PATTERN * * (4) REPORTING ERRORS ENCOUNTERED DURING ALL TESTING * * (5) TEST IS PERFORMED TWICE, ONCE USING WORSE CASE * PATTERN AND SECOND TIME USING COMPLIMENT PATTERN * HWORD NOP LDA HB40 STA HHLTS SAVE HALT TYPE LDA HMFG DETERMINE SZA,RSS WHICH JMP HW0 PATTERN TO USE LDA HJC2 SET UP STA HP0 PATTERN STA HR0 SELECTION CALL JMP HW1 HW0 LDA HJC1 SET UP STA HP0 PATTERN STA HR0 SELECTION CALL HW1 CLA STA HPFG CLEAR PATTERN CHG FLAG CCB JSB HPTN PERFORM WORD PATTERN CCA CLB JSB HPTN PERFORM ALT WD PATTERN JMP HWORD,I EXIT SKP **************** HI MEMORY PATTERN (BIT) TEST ********************** * * HPATT PERFORMS BIT PATTERN TESTS * * (1) BIT 0 PATTERN * * (2) BIT 1 PATTERN * HPATT NOP LDA HJC1 SET UP STA HP0 PATTERN STA HR0 SELECTION CALL JSB HBITO PERFORM BITO TEST JSB HBIT1 PERFORM BIT1 TEST JMP HPATT,I EXIT SPC 2 * * HBITO IS SAME AS LWORD WITH THE EXCEPTION OF * * (1) PATTERN USED * * (2) TEST IS RUN 16 TIMES EACH TIME CHANGING PATTERN * HBITO NOP LDA HB50 STA HHLTS SAVE HALT TYPE LDA HBPT1 LDB HMFG SZB TEST FOR PATTERN TO BE USED LDA HBPT2 STA HBPTS INITIALIZE BIT O PATTERN LDA HDM16 STA HLPC INITIALIZE LOOP COUNT HBOO CLA STA HPFG CLEAR PATTERN CHG FLAG LDB HBPTS JSB HPTN PERFORM BIT O PATTERN LDA HBPTS CLB JSB HPTN PERFORM BIT O ALT PATTERN LDA HBPTS RAL CHANGE BIT O PATTERN STA HBPTS ISZ HLPC BUMP COUNT JMP HBOO CONTINUE JMP HBITO,I EXIT SKP * * HBIT1 IS THE SAME AS LBIT0 EXCEPT FOR INITIAL * PATTERN USED. * HBIT1 NOP LDA HB52 STA HHLTS SAVE HALT TYPE LDA HBPT2 LDB HMFG SZB TEST FOR PATTERN TO BE USED LDA HBPT1 STA HBPTS INITIALIZE BIT 1 PATTERN LDA HDM16 STA HLPC SET UP LOOP COUNT CLA STA HPFG CLEAR PATTERN CHG FLAG HBT10 CCA LDB HBPTS JSB HPTN PERFORM BIT 1 PATTERN LDA HBPTS CCB JSB HPTN PERFORM BIT 1 ALT PATTERN LDA HBPTS RAL CHANGE BIT 1 PATTERN STA HBPTS ISZ HLPC BUMP LOOP COUNT JMP HBT10 CONTINUE JMP HBIT1,I EXIT SPC 2 * * HPTN PERFORMS ACTUAL TEST BY * * (1) SAVING PATTERNS TO BE WRITTEN * * (2) WRITING MEMORY * * (3) READING/TESTING MEMORY * HPTN NOP STA HPTN1 SAVE PATTERN 1 STB HPTN2 SAVE PATTERN 2 CLO INDICATE WRITING MEMORY JSB HWT WRITE PATTERN STO INDICATE READING MEMORY JSB HRD READ AND TEST PATTERN JMP HPTN,I EXIT SKP * * HWT WRITES PATTERN INTO MEMORY BASED ON CPU/MEMORY * TYPE BEING TESTED * HWT NOP JSB HRST TEST FOR PGM RESTART LDA HFRST STA HADDR INITIALIZE FIRST ADDRESS HP0 JSB HACK CHECK ADR FOR PTN TYPE JMP HP1 LDA HPTN1 JMP HP1+1 HP1 LDA HPTN2 STA HADDR,I STORE PATTERN LDA HADDR CPA HLAST TEST FOR LAST ADR JMP HWT,I EXIT ISZ HADDR BUMP CURRENT ADR JMP HP0 CONTINUE SPC 2 * * HRD READS/TESTS MEMORY BASED ON PATTERN WRITTEN * HRD NOP JSB HRST TEST FOR PGM RESTART LDA HFRST STA HADDR INITIALIZE FRST ADDRESS HR0 JSB HACK CHECK ADR FOR PATTERN TYPE JMP HR1 LDA HPTN1 JMP HR1+1 HR1 LDA HPTN2 STA HGDS STA HHLD2 SAVE GOOD DATA LDB HADDR,I READ LOCATION CPB A PATTERN OK ? RSS JSB HER1 NO JSB HCMP YES, COMPLIMENT AND TEST PTN LDA HADDR CPA HLAST TEST FOR LAST ADR JMP HRD,I EXIT ISZ HADDR BUMP CURRENT ADR JMP HR0 CONTINUE SKP * * HACK DETERMINES PATTERN TO BE WRITTEN INTO MEMORY * BASED ON THE EQUATIONS DEINING WORSE CASE * PATTERN FOR A PARTICULAR CPU/MEMORY TYPE * HACK NOP LDA HPFG SZA TEST FOR PATTERN CHG JSB HSACK LDA HADDR AND HMS1,I AND ADDRESS WITH MASK 1 ALF,ALF RAL,RAL POSITION BITS STA HRNS1 JSB HPS LDA HMS2,I SZA TEST FOR ONE TERM JMP HACK1 NO LDA HMSV2 SZA TEST PARITY FOR "0" ISZ HACK JMP HACK,I EXIT HACK1 AND HADDR SZA,RSS TEST FOR T OR F JMP HACK2 F CLA,INA AND HMSV1 STA HMSV3 SAVE AND TERM 1 CLA JMP HACK3 HACK2 STA HMSV3 SAVE AND TERM 1 CLA,INA AND HMSV2 HACK3 STA HMSV4 SAVE AND TERM 2 IOR HMSV3 FORM OR OF TERM 1 & 2 SZA TEST FOR "0" ISZ HACK JMP HACK,I EXIT HMS1 OCT 0 TEMP STORAGE FOR MSK PTR HMS2 OCT 0 TEMP STORAGE FOR MSK PTR HMSV1 OCT 0 PARITY (T) HMSV2 OCT 0 PARITY (F) HMSV3 OCT 0 AND TERM 1 HMSV4 OCT 0 AND TERM 2 HMSK1 DEF * POINTER TO START OF 1ST MASK TBL OCT 41 2116A OCT 3 2116B OCT 140 2116C OCT 101 2115A OCT 101 2114A OCT 101 2114B OCT 140 2100A OCT 100 210XX OCT 40 OCT 40 OCT 40 OCT 40 OCT 40 OCT 40 OCT 40 HMSK2 DEF * POINTER TO START OF 2ND MASK TBL OCT 100 OCT 200 OCT 0 OCT 0 OCT 0 OCT 0 OCT 0 OCT 0 OCT 0 OCT 0 OCT 0 OCT 0 OCT 0 OCT 0 OCT 0 SPC 3 * * HSACK PERFORMS SECOND PATTERN GENERATION * FROM ADDRESS BITS IN TABLE FOR * VARIOUS CPU/MEMORIES * HSACK NOP LDA HACK STA HSACK FORM NEW EXIT LDA HSDS1,I PICK UP MASK AND HADDR AND ADDRESS BITS SZA TEST FOR "0" ISZ HSACK JMP HSACK,I EXIT HPFG OCT 0 HSDS1 OCT 0 HSDM1 DEF *+1 OCT 1 210X OCT 0 210XX SPC 2 HDACK NOP LDA HADDR LOAD CURRENT ADDRESS AND HMSK3 MASK BITS 0+5 CPA HMSK3 JMP HDACK,I EXIT SZA ISZ HDACK JMP HDACK,I EXIT HMSK3 OCT 101 HJC1 JSB HACK HJC2 JSB HDACK SKP * * HCMP SAVES CURRENT PATTERN,WRITES/READS/TESTS * COMPLIMENT PATTERN AND RESTORES OLD PATTERN * FOR EACH LOCATION TESTED * HCMP NOP LDA HGDS LOAD GOOD DATA CMA COMPLIMENT CURRENT PATTERN STA HHLD2 SAVE STA HADDR,I WRITE IT BACK LDB HADDR,I READ IT BACK CPB HHLD2 IS OK ? RSS JSB HER1 NO LDA HGDS RELOAD DATA STA HADDR,I WRITE IT BACK JMP HCMP,I EXIT HGDS OCT 0 SKP *************** HI MEMORY RANDOM NUM.TEST ************************* * * HRNT PERFORMS RANDOM PATTERN TESTING OF MEMORY * HRNT NOP LDA HB60 STA HHLTS SAVE HALT TYPE LDA HRN HRN0 STA HRNS INITIALIZE RNDM NO STORAGE STA HRNTS CLO INDICATE WRITING MEMORY LDA HFWA STA HADDR INITIALIZE 1ST ADDR HRN1 JSB HRNG GENERATE RNDM NUMBER STA HADDR,I STORE NUMBER IN TEST ADR LDA HADDR CPA HLWA LAST ADDR ? JMP *+3 ISZ HADDR BUMP ADDR JMP HRN1 NO STO INDICATE READING MEMORY LDA HFWA YES STA HADDR INITIALIZE 1ST ADDR LDA HRNTS STA HRNS INITIALIZE RNDM NO STORAGE HRN2 JSB HRNG GENERATE RNDM NUMBER LDB HADDR,I CPB HRNS TEST (ADR) RSS JSB HER1 BAD LDA HADDR GOOD CPA HLWA LAST ADDR ? JMP *+3 ISZ HADDR JMP HRN2 NO JSB HRST TEST FOR PGM RESTART NOP JMP *+2 JMP HRNT,I EXIT LDA HRNS JMP HRN0 HRN OCT 177777 RNDM NO HRNS OCT 0 RNDM NO STORAGE HRNTS OCT 0 SKP * * HRNG PERFORMS ACTUAL RANDOM NUMBER GENERATION * * ******** RANDOM PATTERN GENERATION ********************************* * * (1) INITIALIZE PATTERN (RPS _ 1'S) * * (2) AND OFF BITS 11,13,14,16 * * (3) FORM EXCLUSIVE OR OF BITS (PARITY SUM) * * (4) LEFT SHIFT RNDM PATTERN SHIFTING IN PARITY SUM * TO BIT O * * (5) TEST FOR ALL O'S AND DO (1) IF T, (6) IF F * * (6) EXIT * HRNG NOP JSB HRST TEST FOR PROGRAM RESTART LDA HRNS AND HRNM MASK NO FOR BITS 11,13,14,16 RAL POSITION BITS STA HRNS1 SAVE JSB HPS FORM PARITY LDA HRNS RAL SHIFT AND HBT0 ADA HMSV1 SZA,RSS TEST FOR "0" LDA HRN STA HRNS SAVE STA HHLD2 JMP HRNG,I HRNM OCT 132000 BIT MASK HBT0 OCT 177776 BIT O MASK SKP * * HPS GENERATES THE PARITY OF THE BITS IN RSN1 * GENERATOR IS A TOGGLING FLIPFLOP INITIALLY * CLEARED * HPS NOP LDA HDM7 STA HRCT INITIALIZE COUNT LDA HRNS1 CLB CLEAR FLOP HPS1 SLA,RSS JMP HPS2 CMB TOGGLE FLIP FLOP HPS2 RAL NEXT BIT ISZ HRCT LAST BIT JMP HPS1 NO SZB TEST FOR PARITY "0" JMP HPS3 "1" STB HMSV1 SAVE T.P. INB JMP HPS4 HPS3 CLB,INB STB HMSV1 SAVE T.P. CLB HPS4 STB HMSV2 SAVE F.P. JMP HPS,I EXIT HRNS1 OCT 0 HDM7 DEC -7 HRCT OCT 0 CTR STORAGE SKP * * HER1 IS THE COMMON ERROR REPORTING SUBROUTINE WHICH * * (1) CHECKS FOR ERROR HALT * * (2) FORMS HALT TYPE * * (3) CHECKS FOR ERROR TO BE PUT IN TABLE * HER1 NOP STB HHLD1 SAVE BAD DATA LDA HHLT IOR HHLTS OR IN HALT TYPE STA HHLT0 INA STA HHLT1 JSB HCHK CHECK TO SEE IF HLT REQUESTED HHLT0 HLT 10B LDA HADDR HHLT1 HLT 11B LDA HSAVA LDB HSAVB JMP HER1,I EXIT HHLD1 OCT 0 TEMP. STORAGE FOR BAD DATA HHLD2 OCT 0 TEMP. STORAGE FOR GOOD DATA SPC 3 * * HCHK CHECKS TO SEE IF ERROR HALT IS BEING REQUESTED * HCHK NOP STO SET OVERFLOW (ERROR) LIA SWR ALL ENTRIES CHECKED RAL,RAL SLA SUPPRESS ERROR HALT ? JMP HNHLT YES LDA HHLD2 LDB HHLD1 JMP HCHK,I NO HNHLT LDA HCHK ADA HA3 MODIFY RETURN ADDR JMP A,I RETURN HA3 OCT 3 SKP SKP * * RELOCATION ROUTINE * * RELOCATES LOWER PROGRAM MODULE (2-1777) TO UPPER MEMORY * MODULE(3500-5475). * UPPER NOP LDA B10 SAVE STA HHLTS HALT TYPE LDA H3500 SET STA PMOVE LIMITS OF LDB B2 THE MOVE LOOP4 EQU * LDA B,I TRANSFER STA PMOVE,I A WORD INB BUMP ISZ PMOVE POINTERS CPB B2000 DONE? RSS JMP LOOP4 NO LDA H3500 YES.REINITIALIZE STA PMOVE THE MOVE LDB B2 LIMITS LOOP2 EQU * LDA PMOVE,I COMPARE MOVED CPA B,I CONTENTS JMP NEXT1 OK.GO ON STB HSAVB SAVE B REG LDB B,I GET GOOD DATA SWP STA HHLD2 SAVE GOOD DATA STA HSAVA SAVE A REG JSB HER1 GO HALT FOR ERROR NEXT1 EQU * ISZ PMOVE BUMP INB POINTERS CPB B2000 DONE? JMP UPPER,I YES JMP LOOP2 NO SKP * * RELOCATION ROUTINE * * RELOCATES UPPER MEMORY MODULE (3500-5475) TO LOWER PROGRAM * MODULE(2-1777) * LOWER NOP LDA B10 SAVE STA HHLTS HALT TYPE LDA H3500 SET STA PMOVE MOVE LDB B2 LIMITS LOOP3 EQU * LDA PMOVE,I TRANSFER STA B,I A WORD LDA B,I COMPARE THE CPA PMOVE,I CONTENTS MOVED JMP NEXT2 OK.GO ON STB HSAVB SAVE B REG LDB PMOVE,I GET GOOD DATA SWP STA HHLD2 SAVE GOOD DATA STA HSAVA SAVE A REG JSB HER1 GO HALT FOR ERROR NEXT2 EQU * ISZ PMOVE BUMP INB POINTERS CPB B2000 DONE? JMP LOWER,I YES JMP LOOP3 NO PMOVE EQU HADDR B2 OCT 2 B2000 OCT 2000 B10 OCT 10 H3500 OCT 3500 * * * HINIT INITIALIZES INT LOC 4,5 * HINIT NOP LDA HLT4C STA 4B PRIME POWER INT LDA HJPE STA 5B PRIME P.E. INT JMP HINIT,I SKP * * HMPPE PARITY/MEMORY PROTECT INT HANDLER * HMPPE NOP STA HSAVA SAVE A STB HSAVB SAVE B LIA 5 SSA TEST FOR JMP *+3 MEMORY OCT 106005 PROTECT JMP HMP1+2 INT. AND HMSB READ ERROR ADR AND MASK OUT BT15 CMA,INA 2'S COMP OF P.E. ADDR IN A LDB HSTBL+2 ADB A SSB TEST FOR P.E. IN TEST AREA JMP HPGM PGM AREA LDA HHLD2 LOAD CURRENT PATTERN CPA HSAVB LOAD PARITY ERROR PATTERN JMP HMP1 ERROR IS BIT HMP0 STF 5 TURN ON PARITY LDA HSAVA RESTORE A LDB HSAVB RESTORE B JMP HMPPE,I EXIT HMP1 LDB HADDR LOAD ADDR HLT 13B PARITY ERROR JMP HMP0 EXIT HPGM LIA 5 AND HMSB LDB A,I HLT 7B A= ADDR B= (ADDR) STB A,I RESTORE (P.E. ADDR) STF 5 JMP HPE2 RESTART HSAVA OCT 0 SAVE AREA HSAVB OCT 0 SAVE AREA HLT4C HLT 4,C HJPE JSB 3B,I FWAM EQU * END