* 
B56P1 DEF BE561+10
B56P2 DEF BE562+10
BE56  ASC 22,E056 DATA TRFER ERR ON SC XX, BUS SW SC VV/
BE561 ASC 14,      EXPECTED DATA YYYYYY/
BE562 ASC 14,      ACTUAL DATA   ZZZZZZ/
* 
* 
*       FLAG ERROR. CONCATENATE FLAG ERROR MESSAGE STRING 
*       & OUTPUT ERROR MESSAGE E043 
* 
T08ER NOP 
      LDA BSSCX    LOAD SWITCH SC1
      JSB N2AO     CONVERT FAILING SC TO ASCII & STUFF
      STA BE43E      INTO MESSAGE 
* 
      LDB T08CW    GET CONTR WORD & SCAN FOR INSTR SPECIFIED
      LDA B43AQ      (BITS 0-3) PUT THE APPROP. DEF STATE-
      JSB .43CN         MENT INTO THE 1. LINE OF THE ERROR
      STA DF101           MESSAGE E043
* 
      LDB T08CW    SCAN FOR PREDICATE SPECIFIED (BITS 4-7) &
      BRS,BRS        PUT INTO 1. LINE OF E043 
      BRS,BRS 
      LDA B43FQ 
      JSB .43CN 
      STA DF102 
* 
      LDB T08CW    SCAN FOR PREPOSITION SPECIFIED (BITS 8-9) &
      BLF,BLF        PUT INTO 2. LINE OF E043 
      LDA B43KQ 
      JSB .43CN 
      STA DF103 
* 
      LDB T08CW    SCAN FOR ADJECTIVE SPECIFIED (BITS 10-11)
      BLF,RBL 
      RBL 
      LDA B43MQ 
      JSB .43CN 
      LDB T08CW    GET CONTROL WORD AGAIN & CHECK IF A
      BLF,SLB        2-LINE MESSAGE IS REQUIRED 
      JMP *+4      NO 3-LINE MESSAGE
      AND P7777    YES, REMOVE INDIR. BIT IN LAST DEF STATEM. 
      STA DF104    PUT INTO 2. LINE OF E043 & 
      JMP E043-2     GO TO PRINT
* 
      SKP 
* 
      STA DF104    PUT INTO 2. LINE OF E043 
      LDA B43PQ    START WITH 3. LINE OF ERROR MESSAGE
      RBR          BRING BIT 13 TO BIT POS 0
      JSB .43CN 
      LDB T08CW    WAS THE TERM "NOT" REQUESTED (BIT 13)? 
      RBL,RBL 
      SSB 
      JMP *+2      YES, DON'T REMOVE INDIR. BIT IN DEF STATEM.
      AND P7777    NO, REMOVE INDIRECT BIT IN DEF STATEM. 
      STA DF105    STORE DEF
* 
* 
      LDA T08CW    LOAD A-REG WITH INSTR & B-REG WITH SC
      LDB BSSC1 
E043  JSB ERMS,I   PRINT ERROR MESSAGE E043 WITH
      DEF BE43,I    HALT NUMBER 
DF101 NOP            INSTRUCTION TYPE 
      DEF BE43E,I     SC & "INSTR." 
DF102 NOP              PREDICATE
      DEF BE43J,I       "EXTENDER"
DF103 NOP                 "TO"/"F." 
DF104 NOP                  "THIS/OTHER CPU" W/WO TERMIN BIT 
      DEF BE43O,I           "WITH SWITCH" 
DF105 NOP                    "NOT"/"IN NEUTRAL" 
      DEF BE43Q               "IN NEUTRAL"
      JMP T08ER,I 
      JMP T08ER,I 
* 
.43CN NOP          IS THE LSB IN THE CONTROL WORD SET?
      SLB,BRS 
      JMP *+3      YES
      INA          NO, INCREMENT DEF POINTER AND REPEAT 
      JMP *-3 
      LDA A,I      LOAD MESSAGE POINTER 
      IOR SW15     ATTACH INDIR. CONCATINATION BIT & RETURN 
      JMP .43CN,I 
* 
* 
T08CW OCT 0 
T08A  OCT 0 
T08B  OCT 0 
* 
B43AQ DEF B43AP    POINTERS TO MESSAGE POINTERS 
B43FQ DEF B43FP 
B43KQ DEF B43KP 
B43MQ DEF B43MP 
B43PQ DEF B43PP 
* 
      SKP 
* 
B43AP DEF BE43A    MESSAGE POINTERS 
      DEF BE43B 
      DEF BE43C 
      DEF BE43D 
B43FP DEF BE43F 
      DEF BE43G 
      DEF BE43H 
      DEF BE43I 
B43KP DEF BE43K 
      DEF BE43L 
B43MP DEF BE43M 
      DEF BE43N 
B43PP DEF BE43P 
      DEF BE43Q 
* 
BE43  ASC 3,E043 _
BE43A ASC 3,STC _ 
BE43B ASC 3,CLC _ 
BE43C ASC 3,CLF _ 
BE43D ASC 3,SFC _ 
BE43E ASC 6,XX INSTR. _ 
BE43F ASC 8,DID NOT CONNECT/
BE43G ASC 5,CONNECTED/
BE43H ASC 8,DID NOT RELEASE/
BE43I ASC 5,RELEASED/ 
BE43J ASC 8,     EXTENDER _ 
BE43K ASC 2,TO _
BE43L ASC 2,F. _
BE43M ASC 5,THIS CPU /
BE43N ASC 5,OTHER CPU/
BE43O ASC 9,     WITH SWITCH _
BE43P ASC 3,NOT _ 
BE43Q ASC 6,IN NEUTRAL/ 
* 
      SKP 
* 
*        THIS SUBROUTINE TESTS THAT THE UNDEFINED I/O INSTRUCTIONS
*        WITH THE BUS SWITCH SC OF THE EXTENDER DO NOT MODIFY 
*        THE SWITCH SETTINGS IN THE EXTENDER. 
* 
NQI   NOP 
CPU27 STC BSC1       THROW SWITCH TO THIS CPU & CHECK 
      LDA CW01         THAT EXTENDER IS CONNECTED 
      JSB FLDTC 
      LDA LDA01      STORE A LDA .+1 INSTR INTO THE 
      STA T8LDA        VERIFY SUBROUTINE
      JSB NQITS      EXECUTE UNDEFINED I/O INSTRS.
* 
CPU28 CLC BSC1       THROW SWITCH TO OTHER CPU & CHECK
      LDA CW05         THAT EXTENDER IS REMOVED 
      JSB FLDTC 
      LDA LDA10      STORE A LDA SW150 INSTR INTO THE 
      STA T8LDA        VERIFY SUBROUTINE
      JSB NQITS      EXECUTE UNDEFINED I/O INSTRS.
* 
CPU29 STC BSC1       THROW SWITCH TO NEUTRAL POS &
CPU30 CLF BSC1         CHECK THAT EXTENDER IS REMOVED 
      LDA CW03
      JSB FLDTC 
      JSB NQITS      EXECUTE UNDEFINED I/O INSTRS.
      JMP NQI,I      RETURN 
* 
* 
*        EXERCICE THE UNDEFINED I/O INSTR. STF, SFS, MIA/B, 
*        LIA/B ANS OTA/B ON THE BUS SWITCH SC 
* 
NQITS NOP 
      LDA .-8        SET LOOP COUNTER TO -8 FOR THE 8 
      STA T8CNT        INSTR. TO BE TESTED. EXERCISE
CPU31 STF BSC1           EACH INSTR. & GO TO CHECK THAT 
      JSB NQISB            THE INSTR. DID NOT CHANCE
CPU32 SFS BSC1               THE SWITCH 
      JSB NQISB 
CPU33 MIA BSC1
      JSB NQISB 
CPU34 MIB BSC1
      JSB NQISB 
CPU35 LIA BSC1
      JSB NQISB 
CPU36 LIB BSC1
      JSB NQISB 
CPU37 OTA BSC1
      JSB NQISB 
CPU38 OTB BSC1
      JSB NQISB 
* 
      SKP 
* 
*        TEST THAT UNDEFINED I/O INSTRS. DO NOT MODIFY SWITCH 
* 
NQISB NOP 
T8LDA NOP         LDA .+1 OR LDA SW150 IS STORED AS 
      JSB DAFSR      CONTROL WORD FOR SUBROUT DAFSR 
      JMP *+4     ERROR, SUBROUT DID NOT TIME OUT 
      ISZ T8CNT   CORRECT RETURN, INCREMENT COUNTER 
      JMP NQISB,I   & RETURN
      JMP NQITS,I 
* 
      LDA T8CNT   UNDEF. I/O INSTR MODIFIED SWITCH
      ADA .+8     (LOOP CNT + 8).2 + START ADDR OF
      ALS           ASCII STRING = START ADDR OF
      ADA ER51        ASCII STRING SPECIFING
      LDB A,I           INTERFERING INSTR.
      STB BE51+3  GET 1.& 2. PAIR OF ASCII CHAR & 
      INA           STORE IN ERR MESSAGE
      LDB A,I 
      STB BE51+4
* 
      LDA BSSCX   GET BUS SWITCH SC & STORE IN MESSAGE
      JSB N2AO
      STA BE51+5
* 
      LDA T8LDA   DETERMEN FROM OPERAND OF SPECIFIED
      STA *+1       LDA BY EXAMINING BIT 15 WHICH 
      NOP             ERR MESSAGE HAS TO BE APPENDED
      LDB B51AP 
      SSA 
      LDB B51BP 
      STB *+3 
      JSB ERMS,I
      DEF BE51,I
      NOP 
      JMP T08,I 
* 
* 
LDA01 LDA .+1 
LDA10 LDA SW150 
* 
ER51  DEF *+1 
      ASC 16,STF SFS MIA MIB LIA LIB OTA OTB
* 
B51AP DEF BE51A 
B51BP DEF BE51B 
BE51  ASC 07,E051  XXXXYY _ 
BE51A ASC 16,REMOVED EXTENDER FROM THIS CPU/
BE51B ASC 15,SWITCHED EXTENDER TO THIS CPU/ 
* 
* 
* 
*************************************************************** 
      SKP 
      HED TEST 09 
* 
* 
*        TEST 09
*        -------
*        THIS TEST PERFORMS A CURSORY CHECK ON DMA ON 12979B
*        EXTENDERS. THIS TEST IS AUTOMATICALLY EXECUTED IF
*        TEST 08 WAS SELECTED VIA S-REG BIT 15, BIT 13 IS SET 
*        TO INDICATE THAT THE 12898-60001 BOARD IS INSTALLED
*        AND THE CPU HAS DMA. THE TEST REQUIRES ONE OF THE TWO
*        HARDWARE SETUPS SPECIFIED IN TEST 08 (ONE 12979B EX- 
*        TENDER UNDER PROGRAM CONTROL OF TWO CPU'S OR TWO EX- 
*        TENDERS UNDER PROGRAM CONTROL OF ONE CPU). 
* 
* 
      ORG 10000B
TST09 EQU * 
      NOP 
      JSB T09 
      CLC INTP,C
      JMP TST09,I 
* 
T09   NOP 
      CLC INTP,C
      JSB CPTPY,I     CHECK IF 21MX/XE
      LDA USSC        DID OPERATOR SPECIFY THAT DMA IS
      RAL,RAL           INSTALLED IN EXTENDER?
      SSA,RSS 
      JMP T09,I       NO, EXIT
      LDA CPTO        IS DMA INSTALLED IN CPU?
      ARS,ARS 
      SLA 
      JMP *+4         YES, OK 
      JMP ERMS,I      NO, ERROR E053
      DEF ER53
      JMP T09,I       EXIT TEST 
* 
      LDA BSSC1       CONFIGURE BUS SWITCH SC1
      LDB BSCP1 
      JSB ISC 
      LDA BSSC1       TRANSFER CURRENT BUS SW SC
      STA BSSCX         INTO BUFFER 
      LDA USSC        IS TEST REQUESTED ON REDUNDANT CPU'S? 
      RAL 
      SSA 
      JMP T9EXT       NO, REDUNDANT EXTENDERS 
* 
      SKP 
* 
* 
*   *** TEST ONE EXTENDER CONNECTED TO TWO CPU'S ***
* 
      LDA .-4         SET LOOP COUNT TO -4
      STA T9CNT 
CPU50 STC BSC1        TAKE SWITCH & WAIT UP TO 5 SEC
      LDA T5S 
      JSB DAFRS,I 
      JMP DMANT       OTHER CPU TOOK SWITCH 
* 
* 
*       TRANSFER TIMED OUT ON THIS CPU. (CPU#2) 
* 
      JSB T9TST       TEST DMA TRANSFER FROM/TO THIS CPU
CPU51 CLC BSC1        THROW SWITCH TO OTHER CPU 
      LDA .+1         WAIT 1 MSEC TO ASSURE OTHER CPU EXITED
      JSB TMRR,I        SUBROUTINE DAFSR
      LDA S1587       WAIT UP TO .38 SEC TO LET OTHER 
      JSB DAFRS,I       CPU TEST DMA
      JMP *+4         OK, OTHER CPU REPLIED 
      JSB ERMS,I      TIME OUT ERROR
      DEF EM50
      JMP T09,I 
      ISZ T9CNT       INCREMENT LOOP COUNT
      JMP CPU50 
      JMP T09,I 
* 
* 
*       TRANSFER DID NOT TIME OUT ON THIS CPU. (CPU#1)
* 
DMANT LDA T6S15       WAIT UP TO 6 SEC TO LET OTHER 
      JSB DAFRS,I       CPU TEST DMA
      JMP *+4         OK, OTHER CPU FINISHED
      JSB ERMS,I      TIME OUT ERROR
      DEF EM50
      JMP T09,I 
      JSB T9TST       TEST DMA TRANSFER FROM/TO CPU 
CPU52 CLC BSC1        THROW SWITCH TO OTHER CPU FOR 
      LDA .+3           RESINC, THEN WAIT 3 MSEC TO 
      JSB TMRR,I          LET OTHER CPU BECOME CPU#1
      ISZ T9CNT       INCREMENT LOOP COUNT
      JMP CPU50 
      JMP T09,I 
* 
T9CNT OCT 0 
* 
      SKP 
* 
* 
*   *** TEST TWO REDUNDANT EXTENDERS CONNECTED TO ONE CPU *** 
* 
T9EXT LDA .-4          SET LOOP COUNTER TO -4 
      STA T9CNT 
      JSB DISCO        CHECK IF BOTH EXT'S CAN BE DISCONN 
* 
EXT08 STC BSC1         TAKE SWITCH
      JSB T9TST        TEST DMA 
      ISZ T9CNT        TEST 4 TIMES?
      JMP EXT08        YES, EXIT
* 
      LDA EXT08        SEPARATE SC & CHECK IF TEST HAS
      AND .77            BEEN RUN ON BSC2 
      CPA BSSC2 
      JMP T09,I        YES, EXIT TEST 
      LDA BSSC2        NO, RECONFIGURE THIS PART OF 
      LDB BSCP2          TEST WITH BUS SWITCH SC 2, 
      JSB ISC              CHANGE BUS SW SC BUFFER
      LDA BSSC2              & REPEAT PROCESS ON
      STA BSSCX                2. EXTENDER
      JMP T9EXT 
* 
      SKP 
* 
*       SUBROUTINE TO PERFORM DMA TRANSFER & VERIFY DATA
* 
T9TST NOP 
      LDA .+2         CHECK DMA OUTPUT ON CHANNEL 1 
      JSB T9DCF 
      CLA 
      JSB T9DIR 
      JSB T9DMA 
      JSB T9IN
* 
      LDA .+3         CHECK DMA OUTPUT ON CHANNEL 2 
      JSB T9DCF 
      CLA 
      JSB T9DIR 
      JSB T9DMA 
      JSB T9IN
* 
      JSB T9OUT       CHECK DMA INPUT ON CHANNEL 1
      LDA .+2 
      JSB T9DCF 
      LDA .+1 
      JSB T9DIR 
      JSB T9DMA 
      JSB T9VRF 
* 
      JSB T9OUT       CHECK DMA INPUT ON CHANNEL 2
      LDA .+3 
      JSB T9DCF 
      LDA .+1 
      JSB T9DIR 
      JSB T9DMA 
      JSB T9VRF 
      JMP T9TST,I 
* 
ER53  ASC 11,E053 CPU WITHOUT DMA/
* 
      SKP 
* 
*        SUBROUTINE TO CONFIGURE DMA SC 2 & 6 OR 3 & 7
* 
T9DCF NOP             CONFIGURE THE 6 I-O INSTR. IN 
      LDB DMAPT         DMA SUBROUTINE TO SC 2 OR 3 
      JSB ISC 
      LDA DMA1        RECONFIGURE 1.& 6. DMA COMMAND
      ADA .+4           TO SC 6 OR 7
      STA DMA1
      LDA DMA6
      ADA .+4 
      STA DMA6
      JMP T9DCF,I 
* 
* 
* 
*        SUBROUTINE TO CREATE DMA ADDRESS WORD, PREPARE 
*        2-WORD DATA BUFFER & SET UP LOC "DMAXZ"
* 
T9DIR NOP 
      RAR             ROTATE DIRECTION BIT TO BIT POS 15
      AND SW15          CONCATENATE BUFFER ADDRESS & STORE
      IOR AW
      STA AWLC
      SSA             WAS DMA OUTPUT REQUESTED? 
      JMP *+8         NO, INPUT 
      LDA .1252       YES, LOAD OUTPUT BUFFER 
      STA AW+1
      LDA .0525 
      STA AW+2
      LDA T9.02       INSERT STC CH,C INSTR FOR DMA OUTPUT
      STA DMAXY 
      JMP T9DIR,I 
      CLA             CLEAR INPUT BUFFER
      STA AW+1
      STA AW+2
      CLA             REMOVE STC CH,C INSTR FOR DMA INPUT 
      STA DMAXY 
      JMP T9DIR,I 
* 
      SKP 
* 
*        SUBROUTINE TO TRANSFER DATA VIA DMA
* 
T9DMA NOP 
      LDA T9.01       LOAD CONTROL WORD WITH INTERF. BOARD
DMA1  OTA DMASC         SC & OUTPUT 
DMA2  CLC DMASC       OUTPUT MEM ADDRESS WORD 
      LDA AWLC
DMA3  OTA DMASC 
DMA4  STC DMASC       OUTPUT BLOCK LENGTH 
      LDA .-2 
DMA5  OTA DMASC 
DMAXY NOP             TURN I/O BOARD ON IF DMA OUTPUT 
DMA6  STC DMASC,C     TURN DMA ON 
      JMP T9DMA,I 
* 
T9.02 STC CH,C
T9.01 OCT 120000      CONTROL WORD WITH INTRF. BOARD SC 
AWLC  OCT 0           ADDR WORD WITH BUFF ADDR & DIRECTION
AW    DEF *+1 
      BSS 2 
* 
* 
* 
*        SUBROUTINE TO READ DATA FROM INTERF BOARD & COMPARE IT 
* 
T9IN  NOP 
      CLB             SET DMA ERR FLAG TO 0 
      NOP             ALLOW 12554 BOARD TO FINISH DMA 
      NOP               TRANF. BEFORE CHECKING
T9.03 LIA CH          READ 2 WORDS TRANSFERED TO INTF.
      CPA .1252         BOARD BY DMA BACK IN & COMPARE
      RSS 
      JSB T9DER       1. WORD TRANSFERED FAILED 
      INB             SET DMA ERROR FLAG TO 1 
T9.04 STC CH,C
      LDA .-4         ALLOW TIME FOR 12554 BOARD TO REPLY 
      ISZ A 
      JMP *-1 
T9.05 LIA CH
      CPA .0525 
      JMP T9IN,I
      JSB T9DER       2. WORD TRANSFERED FAILED 
* 
      SKP 
* 
*        SUBROUTINE TO PREPARE OUTPUT BUFFER FOR DMA TRANSFER 
* 
T9OUT NOP 
      LDA .1252       OUTPUT 2 WORDS TO INTF. BOARD 
T9.06 OTA CH
T9.07 STC CH,C
      LDA .-4         ALLOW TIME FOR 12554 BOARD TO REPLY 
      ISZ A 
      JMP *-1 
      LDA .0525 
T9.08 OTA CH
      JMP T9OUT,I 
* 
* 
* 
*        SUBROUTINE TO CHECK INPUT BUFFER FOR CORRECT DATA
* 
T9VRF NOP 
      LDB .+2         SET DMA ERROR FLAG TO 2 
      LDA AW+1        COMPARE THE 2 INPUTTED WORDS VIA
      CPA .1252         DMA INTO THE MEMORY BUFFER WITH 
      RSS                 THE EXPECTED VALUE
      JSB T9DER       ERROR 
      INB             SET DMA ERROR FLAG TO 3 
      LDA AW+2
      CPA .0525 
      JMP T9VRF,I     2. WORD OK, RETURN
      JSB T9DER 
* 
* 
* 
*        ERROR SUBROUTINE FOR DMA TRANSFER
* 
T9DER NOP 
      STA T9ARG       STORE DATA RECEIVED FROM DMA
      STB T9BRG         TRANSFER & ERROR FLAG 
      LDA BSSCX       STORE BUS SW SC INTO ERR MSG. 
      JSB N2AO
      STA ER54+17 
      STA ER55+17 
      LDA ER54P       ASSUME THAT DMA OUTPUT ERR
      LDB T9BRG       GET ERROR FLAG AGAIN
      RBR,SLB         WAS THIS A DMA OUTPUT?
      LDA ER55P       NO, INPUT ERR 
      IOR SW15        YES, ADD CONCATENATION BIT
      STA E5X1          & STORE IN MESSAGE
* 
      LDA ER5P1       ASSUME THAT 1.WORD FAILED 
      RBL,SLB         IS THAT TRUE? 
      LDA ER5P2       NO, 2. WORD FAILED
      IOR SW15        YES, ADD CONCATENATION BIT
      STA E5X2          & STORE IN MESSAGE
* 
      SKP 
* 
      LDA DMA1        DETERMEN FAILING DMA SC, CONVERT
      AND .77           TO ASCII & STORE IN MESSAGE 
      JSB N2AO
      STA ER5XC+13
* 
      LDA .1252       ASSUME THAT 1. WORD FAILED
      LDB T9BRG 
      SLB             IS THAT TRUE? 
      LDA .0525       NO, 2. WORD FAILED
      CLE             CONVERT EXPECTED WORD TO ASCII
      LDB ER5PE         & STUFF IN MESSAGE
      JSB O2AS,I
* 
      CLE             CONVERT ACTUAL WORD TO ASCII
      LDB ER5PA 
      LDA T9ARG 
      JSB O2AS,I
* 
      LDA .1252      LOAD A-REG WITH EXPECTED & B-REG 
      LDB T9BRG        WITH ACTUAL DATA WORD
      SLB            IS EXPECTED WORD = 125252? 
      LDA .0525      NO, IT'S 052525
      LDB T9ARG      ACTUAL WORD
      JSB ERMS,I
E5X1  NOP 
E5X2  NOP 
      DEF ER5XC,I 
      DEF ER5XE 
      JMP T09,I      EXIT TEST
* 
T9ARG OCT 0 
T9BRG OCT 0 
* 
ER54P DEF ER54
ER55P DEF ER55
ER5P1 DEF ER5X1 
ER5P2 DEF ER5X2 
* 
ER5PE DEF ER5XE+7 
ER5PA DEF ER5XA+7 
ER54  ASC 19,E054 DMA OUTPUT ERR, ON BUS SW SC VV/
ER55  ASC 19,E055 DMA INPUT ERR,  ON BUS SW SC VV/
ER5X1 ASC 04,     1._ 
ER5X2 ASC 04,     2._ 
ER5XC ASC 15, WORD TRANSF FAILED ON SC ZZ/
ER5XE ASC 10,     EXPECTED XXXXXX 
      OCT 6412
ER5XA ASC 11,     ACTUAL   YYYYYY/
* 
* 
* 
*************************************************************** 
      HED MESSAGES
FWAA  EQU *         FIRST WORD OF AVAL. MEMORY
      END