CPA T2A,I RSS HLT 0 STA,I/CPA,I FAILED * LDB EVEN1 EVEN1 = 052525 STB T2A,I CPB T2A,I RSS HLT 0 STB,I/CPB,I FAILED * CCA STA T2A,I T2A = DEF T2 ISZ T2A,I HLT 0 ISZ,I FAILED - DID NOT SKIP LDA T2A,I SZA HLT 0 ISZ,I FAILED - T2 NOT 0 * CLA IOR .P1,I .P1 = DEF TBL.1, TBL.1 = 015366 CPA K10 K10 = 015366 RSS HLT 0 IOR,I FAILED * CCA XOR .P1,I .P1 = DEF TBL.1, TBL.1 = 015366 CPA K12 K12 = 162411 RSS HLT 0 XOR,I FAILED * CCA AND .P1,I .P1 = DEF TBL.1, TBL.1 = 015366 CPA K10 K10 = 015366 RSS HLT 0 AND,I FAILED * CLA ADA .P2,I .P2 = DEF TBL.2, TBL.2 = 051463 CPA K11 K11 = 051463 RSS HLT 0 ADA,I FAILED * CLB ADB .P1,I .P1 = DEF TBL.1, TBL.1 = 015366 CPB K10 K10 = 015366 RSS HLT 0 ADB,I FAILED * JMP JMP1A,I JMP TO JMP1(INDIRECT), THEN JMP2 HLT 0 JMP,I FAILED * JMP2 CLA STA SR1A,I SR1A = DEF SR1 < SR1 _ NOP> JSB SR1A,I .P3 HLT 0 JSB,I FAILED .P4 LDA SR1A,I CPA .ADR3 .ADR3 = DEF .P3 RSS HLT 0 JSB,I FAILED - BAD RETURN ADDRESS * NOP ***** MODULE LOOP SPC 3 JMP PG1 GOTO END OF PAGE 0 HLT 0 JMP FAILED SPC 3 M1 DEC -1 M2 DEC -2 .0 DEC 0 .1 DEC 1 EVEN1 OCT 52525 ALL EVEN BITS 1'S ODD1 OCT 125252 ALL ODD BITS 1'S K1 OCT 52524 PMAX OCT 77777 BIT12 OCT 10000 BIT15 OCT 100000 HLT0 HLT 0 H7077 OCT 107077 T1 NOP TEMPORARY STORAGE ADDR1 DEF X1 ADDR3 DEF P3 ADDR4 DEF P4 JR1 JMP RTN1 JR2 JMP RTN2 JR3 JMP RTN3 JR4 JMP RTN4 A EQU 0 A REGISTER B EQU 1 B REGISTER * ADDR2 DEF RA3-1 ADDRY DEF RA4-1 ADDR7 DEF Z1 IA1 DEF IR1 IA2 DEF *+1,I DEF IR2 IA3 DEF RA3 IA4 DEF *+1,I DEF RA4 IA5 DEF M1 IA6 DEF IA5,I IA7 DEF EVEN1 IA8 DEF IA7,I IA9 DEF T1 IA10 DEF IA9,I K7 DEC 14397 * IR11 DEF RA11 IR12 DEF RA12 IR13 DEF X13 IR14 DEF X14 ADR13 DEF P13 ADR14 DEF P14 * .P1 DEF TBL.1 .P2 DEF TBL.2 K10 OCT 015366 K11 OCT 051463 K12 OCT 162411 T2A DEF T2 JMP1A DEF JMP1 SR1A DEF SR1 .ADR3 DEF .P3 P99A DEF P99 FCA DEF 2 FIRST CORE ADDRESS LCA DEF 3677B LAST CORE ADDRESS (2K) * JSB7 NOP SUBROUTINE FROM PAGE 1 JMP *+2,I RETURN TO PAGE 1 HLT 0 JMP,I FAILED DEF P9 JMP5 JMP *+2,I GO BACK TO PAGE 1 HLT 0 JMP DEF P6 SPC 3 ORG 1777B PG1 NOP HED INDIRECT ADDRESSING TO BASE PAGE LDA K11A,I K11 = DEF K11, K11 = 051463 CPA TBL.2 TBL.2 = 051463 RSS HLT 0 LDA,I FAILED * LDB K10A,I K10A, = DEF K10, K10 = 015366 CPB TBL.1 TBL.1 = 015366 RSS HLT 0 LDB,I FAILED * LDA TBL.1 TBL.1 = 015366 CPA K10A,I K10A = DEF K10, K10 = 015366 RSS HLT 0 CPA,I FAILED * LDB TBL.2 TBL.2 = 051463 CPB K11A,I K11A = DEF K11, K11 = 051463 RSS HLT 0 CPB,I FAILED * LDA EVEN1 STA T1A,I T1A = DEF T1 CPA T1 RSS HLT 0 STA,I/CPA FAILED * LDB ODD1 STB T1A,I T1A = DEF T1 CPB T1 RSS HLT 0 STB,I/CPB FAILED * CCA STA T1 ISZ T1A,I T1A = DEF T1 HLT 0 ISZ,I FAILED - DID NOT SKIP LDA T1 SZA HLT 0 ISZ,I FAILED - T1 NOT 0 * CLA IOR K11A,I K11A = DEF K11, K11 = 051463 CPA TBL.2 TBL.2 = 051463 RSS HLT 0 IOR,I FAILED * CCA XOR K12A,I K12A = DEF K12, K12 = 162411 CPA TBL.1 RSS HLT 0 XOR,I FAILED * CCA AND K10A,I K10A = DEF K10, K10 = 015366 CPA TBL.1 TBL.1 = 015366 RSS HLT 0 AND,I FAILED * JMP JMP5A,I JMP5A = DEF JMP5 HLT 0 JMP,I FAILED * P6 CLA STA JSB7 JSB7 _ NOP JSB JSB7A,I JSB7A = DEF JSB7 P7 HLT 0 JSB,I FAILED P9 LDA JSB7 CPA P7A P7A = DEF P7 RSS HLT 0 JSB,I FAILED - BAD RETURN ADDRESS * NOP ***** MODULE LOOP HED REGISTER INTERACTION TESTS * THIS SECTION CHECKS THAT ALL OTHER REGISTERS REMAIN UNCHANGED * WHEN A MEMORY REFERENCE INSTRUCTION IS EXECUTED. * CLB CLE CLO LDA M1 M1 = 177777 SZB HLT 0 LDA - B CHANGED SEZ HLT 0 LDA - E CHANGED SOC HLT 0 LDA - OV CHANGED CPA M1 RSS HLT 0 CPA FAILED SZB HLT 0 CPA - B CHANGED SEZ HLT 0 CPA - E CHANGED SOC HLT 0 CPA - OV CHANGED * CLA CLE CLO LDB EVEN1 EVEN1 = 052525 SZA HLT 0 LDB - A CHANGED SEZ HLT 0 LDB - E CHANGED SOC HLT 0 LDB - OV CHANGED CPB EVEN1 RSS HLT 0 CPB FAILED SZA HLT 0 CPB - A CHANGED SEZ HLT 0 CPB - E CHANGED SOC HLT 0 CPB - OV CHANGED * LDA ODD1 ODD1 = 125252 CCB CCE STO STA T1 SEZ,RSS HLT 0 STA - E CHANGED SOS HLT 0 STA - OV CHANGED CPB M1 RSS HLT 0 STA - B CHANGED CPA T1 RSS HLT 0 STA FAILED * LDB EVEN1 EVEN1 = 052525 CLA CLE CLO STB T1 SZA HLT 0 STB - CHANGED SEZ HLT 0 STB - E CHANGED SOC HLT 0 STB - OV CHANGED CPB T1 RSS HLT 0 STB FAILED * CLO CLE CLA CLB JMP *+2 HLT 0 JMP FAILED SZA HLT 0 JMP - A CHANGED SZB HLT 0 JMP - B CHANGED SEZ HLT 0 JMP - E CHANGED SOC HLT 0 JMP - OV CHANGED * CLA STA X99 X99 _ NOP CCA CCB STO CCE JSB *+2 P99 HLT 0 JSB FAILED X99 NOP SEZ,RSS HLT 0 JSB - E CHANGED SOS HLT 0 JSB - OV CHANGED CPA M1 RSS HLT 0 JSB - A CHANGED CPB M1 RSS HLT 0 JSB - B CHANGED LDA X99 CPA P99A P99A = DEF P99 RSS HLT 0 JSB - BAD RETURN ADDRESS * CLA CLB ADA M1 < E, OV, A CHECKED ELSEWHERE> SZB HLT 0 ADA - B CHANGED * CLA CLB ADB ODD1 < E, OV, B CHECKED ELSEWHERE> SZA HLT 0 ADB - A CHANGED * CLA CLB CLO CLE IOR EVEN1 EVEN1 = 052525 XOR ODD1 ODD1 = 125252 AND M1 M1 = 177777 SZB HLT 0 IOR OR XOR OR AND - B CHANGED SOC HLT 0 IOR OR XOR OR AND - OV CHANGED SEZ HLT 0 IOR OR XOR OR AND - E CHANGED CPA M1 RSS HLT 0 IOR/XOR/AND - RESULT NOT 177777 * CCA STA T1 T1 _ 177777 CLA CLB CLE CLO ISZ T1 HLT 0 ISZ FAILED - DID NOT SKIP SZA HLT 0 ISZ - A CHANGED SZB HLT 0 ISZ - B CHANGED SEZ HLT 0 ISZ - E CHANGED SOC HLT 0 ISZ - OV CHANGED * NOP ***** MODULE LOOP HED INDIRECT ADDRESSING VIA A & B REGISTERS LDA IA5 IA5 = DEF M1, M1 = 177777 LDA A,I CPA M1 RSS HLT 0 LDA A,I FAILED * LDB IA7 IA7 = DEF EVEN1, EVEN1 = 052525 LDA B,I CPA EVEN1 RSS HLT 0 LDA B,I FAILED * LDB IA5 IA5 = DEF M1, M1 = 177777 LDB B,I CPB M1 RSS HLT 0 LDB B,I FAILED * LDA IA7 IA7 = DEF EVEN1, EVEN1 = 052525 LDB A,I CPB EVEN1 RSS HLT 0 LDB A,I FAILED * CLB STB T1 T1 _ 0 LDA IA9 IA9 = DEF T1 STA A,I LDB T1 CPB T1 RSS HLT 0 STA A,I FAILED * CLA STA T1 T1 _ 0 LDB IA9 IA9 = DEF T1 STB B,I LDA T1 CPA T1 RSS HLT 0 STB B,I FAILED * CLA STA T1 T1 _ 0 CCA A _ 177777 LDB IA9 IA9 = DEF T1 STA B,I LDB T1 CPB M1 RSS HLT 0 STA B,I FAILED * CLB STB T1 T1 _ 0 CCB B _ 177777 LDA IA9 IA9 = DEF T1 STB A,I LDA T1 CPA M1 RSS HLT 0 STB A,I FAILED * LDA IA9 IA9 = DEF T1 STA T1 CPA A,I RSS HLT 0 CPA A,I FAILED LDB IA9 IA9 = DEF T1 STB T1 CPB B,I RSS HLT 0 CPB B,I FAILED * LDA IA9 IA9 = DEF T1 STA T1 LDB IA9 CPA B,I RSS HLT 0 CPA B,I FAILED CPB A,I RSS HLT 0 CPB A,I FAILED * LDA IA7 IA7 = DEF EVEN1 ADA EVEN1 EVEN1 = 052525 STA T1 LDA IA7 ADA A,I CPA T1 RSS HLT 0 ADA A,I FAILED * LDB IA5 IA5 = DEF M1 ADB M1 M1 = 177777 STB T1 LDB IA5 ADB B,I CPB T1 RSS HLT 0 ADB B,I FAILED * CLA LDB IA5 IA5 = DEF M1, M1 = 177777 ADA B,I CPA M1 RSS HLT 0 ADA B,I FAILED * CLB LDA IA7 IA7 = DEF EVEN1, EVEN1 = 052525 ADB A,I CPB EVEN1 RSS HLT 0 ADB A,I FAILED * LDA IA5 IA5 = DEF M1, M1 = 177777 IOR A,I CPA M1 RSS HLT 0 IOR A,I FAILED * CLA LDB IA7 IA7 = DEF EVEN1, EVEN1 = 052525 IOR B,I CPA EVEN1 RSS HLT 0 IOR B,I FAILED * LDA IA5 IA5 = DEF M1, M1 = 177777 AND A,I CPA IA5 RSS HLT 0 AND A,I FAILED * LDA EVEN1 EVEN1 = 052525 LDB IA5 IA5 = DEF M1, M1 = 177777 AND B,I CPA EVEN1 RSS HLT 0 AND B,I FAILED * * CHECK CMB INSTRUCTION BEFORE TESTING XOR A,I * LDB EVEN1 B _ 052525 CMB CPB ODD1 RSS HLT 0 CMB FAILED CMB CPB EVEN1 RSS HLT 0 CMB FAILED * LDB IA5 IA5 = DEF M1, M1 = 177777 CMB LDA IA5 XOR A,I CPA B RSS HLT 0 XOR A,I FAILED * LDA EVEN1 EVEN1 = 052525 LDB IA5 IA5 = DEF M1, M1 = 177777 XOR B,I CPA ODD1 RSS HLT 0 XOR B,I FAILED * LDA IR11 IR11 = DEF RA11 JMP A,I HLT 0 JMP A,I FAILED * RA11 LDB IR12 IR12 = DEF RA12 JMP B,I HLT 0 JMP B,I FAILED * RA12 CLA STA X13 X13 _ NOP