ASMB,A,B,L,C HED 2100 SERIES COMPUTER MEMORY REFERENCE TEST ORG 126B OCT 101100 DIAGNOSTIC SERIAL NUMBER * ******************************************************************* * * MEMORY REFERENCE INSTRUCTION GROUP DIAGNOSTIC * * RUNS IN 4K MEMORY * * TELETYPE NOT REQUIRED * * DIAGNOSTIC CONFIGURATOR NOT REQUIRED * * DIAGNOSTIC SERIAL NO (DSN) 101100 * * 1. LOAD MRG DIAGNOSTIC. * * 2. SET P REGISTER TO 100. * * 3. SELECT PROGRAM OPTIONS IN THE SWITCH REGISTER: * *************** SWITCH REGISTER OPTIONS *************************** * * BIT MEANING * * 0-11 RESERVED * 12 CLEAR TO HALT 102077 AT END OF PASS. * SET TO LOOP ON DIAGNOSTIC * 13-15 RESERVED * * 4. PRESET(INT. & EXT. IF PRESENT) AND RUN. * *************** COMPUTER HALTS ************************************* * * HALT MEANING * * 102000 ERROR HALT * 102077 END OF PASS * 106075 UNEXPECTED HALT(LOCATIONS 3472 THRU 6477) * 106077 UNEXPECTED HALT(LOCATIONS 2 THRU 77) * ******************************************************************* SKP * THE FOLLOWING SOURCE LINES ARE SUPPRESSED * UNL SUPPRESS SOURCE LISTING * ORG 2 * REP 62 106077 HALTS IN CORE * OCT 106077 LOC 2 THRU 77 * ORG 3472B * REP 3005B * OCT 106075 LOC 3472 THRU 6477 UNL ORG 2 REP 62 OCT 106077 ORG 3472B REP 3005B OCT 106075 LST RESUME SOURCE LISTING SPC 3 * THE FOLLOWING IS A SIMPLE LOOP WHICH CAN BE USED TO CHECK THE * SWITCH REGISTER,HLT INSTRUCTION & JMP INSTRUCTION PRIOR TO * EXECUTION OF THE MRG DIAGNOSTIC. * THIS PROGRAM MUST BE MANUALLY LOADED VIA THE FRONT PANEL. * * 00010 ORG 10B * 00010 102501 LPO LIA 1 * 00011 102000 HLT 0 * 00012 102601 OTA 1 * 00013 024010 JMP LPO SPC 3 ORG 100B JMP 130B HED BASIC TESTS ORG 130B * * CHECK SIMPLE ALTER-SKIP INSTRUCTIONS * START RSS HLT 0 RSS FAILED * CLA SZA HLT 0 CLA/SZA FAILED * CLA SZA,RSS RSS HLT 0 CLA/SZA,RSS FAILED * CLB SZB HLT 0 CLB/SZB FAILED * CLB SZB,RSS RSS HLT 0 CLB/SZB,RSS FAILED * * CHECK CPA INSTRUCTION * CLA CPA .0 RSS HLT 0 CLA/CPA .0 FAILED * CLA CPA M1 HLT 0 CLA/CPA M1 FAILED * CCA CPA M1 RSS HLT 0 CCA/CPA M1 FAILED * CLA,INA SZA,RSS HLT 0 CLA,INA/SZA,RSS FAILED * CLA,INA CPA .1 RSS HLT 0 CLA,INA/CPA .1 FAILED * * CHECK LDA & CPA INSTRUCTIONS * LDA .0 CPA .0 RSS HLT 0 LDA .0/CPA .0 FAILED * LDA M1 CPA M1 RSS HLT 0 LDA M1/CPA M1 FAILED * LDA EVEN1 CPA EVEN1 RSS HLT 0 LDA EVEN1/CPA EVEN1 FAILED * LDA ODD1 CPA ODD1 RSS HLT 0 LDA ODD1 /CPA ODD1 FAILED * CLA CPA M1 HLT 0 CLA/CPA M1 FAILED * LDA EVEN1 CPA ODD1 HLT 0 LDA EVEN1/CPA ODD1 FAILED * * * CHECK STA INSTRUCTION * CLA STA T1 CPA T1 RSS HLT 0 CLA/STA T1/CPA T1 FAILED * CCA STA T1 CPA T1 RSS HLT 0 CLA/STA T1/CPA T1 FAILED * LDA EVEN1 STA T1 CPA T1 RSS HLT 0 LDA EVEN1/STA T1/CPA T1 FAILED * LDA ODD1 STA T1 CPA T1 RSS HLT 0 LDA ODD1/STA T1/CPA T1 FAILED * * * CHECK AND INSTRUCTION * CCA AND M1 CPA M1 RSS HLT 0 CCA/AND M1/CPA M1 FAILED * CLA AND M1 SZA HLT 0 CLA/AND M1/SZA FAILED * CLA AND .0 SZA HLT 0 CLA/AND .0/SZA FAILED * CCA AND .0 SZA HLT 0 CCA/AND .0/SZA FAILED * * CHECK IOR INSTRUCTION * CLA IOR .0 SZA HLT 0 CLA/IOR .0/SZA FAILED * CLA IOR M1 CPA M1 RSS HLT 0 CLA/IOR M1/CPA M1 FAILED * CCA IOR M1 CPA M1 RSS HLT 0 CCA/IOR M1/CPA M1 FAILED * CCA IOR .0 CPA M1 RSS HLT 0 CCA/IOR .0/CPA M1 FAILED * * CHECK XOR INSTRUCTION * CLA XOR .0 SZA HLT 0 CLA/XOR .0/SZA FAILED * CCA XOR .0 CPA M1 RSS HLT 0 CCA/XOR .0/CPA M1 FAILED * CLA XOR M1 CPA M1 RSS HLT 0 CLA/XOR M1/CPA M1 FAILED * CCA XOR M1 SZA HLT 0 CCA/XOR M1/SZA FAILED * * CHECK CPB INSTRUCTION * CLB CPB .0 RSS HLT 0 CLB/CPB .0 FAILED * CLB CPB M1 HLT 0 CLB/CPB M1 FAILED * CCB CPB M1 RSS HLT 0 CCB/CPB M1 FAILED * CLB,INB SZB,RSS HLT 0 CLB,INB/SZB,RSS FAILED * CLB,INB CPB .1 RSS HLT 0 CLB,INB/CPB .1 FAILED * * CHECK LDB & CPB INSTRUCTIONS * LDB .0 CPB .0 RSS HLT 0 LDB .0/CPB .0 FAILED * LDB M1 CPB M1 RSS HLT 0 LDB M1/CPB M1 FAILED * LDB EVEN1 CPB EVEN1 RSS HLT 0 LDB EVEN1/CPB EVEN1 FAILED * LDB ODD1 CPB ODD1 RSS HLT 0 LDB ODD1/CPB ODD1 FAILED * CLB CPB M1 HLT 0 CLB/CPB M1 FAILED * LDB EVEN1 CPB ODD1 HLT 0 LDB EVEN1/CPB ODD1 FAILED * * CHECK STB INSTRUCTION * CLB STB T1 CPB T1 RSS HLT 0 CLB/STB T1/CPB T1 FAILED * CCB STB T1 CPB T1 RSS HLT 0 CCB/STB T1/CPB T1 FAILED * LDB EVEN1 STB T1 CPB T1 RSS HLT 0 LDB EVEN1/STB T1/CPB T1 FAILED * LDB ODD1 STB T1 CPB T1 RSS HLT 0 LDB ODD1/STB ODD1/CPB T1 FAILED * * CHECK ADA INSTRUCTION * CLA ADA M1 CPA M1 RSS HLT 0 CLA/ADA M1/CPA M1 FAILED * CCA ADA M1 CPA M2 RSS HLT 0 CCA/ADA M1/CPA M2 FAILED * LDA ODD1 A=125252 ADA ODD1 A=052524 CPA K1 RSS HLT 0 LDA ODD1/ADA ODD1/CPA K1 FAILED * LDA EVEN1 A = 052525 ADA EVEN1 A = 125252 CPA ODD1 RSS HLT 0 LDA EVEN1/ADA EVEN1/CPA ODD1 FAI * * CHECK ADB INSTRUCTION * CLB ADB M1 CPB M1 RSS HLT 0 CLB/ADB M1/CPB M1 FAILED * CCB ADB M1 CPB M2 RSS HLT 0 CCB/ADB M1/CPB M2 FAILED * LDB ODD1 B=125252 ADB ODD1 B=052524 CPB K1 RSS HLT 0 LDB ODD1/ ADB ODD1/CPB K1 FAILED * LDB EVEN1 B=125252 ADB EVEN1 B=052525 CPB ODD1 RSS HLT 0 LDB EVEN1/ADB EVEN1/CPB ODD1 FAI * * CHECK JMP INSTRUCTION * JMP *+2 HLT 0 JMP FAILED * * CHECK JSB INSTRUCTION * CLA STA X2 NOP LOCATION X2 JSB *+2 X1 HLT 0 JSB FAILED X2 NOP LDA X2 CPA ADDR1 ADDR1 = ADDRESS X1 RSS HLT 0 JSB FAILED - BAD RETURN ADDRESS * * CHECK ISZ INSTRUCTION * CLA STA T1 T1=0 ISZ T1 RSS HLT 0 ISZ FAILED - UNEXPECTED SKIP LDB T1 CPB .1 RSS HLT 0 ISZ FAILED - T1 NOT 1 * CCA STA T1 T1=177777 ISZ T1 HLT 0 ISZ FAILED - DID NOT SKIP LDA T1 SZA HLT 0 ISZ FAILED - T1 NOT 0 * CLA STA T1 T1=0 X4 INA SZA,RSS JMP X5 ISZ T1 RSS HLT 0 ISZ FAILED - UNEXPECTED SKIP CPA T1 JMP X4 HLT 0 ISZ FAILED - T1 NOT INCREMENTED JMP X4 * X5 NOP ***** MODULE LOOP HED MEMORY REFERENCES TO A & B REGISTERS LDA JR1 A _ JMP RTN1 LDB HLT0 B _ 102000 JMP A HLT 0 JMP A FAILED * RTN1 LDA HLT0 A _ 102000 LDB JR2 B _ JMP RTN2 JMP B HLT 0 JMP B FAILED * RTN2 CLA A _ NOP LDB JR3 B _ JMP RTN3 JSB A P3 HLT 0 JSB A FAILED RTN3 CPA ADDR3 ADDR3 = LOCATION P3 RSS HLT 0 BAD RETURN ADDRESS IN A * LDA HLT0 A _ 102000 LDB JR4 STB 2 2 _ JMP RTN4 CLB B _ NOP JSB B P4 HLT 0 JSB B FAILED RTN4 CPB ADDR4 ADDR4 = LOCATION P4 RSS HLT 0 BAD RETURN ADDRESS IN B * LDA H7077 H7077 = 107077 STA 2 RESTORE HALT TO LOCATION 2 * LDB EVEN1 LDA B CPA EVEN1 RSS HLT 0 LDA B FAILED * LDA ODD1 LDB A CPB ODD1 RSS HLT 0 LDB A FAILED * CCB CLA STA B SZB HLT 0 STA B FAILED * CCA CLB STB A SZA HLT 0 STB A FAILED * LDA EVEN1 LDB EVEN1 CPA B RSS HLT 0 CPA B FAILED CPB A RSS HLT 0 CPB A FAILED * LDB M1 CLA IOR B CPA M1 RSS HLT 0 IOR B FAILED * CCB CLA XOR B CPA M1 RSS HLT 0 XOR B FAILED * CCB LDA EVEN1 AND B CPA EVEN1 RSS HLT 0 AND B FAILED * LDB EVEN1 CLA ADA B CPA EVEN1 RSS HLT 0 ADA B FAILED * LDA ODD1 CLB ADB A CPB ODD1 RSS HLT 0 ADB A FAILED * CLA CLB X20 INB B_B+1: NEXT EXPECTED A CONTENTS SZB EXPECT ISZ TO CAUSE SKIP IF 0