IMD 1.16: 30/08/2008 21:24:25 rev. e dmu (53736 e0) diagnostic f94903 84-94903-01a1   ?nI7D@@8p8q0  nIPnI1f! %&&&$(('*9'C# LAC0HU U1G1JPS ?(K٠8p<0=q>>?Ơ2:GF4;9/!> ֠8:8=9O A9R"! &:ƭ >-A)>?8p?r8p?r8pΠ95o9A;mYWZd)]N- RI/%663ОDD(G6p9R<ʳ:!9RY]_!C3]^#uj!( o7//?)wdch c:T88888"$>H !  1 .H !0 !#(rr  F !Cr:',Q9 1  . H1  1 0  1 S &>:J;;;::;::;:m9[ee Pc`9A;l^H;z:IA=q;z=q;zIJ "IV!,:}:&<;}$:q: :}::q:1;}<:q:!^;ldef;X;k;j<;l<0:i! (H:i<%:i  3 :i   vOQQG:q:kCjA  !.76H?0]\1(9!71@E&01*7+ ;>(PCF{:q:4<<:q:vvvv 8A(D=qޭz=q)>?8p?r8p?r8pΠӠԶP" !=8B:};Z<;}j325L:J2 0\H^cHFg(R6QQNRP I8\>$?  -kl 1216yz{}(j8:};Z < :<0W3 5;Y;;;;;;;;;;Y;Y;Y;;;syt ! !1(^ (YZ -$SG(1@Au s9Y X !6WP"HКSQP 400'S<< >= A&&A%PG<0T+<<= =G8c!  !-T4=q_\!)XU1\2YJ=$Q 6 ^ (228S+=`D B !I}͠=l' 1 1 1Zk\p =q:o; <8=2X0R  =O=V=Z > ?nI7D@@8p8q0  nIPnI1f! %&&&$(('*9'C# LAC0HU U1G1JPS ?(K٠8p<0=q>>?ITUTVUOQ  J ID!+  !< D:GH875AlI,521 /!!'$&($$%" $  #nI" P0ɲ HVWY=\>>:gulD8I9X8!X"I2flclP0X]nR 8F13Sl X!"2 HlGl Bn P 8R9n$DZ 9h?2      Ġ@- )B٠.٠K8٠ƹ٠  ?7D@@@8p8q0  nIPnIWx6zz&$(('*9'C# LAC0H/%$$  !os>9 S Wu w BCD T U V XO @1Ap8p<0=q>>?>>  +++DIAGNOSTIC ABORT+++  **SENSE INT. ACK. FROM DMU FALSE **  **FAIL****FAIL****FAIL****FAIL****FAIL****FAIL** **FAIL****FAIL****FAIL****FAIL****FAIL****FAIL** pSYT!$P A. INTERRUPT TEST:  T!$ P!YSD% ..PASS.. 2pn S YT!$P] B1. DMU SET SENSE FLAGS TEST: K II!I0I?T!$n!24P5YSD9T1S!-PnT!\YS D4JIT1 S!:PnT!jT4GYS DZT1 S! 8PnT!ye4GYS j[T1S1[5Ps4CYS Dyn **SENSE FLAG 1 NOT SET**  **SENSE FLAG 2 NOT SET**  **SENSE FLAG 3 NOT SET**  **AFTER DMU RESET, CPU ENABLE SENSE FLAG NOT SET BY DMU** [n S YT!$^P]^ HH!H1T!$n!PZYSDZT1S1[NPnT![04GYS DZT1 S1[LPnT!kB4GYS DZT1S! KPZ4CYS D[ B2. DMU RESET SENSE FLAGS TEST: Y **SENSE FLAG 1 NOT RESET** l **SENSE FLAG 2 NOT RESET** | **SENSE FLAG 3 NOT RESET**  **CPU ENABLE SENSE FLAG NOT RESET AFTER DMU RESET** pn0SYT!$P]^ nT1S! PT!4EYS D"[ T1S!PpH HI*I9n1%4N T1S1[?PnT!UD4GYS DZT1 S!+tPnT!dU4GYS D[T1 S!zPnT!sf4GYS DlT1S! Ps4CYS Dy[ C. SOFTWARE RESET ON ISTR AND SENSE FLAGS TEST: 4 **ISTR NOT RESET** O ..ISTR RESET PASS.. [ **SENSE INPUT READY TRUE (NOT RESET)** h **SENSE OUTPUT READY FALSE (NOT RESET)** ~ **SENSE INT. ACK. FALSE (NOT RESET)** p@S YT!$P]^ I"XҔ T1 S!P]^Z4GT1S! P~_4EYS DZ[XrT1 S!HPPT!wZ4GYS DZ_T1 S!ZPPV_T!Z;4JYS DZ T1S104YS DZPZ T1S1`PZ4YSDZPZ T1 S!!PX" T1=Pp4K 4EYS DZT18P_4EYS DZ[H$H$HH D1. UNCONDITIONAL INPUT :1248 TEST: X ..DATA GOOD.. m **DATA BAD** w **SENSE INPUT READY FALSE** **OUTPUT READY BIT OF ISTR NOT SET AFTER CPU ACCESSED OUTR** ..ISTR OUTPU T READY BIT SET BY CPU AFTER ACCESSING OUTR.. **OUTPUT READY BIT OF ISTR NOT RESET AFTER DMU LOADED OUTR** p@S YT!$P]^ D2. UNCONDITIONAL INPUT :2481 TEST: pȞ@S YT!$P]^ D3. UNCONDITIONAL INPUT :4812 TEST: ,p@S YT!$P ]^ D4. UNCONDITIONAL INPUT :8124 TEST: SpPS YT!$P"]^ablc } T1S!dPIT1S!PZ4K 4EYSDZT1S! PZYS D4GZ\[T1 S!DdPPT!)4GYS  DZZT1 S!VdPPT!J;4GYS DZT1S!gePX_Z4EYS ZT1 S!uePX_qPZ4GYS DZT1 S! PePX_Z4GYS DZ[ E1. UNCONDITIONAL OUTPUT :1248 TEST: ..SENSE OUTPUT READY TRUE.. **SENSE OUTPUT READY FALSE**   **NEW INPUT BIT OF ISTR NOT RESET AFTER DMU ACCESSED MBOX** / **NEW INPUT BIT OF ISTR NOT SET AFTER CPU LOADED MBOX**  QpPS YT!$ P$]^iblc E2. UNCONDITIONAL OUTPUT :2481 TEST: pPS YT!$ P&]^j blc E3. UNCONDITIONAL OUTPUT :4812 TEST: pPS YT!$ P(]^kblc E4. UNCONDITIONAL OUTPUT :8124 TEST: p`S YT!$@P*]@ 8B1D{T1\4AYSDZXbIXlT1 S!ePlm Pb_Z4IYS   DZ[ F01. LOAD RAM WITH 00 TEST: * AT ;p`S YT!$P,]@P F02. LOAD RAM WITH :FF TEST: Pfgh F03. RAM 1000--10FF TEST: hfgh F04. RAM 1100--11FF TEST: fgh F05. RAM 1200--12FF TEST:  fgh F06. RAM 1300--13FF TEST: fgh F07. RAM 1400--14FF TEST: fgh F08. RAM 1500--15FF TEST: f gh F09. RAM 1600--16FF TEST: fgh F10. RAM 1700--17FF TEST: fgh F11. RAM 1800--18FF TEST: fgh F12. RAM 1900--19FF TEST: 7fgh F13. RAM 1A00--1AFF TEST: Nfgh F14. RAM 1B00--1BFF TEST: efgh F15. RAM 1C00--1CFF TEST: |fgh F16. RAM 1D00--1D FF TEST: fgh F17. RAM 1E00--1EFF TEST: fgh F18. RAM 1F00--1FFF TEST:  fgh  F19. RAM 2000--20FF TEST: !f gh F20. RAM 2100--21FF TEST: "f!gh F21. RAM 2200--22FF TEST: #f"gh F22. RAM 2300--23FF TEST: $f#gh F23. RAM 2400--24FF TEST: 4%f$gh F24. RAM 2500--25FF TEST: K&f%gh F25. RAM 2600--26FF TEST: b'f&gh F26. RAM 2700--27FF TEST: y(f'gh F27. RAM 2800--28FF TEST: )f(gh F28. RAM 2900--29FF TEST: *f)gh F29. RAM 2A00--2AFF TEST: +f0gh F30. RAM 2B00--2BFF TEST: ,f1gh F31. RAM 2C00--2CFF TEST: -f2gh F32. RAM 2D00--2DFF TEST: .f3gh F33. RAM 2E00--2EFF TEST: /f4gh F34. RAM 2F00--2FFF TEST: 1p`SPYT!$ P.]l 0f5gh F35. RAM 3000--30FF TEST: [1f6gh F36. RAM 3100--31FF TEST: r2f7gh F37. RAM 3200--32FF TEST: 3f8gh F38. RAM 3300--33FF TEST: 4f9gh F39. RAM 3400--34FF TEST: 5f@gh F40. RAM 3500--35FF TEST: 6fAgh F41. RAM 3600--36FF TEST: 7fBgh F42. RAM 3700--37FF TEST: 8fCgh F43. RAM 3800--38FF TEST: 9fDgh F44. RAM 3900--39FF TEST: *:fEgh F45. RAM 3A00--3AFF TEST: A;fFgh F46. RAM 3B00--3BFF TEST: XfIgh F49. RAM 3E00--3EFF TEST: ?fPgh F50. RAM 3F00--3FFF TEST: @fQgh F51. RAM 4000--40FF TEST: AfRgh F52. RAM 4100--41FF TEST: BfSgh F53. RAM 4200--42FF TEST: CfTgh F54. RAM 4300--43FF TEST: DfUgh F55. RAM 4400--44FF TEST: 'EfVgh F56. RAM 4500--45FF TEST: >FfWgh F57. RAM 4600--46FF TEST: UGfXgh F58. RAM 4700--47FF TEST: lHfYgh F59. RAM 4800--48FF TEST: If`gh F60. RAM 4900--49FF TEST: Jfagh F61. RAM 4A00--4AFF TEST: Kfbgh F62. RAM 4B00--4BFF TEST: Lfcgh F63. RAM 4C00--4CFF TEST: Mfdgh F64. RAM 4D00--4DFF TEST: Nfegh F65. RAM 4E00--4EFF TEST:  Offgh F66. RAM 4F00--4FFF TEST: $ppS YT!$wP0]jlcZ T1S!$PZ4CYS DZ T1S!PX_P!_Z"_Z4NYS DZ[ -T1S  {!GP4CYS DZ =T1S!WeP,4CYS DZ T1`PZ4CYSDZ G1. DMA READ :4812 FROM LOC. :1FFF TEST:  **DMA READ CYCLE STARTS BEFORE INR IS EMPTIED BY DMU**  **NO DMA COMPLETION INTERRUPT**  **DMA DONE BIT OF ISTR NOT SET**  FROM  **DMA FAIL ** ppS YT!$LP8]jбk$lc[ رT1S!G-P4CYS DZ     G2. DMA READ :4812 FROM LOC. :1FFF, :8124 FROM :2000 TEST: @pƀS YT!$P:]YlctZII T1S!&PZ4CYS DZ T1S!P_P_YZU_PY_Z4RYS DZ[ T1S!EP4CYS DZ T1S!SP,4QYS DZ KjYk T1`PZ4CYSDZT1S!vePO4CYS DZ H1. DMA WRITE :4812 TO LOC. :1FFF TEST:  **DMA WRITE CYCLE STARTS BEFORE OUTR IS LOADED BY DMU**  AT pƀS YT!$%P@]Y췷lc H2. DMA WRITE :4812 TO :1FFF, :8124 TO :2000 TEST: /pƐSYT!$=PB]^ pT1S!ZPZ4CYS DZ T1Sm! AWRarjBbF!LPSJI򪶩RI2A5oVVm SHM@DlClBl=l@5@e8ge-312 3+)(((<(((!w !egH!0($* 0 P XXm SHM@DlClBl=l@5@e8ge-312 3+)((( ?7D@@@ 8p8q0  nIPnI1f! %&&&$(('*9'C# LAC0HU U1G1JPS ?(K٠8p<0=q>>?} 7Ơ:;GhAd!D`^kOU SRhƠZH%t%t  cd1l9!1 ((1v#|%%1P !^`(Kn"h (Pf{D 0Xk7ڍ߾  ڈh #$&+)V1 ^Rmjjg!ca_ HIZKL>(0PMWMy)_1)Fddgio tvz~6 S 0  ޭ  %t%t3 (9 $k$ 1,!FԜZ1(&!E0 °°°°ӱӲӳӴ0K$i  "8K)i ݜ P Μ ɜK-i l㼜Kgi2㶴!㬼1S㨴P  D Zt@㜴P㘜㖜-4E>㌴ ㉌〔 D|ZGu DP H 5Z%t%tGd Ki^p\ X,wjTVqYSO G1 (08hB:C=И  FhC 0(!FZS    OVMfhNTGacbR;  RK i "$! K(i21-68 4?AA) }Khp`U(WHY iTd kw2j  js )"}(ƲĜ k?D2P1X%t%t0XF(1 ! ( D k?D2PВ 1X1ڈtXš X D ՜Xqq1Мjk?gg2Кdba(EKdi"EQk?N2(㊴М!C65 FpX(q1Z" Z   ך ( q8 : ;C. 1,pΚ""$pW(p΢CZ⥄Z1%t%t^8UJfXh↜hⅴO-bx^bY @FqK)i2YZkƀc&k7F[K)i"UZk?PJJ !0b״WSFk|2>k}2k|"9P2 0@("2kk56?kw2 `<=Z ZUV М^ _(TF (i;nkwZ"F!Ipt} Iw((G%t%t    ! ! 睜S *МP ղpk >fP"aaD @ô!UU8RiN3ԜDPG(@W`Z!'4[74X1H-.HSQhIUL (+4Q RP   #*0123456789:ABCDEFGHIJKLMNOPQRSTUVWXYZTXTSYBISI ~-geeUa_``0W! !' !%? G"$CP )DP Z{7G@Z/.1>)%t%t '*瑴 ȴP# M H0K`j2WS zkƀ fMJcGPNg0v0Ki K";&0++;/02117! ۢP1~P1IP1(Q P GXD}_ mXヴW}nrwvtqF lbFfZ 燴m12Z780WRмZ ;祴Z!R  W!Z) FH` 0Z  r%  %t%t ҴklԜk  B   ? FOWhiILUܴW 1,""'(1P16@;㵜< CZ :8I㢜\W㘴 E cd p {)p 8 m0K 2(  1G犜P?K/ia ! Y?S0 (p >F!; 88 D 3;XY5 1 ŴF') ܜ۴WZ%t%t  hXJMcGHfNPojheǀ0K`28E U%-( F22Z0K`"Q; (  $ LMZ0K(LT" !` (eV N SZ EM   h@8??%熴 /8 HW  (Ki. Kki25 !j - :OQVKI k/20 (k/2P(!kFX %t%t  31  1  1 10 Z  ' 皜'Yf]H! v .0 ~֎ H,0ka"k2شƴ2PPDŴ2ԲƄɴӚ 1 kƄ2ƂRךy0l0HP1D0l0PiC1*` ;]猴'!Z&!G|( }WS{{WxxA@2&!d0@8E2_6]/*OY%t%tC9"PCCJCIb&?~gk[aXUxp A&) #%t%t ^^qq ZB2TS( !@12 h$l(* / z v#zڤڢ롲w,'hDXDFОLM޶NܶOڶ@!ꇴHОJW PPPPN1 U≴E!₲AggQ=N>AWR%t%tarjBbF!LPSJI򪶩RI2A5oVVm SHM@%t%t{DlClBl=l@5@e8ge-312 3+)((((((!w !egH!0($* 0 P XXYmHB @M@MO! KFEAPP=!3.0!-**!\|#zv((0~~kQ3KPtRNG1E!?8113111/!1%t%tt!0>1 m1Y  ؠԠ!К    ƍ3.zZYHצ S"OPPP)H-D >W<;:7-.0[2/K.P'- ƠP( *+Ĵ(D ƽ~oL YmKHP%t%tmYP m &H׊EI<:H׊5:מ7Wj*'m%-&'`uSQP I  ď1ȏ  ͯį٬ 4+!@G+'&#% W K(; @Bt @BX/H%W hX!PfHlh,m 7Yv4%X L^%t%tf:X^aYF U!   T2`aES_!  ){}1!!d! !Ѳ1FBrqp<    ]7Y4X1W.UW& [@!R!!O%M)K-.N.t۬AHXH(!W  !  H"}2%tĴP4.+1-%t%t_+h)&%$#%!P1ĺį(0Ž  -/ /)*" &#SU\[__c] Şh 1ln .*-(()$!S!LÞRV 1  0'hXP +!8E%Y 1 #Ӟ MoP{Y ŞnhXPO %t%tX'"$w1$!!(1(!( ݚޚ۞-lxyŚƚij"$Msd1}H!K򏊩Ҩoj(esdW КSP[fZc҃ڀJ;v@t"d"u@'qo8s/8.!h fP7(&/]0[01̛-ɲ!Dś(HRKPI! 3. HEFGHILJK!!  "!&$sP:GWJ%t"2%t%tQ2s}H  0!($O`ЗNĴPPqqh::X98543?NQc["lh#cwrqX€/1МW0W ע @([F h S/!FF1BM; 6&K)1,s--v+z%"[1ahg1J0!m0Pqrvw%t%tJy#X3K9UMTb0Ǻ.ֺĺͺ%κźϺԺ$Ժ*ע @([1F h S!FF1BM; 6&K ĠԠؠĴɯϠҠĠ ĠҺ xPнؽӽ h>Z=: <8 <%t%tC88Ah !М1(' (@1,/ЛP6990h=n@"  ! @hX@D@B@@@ lh ҭ<@=<(4 HR2у(@ 0!0!2Pu %he4š 1T  !  Ɓ- .NP1 %T"B=w1'! @#Л.%t%t< *Pnh "x{X (sH ,lM- P0+&Q2 Q2L0%Q2"0#VQ2/0Q2(2 ;gU`ME<yp(   fs)"wPPqP255R" Q" 0"BҶF[KR22lPP更P2[[T"ZD`N IJŲY Π Ԡ%t%t 5ĠŠҠҠҠԠŠҠ Ԡ̠ΠԠŠŠŠſ:+@ [@<T" 6% A /2_R@?hZ ꄚ l1Aڂo szךkU|22 MwAcval1],DI9QPJX ✲YJC;~---*=)@<&1%1%t%t. @=@> @8@= @:@=lh ǀP'(Y= P*:Id8޴⣶^Դ(Ơ( 41ĊV2;Ġ/¾ ć/F34ⰴPܚ7'@ 2=)X92H1*()&!%溜vqX9Wl 1!bik33 2  GGJFLAzО#~#'P*H/4!Ċ@W@AA 1N?PKJO0I,X1{H& _a_!gcX1nWpqq 1%t%t! 0 sb ! |~P!OĊ1u@41m1o11 摴8m15m1.Fީާ椴(!歜МI1!ƍm1I1 Im1Wm1I1!ZU2ۮY [I1ٶ܄  "ƌm!ۤH! P1C("ƌm!@$귴"1⯴򁲢:H'PH&1 ڏĊ  ČچڅĊo!ډo!zI!@$~|}zy%t%t" !$tsPponqlkmifPH][W0h@%@&;W"Ơm!&ƍm!?" >  160!Čo!)!P!hZ hn!,Bd!"7 U" ZB2T%t%t( !@12 h$l(* / z v#zڤڢ롲w,'hDXDFОLM޶NܶOڶ@!ꇴHОJW PPPPN1 %t%t#U≴E!₲AggQ=N>AWRarjBbF!LPSJI򪶩RI2A5oVVm SHM@DlClBl=l@5@e8ge-312 3+)((((((!w !egH!0($* 0 P XX*+)**(&&$8EaQWtzqQWd@VdS(0 i! HTP&}&<-'x(\('''z''2'M'?'r'}'PRREBULGLPBACHIVOSRTRWRRDRCTCWCRATAWARMTMRGOIVERADLCCTCIMODMRERR%t%t%FCOMTXUNCTSDADRPFVLDREOBTEOBRAOKRNOKFTMOLTMORINGDSRYSIGQBFOKBNOK***%%&l&&%%%(%))))) WfWe+;/;?&<'&L)&'')&(%(@!Ill QWyj^lUj_lU j`lUi[UQWjy@8!P 8AH8   I8tzX8@<I8 Wf%1P@8}8  ( @< m90'v@<(@"Dm9X"m9 I9TtTT*P ON OFF%r os ot!QW& YD 2 X 2%t%t& X 2 X 2   2 DSX(&DXT"  :(XSD( k1QWXgr k1QWXgs gkY g1 YY(Y1Y$%QW"\QW%ttk1QWXtzg i|&Y&x ! QW ixZk1QWXiPWai gvwlmut1 z0r|Prgq#Pg%t%t'irYsdPp nF(Z!hf    cfW  0 PH](]F+XFS 1 3W Z>"AC"&'GH(o0(OQ45(XG^ͮͣ:-'G !g"""˽"x2<2<2<2K-!cìõT'KlYPnÈ>2->2!-"-H!F*p#q#"!5ʈ!F*p#q#r#s#"!5ʈ5ʈ!F*p#q#"!5È!F*p#q#r#s#"%t%t,!5ʈ5È##^#Vs+rD*V:-G@v]!^vBKPYpz*"2Ô]T) K4 &s#r!s#r#!K- "4:-G6^V ͊:-O>^X"͊:-WF^Z$͊:-_3N^\&͊{y'=S`x*4 :-s x| ʄ ʒ *4 &>2R, M ~2"Snf66| !Nnf ^#V "y%t%t- $(,048<@DHLPTX\`dhlptx|  $(,048<@DHLPTX\`dhlptx|͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟%t%t.͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟͟ ͟>2!"l:-G*gU:-O-*gU:-W>*gU:-_O*gU ͼ ͼ "["]2_!_`!_[[!_[]œ!_4~7ï7nfnfnfnfû*-u t!u"t#u$t%u&t':%t%t/-*w0>2ͼ!"l:4 Ky:-_C8KQyKEKQySRKQy[_KQy>2K! !÷>2K!"!÷>2K!$!÷>2K!&!÷45A͙DKO:-yDKOx#Eg#Eg""#"E"g""""33#3E3g3333>2ͼ*-)|<2/!//:-Gʦ*!/SPSR9͙͇:-O*!7SPSR9͙͇:-W*!/?SP%t%t0SR9͙͇:-_'*!??SPSR 9͙͇!O:-o:-o~w0>w>w >wˇw>w *Pu&t'*-u$t%*R#u"t#*-+u t!ww w>2*!÷>2*! ÷>2*!÷>2* !÷w ͙ >2*i÷>2*i÷>2*i÷>2* i÷*-u t!p0 >2*!÷>2*!÷>2*!÷>2* !÷%t%t1~ O##-~ ~ w_ ww @w o g ͙ ~ GUOhnf~ w͙ w nf~ +wNxN_ N:-:-Gʖ>2!//:-Oʬ>2!77:-W>2!??:-_>2!GGK-> 7:-ww w w7~ ~ ~ ~>2ͼ!"l*w@:-G@*gH*gP*gX*g>!tw uw >2!*÷>2!*÷>2!*÷>2!*÷%t%t2~GOW͙7~KlYPnKlYPnTKl'YPǹ:-G?*pq ON*pq W]*pq _l*pq 'Hcd1l9!1 ((1v#|%%1P !^`(Kn"h (Pf{D 0Xk7ڍ߾  ڈh #$&+)V1 ^Rmjjg!ca_ HIZKL>(0PMWMy)%t%t3_1)Fddgio tvz~6 S 0  ޭ   (9 $ 1,!FԜZ1(&!E0 °°°°ӱӲӳӴ0K$i  "8K)i ݜ P Μ ɜK-i %t%t4㼜Kgi2㶴!㬼1S㨴P D Zt@㜴P㘜㖜-4E>㌴ ㉌〔 D|ZGu DP H 5ZGd Ki^p\ X,wjTVqYSO G1 (08hB:C=И  FhC 0(!FZS    OVMfhNTGacbR;  RK i "$! K(i21-68 %t%t  5 4?AA) }Khp`U(WHY id kw2j  s )"}(ƲĜ k?D2P1X0XF(1 ! ( D k?D2%t(08hB:C=И  FhC 0(!FZS    OVMfhNTGacbR;  RK i "$! K(i21-68 %t%t ?7D@@@8p8q0  nIPnIWx6zz&$(('*9'C# LAC0H/%$$  !os>9 S Wu w BCD T U V XO @1Ap8p<0=q>>?>>  +++DIAGNOSTIC ABORT+++  **SENSE INT. ACK. FROM DMU FALSE**  **FAIL****FAIL****FAIL****FAIL****FAIL****FAIL** **FAIL****FAIL****FAIL****FAIL****FAIL****FAIL** pSYT!$P A. INTERRUPT TEST:  T!$ P!YSD% ..PASS.. 2pn S YT!$P] B1. DMU SET SENSE FLAGS TEST: K II!I0I?T!$n!24P5YSD9T1S!-PnT!\YS D4JIT1 S!:PnT!jT4GYS DZT1 S! 8PnT!ye4GYS j[T1S1[5Ps4CYS Dyn **SENSE FLAG 1 NOT SET**  **SENSE FLAG 2 NOT SET**  **SENSE FLAG 3 NOT SET**  **AFTER DMU RESET, CPU ENABLE SENSE FLAG NOT SET BY DMU** [n S YT!$^P]^ HH!H1T!$n!PZYSDZT1S1[NPnT![04GYS DZT1 S1[LPnT!kB4GYS DZT1S! KPZ4CYS D[ B2. DMU RESET SENSE FLAGS TEST: Y **SENSE FLAG 1 NOT RESET** l **SENSE FLAG 2 NOT RESET** | **SENSE FLAG 3 NOT RESET**  **CPU ENABLE SENSE FLAG NOT RESET AFTER DMU RESET** pn0SYT!$P]^ nT1S! PT!4EYS D"[ T1S!PpH HI*I9n1%4N T1S1[?PnT!UD4GYS DZT1 S!+tPnT!dU4GYS D[T1 S!zPnT!sf4GYS DlT1S! Ps4CYS Dy[ C. SOFTWARE RESET ON ISTR AND SENSE FLAGS TEST: 4 **ISTR NOT RESET** O ..ISTR RESET PASS.. [ **SENSE INPUT READY TRUE (NOT RESET)** h **SENSE OUTPUT READY FALSE (NOT RESET)** ~ **SENSE INT. ACK. FALSE (NOT RESET)** p@S YT!$P]^ I"XҔ T1 S!P]^Z4GT1S! P~_4EYS DZ[XrT1 S!HPPT!wZ4GYS DZ_T1 S!ZPPV_T!Z;4JYS DZ T1S104YS DZPZ T1S1`PZ4YSDZPZ T1 S!!PX" T1=Pp4K 4EYS DZT18P_4EYS DZ[H$H$HH D1. UNCONDITIONAL INPUT :1248 TEST: X ..DATA GOOD.. m **DATA BAD** w **SENSE INPUT READY FALSE** **OUTPUT READY BIT OF ISTR NOT SET AFTER CPU ACCESSED OUTR** ..ISTR OUTPU T READY BIT SET BY CPU AFTER ACCESSING OUTR.. **OUTPUT READY BIT OF ISTR NOT RESET AFTER DMU LOADED OUTR** p@S YT!$P]^ D2. UNCONDITIONAL INPUT :2481 TEST: pȞ@S YT!$P]^ D3. UNCONDITIONAL INPUT :4812 TEST: ,p@S YT!$P ]^ D4. UNCONDITIONAL INPUT :8124 TEST: SpPS YT!$P"]^ablc } T1S!dPIT1S!PZ4K 4EYSDZT1S! PZYS D4GZ\[T1 S!DdPPT!)4GYS  DZZT1 S!VdPPT!J;4GYS DZT1S!gePX_Z4EYS ZT1 S!uePX_qPZ4GYS DZT1 S! PePX_Z4GYS DZ[ E1. UNCONDITIONAL OUTPUT :1248 TEST: ..SENSE OUTPUT READY TRUE.. **SENSE OUTPUT READY FALSE**   **NEW INPUT BIT OF ISTR NOT RESET AFTER DMU ACCESSED MBOX** / **NEW INPUT BIT OF ISTR NOT SET AFTER CPU LOADED MBOX**  QpPS YT!$ P$]^iblc E2. UNCONDITIONAL OUTPUT :2481 TEST: pPS YT!$ P&]^j  blc E3. UNCONDITIONAL OUTPUT :4812 TEST: pPS YT!$ P(]^kblc E4. UNCONDITIONAL OUTPUT :8124 TEST: p`S YT!$@P*]@ 8B1D{T1\4AYSDZXbIXlT1 S!ePlm Pb_Z4IYS DZ[ F01. LOAD RAM WITH 00 TEST: * AT ;p`S YT!$P,]@P F02. LOAD RAM WITH :FF TEST: Pfgh F03. RAM 1000--10FF TEST: hfgh F04. RAM 1100--11FF TEST: fgh F05. RAM 1200--12FF TEST:  fgh F06. RAM 1300--13FF TEST: fgh F07. RAM 1400--14FF TEST: fgh F08. RAM 1500--15FF TEST: f gh F09. RAM 1600--16FF TEST: fgh F10. RAM 1700--17FF TEST: fgh F11. RAM 1800--18FF TEST: fgh F12. RAM 1900--19FF TEST: 7fgh F13. RAM 1A00--1AFF TEST: Nfgh F14. RAM 1B00--1BFF TEST: efgh F15. RAM 1C00--1CFF TEST: |fgh F16. RAM 1D00--1D FF TEST: fgh F17. RAM 1E00--1EFF TEST: fgh F18. RAM 1F00--1FFF TEST:  fgh  F19. RAM 2000--20FF TEST: !f gh F20. RAM 2100--21FF TEST: "f!gh F21. RAM 2200--22FF TEST: #f"gh F22. RAM 2300--23FF TEST: $f#gh F23. RAM 2400--24FF TEST: 4%f$gh F24. RAM 2500--25FF TEST: K&f%gh F25. RAM 2600--26FF TEST: b'f&gh F26. RAM 2700--27FF TEST: y(f'gh F27. RAM 2800--28FF TEST: )f(gh F28. RAM 2900--29FF TEST: *f)gh F29. RAM 2A00--2AFF TEST: +f0gh F30. RAM 2B00--2BFF TEST: ,f1gh F31. RAM 2C00--2CFF TEST: -f2gh F32. RAM 2D00--2DFF TEST: .f3gh F33. RAM 2E00--2EFF TEST: /f4gh F34. RAM 2F00--2FFF TEST: 1p`SPYT!$ P.]l 0f5gh F35. RAM 3000--30FF TEST: [1f6gh F36. RAM 3100--31FF TEST: r2f7gh F37. RAM 3200--32FF TEST: 3f8gh F38. RAM 3300--33FF TEST: 4f9gh F39. RAM 3400--34FF TEST: 5f@gh F40. RAM 3500--35FF TEST: 6fAgh F41. RAM 3600--36FF TEST: 7fBgh F42. RAM 3700--37FF TEST: 8fCgh F43. RAM 3800--38FF TEST: 9fDgh F44. RAM 3900--39FF TEST: *:fEgh F45. RAM 3A00--3AFF TEST: A;fFgh F46. RAM 3B00--3BFF TEST: XfIgh F49. RAM 3E00--3EFF TEST: ?fPgh F50. RAM 3F00--3FFF TEST: @fQgh F51. RAM 4000--40FF TEST: AfRgh F52. RAM 4100--41FF TEST: BfSgh F53. RAM 4200--42FF TEST: CfTgh F54. RAM 4300--43FF TEST: DfUgh F55. RAM 4400--44FF TEST: 'EfVgh F56. RAM 4500--45FF TEST: >FfWgh F57. RAM 4600--46FF TEST: UGfXgh F58. RAM 4700--47FF TEST: lHfYgh F59. RAM 4800--48FF TEST: If`gh F60. RAM 4900--49FF TEST: Jfagh F61. RAM 4A00--4AFF TEST: Kfbgh F62. RAM 4B00--4BFF TEST: Lfcgh F63. RAM 4C00--4CFF TEST: Mfdgh F64. RAM 4D 00--4DFF TEST: Nfegh F65. RAM 4E00--4EFF TEST:  Offgh F66. RAM 4F00--4FFF TEST: $ppS YT!$wP0]jlcZ T1S!$PZ4CYS DZ T1S!PX_P!_Z"_Z4NYS DZ[ -T1S{!GP4CYS DZ =T1S!WeP,4CYS DZ T1`PZ4CYSDZ G1. DMA READ :4812 FROM LOC. :1FFF TEST:  **DMA READ CYCLE STARTS BEFORE INR IS EMPTIED BY DMU**  **NO DMA COMPLETION INTERRUPT**  **DMA DONE BIT OF ISTR NOT SET**  FROM  **DMA FAIL ** ppS YT!$LP8]jбk$lc[ رT1S!G-P4CYS DZ     G2. DMA READ :4812 FROM LOC. :1FFF, :8124 FROM :2000 TEST: @pƀS YT!$P:]YlctZII T1S!&PZ4CYS DZ T1S!P_P_YZU_PY_Z4RYS DZ[ T1S!EP4CYS DZ T1S!SP,4QYS DZ KjYk T1`PZ4CYSDZT1S!vePO4CYS DZ H1. DMA WRITE :4812 TO LOC. :1FFF TEST:  **DMA WRITE CYCLE STARTS BEFORE OUTR IS LOADED BY DMU**  AT pƀS YT!$%P@]Y췷lc H2. DMA WRITE :4812 TO :1FFF, :8124 TO :2000 TEST: /pƐSYT!$=PB]^ pT1S!ZPZ4CYS DZ T1Sm! AWRarjBbF!LPSJI򪶩RI2A5oVVm SHM@DlClBl=l@5@e8ge-312 3+)(((<(((!w !egH!0($* 0 P XXm SHM@DlClBl=l@5@e8ge-312 3+)((( ?7D@@@ 8p8q0  nIPnI1f! %&&&$(('*9'C# LAC0H$   dh3- G Kj k t456 H I J LD @ 1Ap8p<0=q>>? @!PP @<m9 --PP      [ \ ln@8AI 8B T1 S!1PT1 ;P4HYS DT1S1 uP 4YS D ,6PT!iZ <<>>  +++DIAGNOSTIC ABORT+++  **SENSE INT. ACK. FROM DMU FALSE**  **FAIL****FAIL****FAIL****FAIL****FAIL****FAIL** **FAIL****FAIL****FAIL****FAIL****FAIL****FAIL** pSYT!$P A. INTERRUPT TEST:  T!$ P!YSD% ..PASS.. &pn S YT!$P] B1. DMU SET SENSE FLAGS TEST: ? II!I0I?T!$n!24P5YSD9T1S!-PnT!\4FYS DIT1 S!:PnT!jT4GYS DZT1 S! 8PnT!ye4GYS j[T1S1[5Ps4CYS Dyn **SENSE FLAG 1 NOT SET**  **SENSE FLAG 2 NOT SET**  **SENSE FLAG 3 NOT SET**  **AFTER DMU RESET, CPU ENABLE SENSE FLAG NOT SET BY DMU** [n S YT!$^P]^ HH!H1T!$n!PZYSDZT1S1[NPnT![04GYS DZT1 S1[LPnT!kB4GYS DZT1S! KPZ4CYS D[ B2. DMU RESET SENSE FLAGS TEST: M **SENSE FLAG 1 NOT RESET** ` **SENSE FLAG 2 NOT RESET** p **SENSE FLAG 3 NOT RESET**  **CPU ENABLE SENSE FLAG NOT RESET AFTER DMU RESET** pn0SYT!$P]^ nT1S! PT!4EYS D"[ T1S!PpH HI*I9n1%4N T1S1[?PnT!UD4GYS DZT1 S!+tPnT!dU4GYS D[T1 S!zPnT!sf4GYS DlT1S! Ps4CYS Dy[ C. SOFTWARE RESET ON ISTR AND SENSE FLAGS TEST: ( **ISTR NOT RESET** C ..ISTR RESET PASS.. O **SENSE INPUT READY TRUE (NOT RESET)** \ **SENSE OUTPUT READY FALSE (NOT RESET)** r **SENSE INT. ACK. FALSE (NOT RESET)** p@S YT!$P]^ I"XҔ T1 S!P ]^Z4GT1S! P~_4EYS DZ[XrT1 S!HPPT!wZ4GYS DZ_T1 S!ZPPV_T!Z;4JYS DZ T1S104YS DZPZ T1S1`PZ4YSDZPZ T1 S!!PX" T1=Pp4K 4EYS DZT18P_4EYS DZ[H$H$HH D1. UNCONDITIONAL INPUT :1248 TEST: L ..DATA GOOD.. a **DATA BAD** k **SENSE INPUT READY FALSE** t **OUTPUT READY BIT OF ISTR NOT SET AFTER CPU ACCESSED OUTR** ..ISTR OUTPUT READY BIT SET BY CPU A FTER ACCESSING OUTR.. **OUTPUT READY BIT OF ISTR NOT RESET AFTER DMU LOADED OUTR** p@S YT!$P]^ D2. UNCONDITIONAL INPUT :2481 TEST: pȞ@S YT!$P]^ D3. UNCONDITIONAL INPUT :4812 TEST: p@S YT!$P ]^ D4. UNCONDITIONAL INPUT :8124 TEST: GpPS YT!$P"]^ablc q T1S!dPIT1S!PZ4K 4EYSDZT1S! PZ4CYS DZ\[T1 S!DdPPT!)4GYS DZZT1 S!VdPP T!J;4GYS DZT1S!gePX_Z4EYS ZT1 S!uePX_pPZ4GYS DZT1 S! PePX_Z4GYS DZ[ E1. UNCONDITIONAL OUTPUT :1248 TEST: ..SENSE OUTPUT READY TRUE..  **SENSE OUTPUT READY FALSE**  **NEW INPUT BIT OF ISTR NOT RESET AFTER DMU ACCESSED INR** # **NEW INPUT BIT OF ISTR NOT SET AFTER CPU LOADED INR** DpPS YT!$ P$]^iblc v E2. UNCONDITIONAL OUTPUT :2481 TEST: wpPS YT!$ P&]^jblc E3. UNCONDITIONA L OUTPUT :4812 TEST: pPS YT!$ P(]^kblc E4. UNCONDITIONAL OUTPUT :8124 TEST: p`S YT!$@P*]@ 8B1DpT1\4AYSDZXbIXlT1 S!ePlm Pb_Z4IYS DZ[ F01. LOAD RAM WITH 00 TEST:  AT -p`S YT!$P,]@P F02. LOAD RAM WITH :FF TEST: Bfgh F03. RAM 1000--10FF TEST: Zfgh F04. RAM 1100--11FF TEST: qfgh F05. RAM 1200--12FF TEST: fgh F06. RA M 1300--13FF TEST: fgh F07. RAM 1400--14FF TEST: fgh F08. RAM 1500--15FF TEST: f gh F09. RAM 1600--16FF TEST: fgh F10. RAM 1700--17FF TEST: fgh F11. RAM 1800--18FF TEST: fgh F12. RAM 1900--19FF TEST: )fgh F13. RAM 1A00--1AFF TEST: @fgh F14. RAM 1B00--1BFF TEST: Wfgh F15. RAM 1C00--1CFF TEST: nfgh F16. RAM 1D00--1DFF TEST: fgh   F17. RAM 1E00--1EFF TEST: fgh F18. RAM 1F00--1FFF TEST:  fgh F19. RAM 2000--20FF TEST:  !f gh F20. RAM 2100--21FF TEST: "f!gh F21. RAM 2200--22FF TEST: #f"gh F22. RAM 2300--23FF TEST: $f#gh F23. RAM 2400--24FF TEST: &%f$gh F24. RAM 2500--25FF TEST: =&f%gh F25. RAM 2600--26FF TEST: T'f&gh F26. RAM 2700--27FF TEST: k(f'gh F27. RAM 2800--28FF TEST: )f(gh F28. RAM 2900--29FF TEST: *f)gh F29. RAM 2A00--2AFF TEST: +f0gh F30. RAM 2B00--2BFF TEST: ,f1gh F31. RAM 2C00--2CFF TEST: -f2gh F32. RAM 2D00--2DFF TEST: .f3gh F33. RAM  2E00--2EFF TEST:  /f4gh F34. RAM 2F00--2FFF TEST: #p`SPYT!$ P.]l 0f5gh F35. RAM 3000--30FF TEST: M1f6gh F36. RAM 3100--31FF TEST: d2f7gh F37. RAM 3200--32FF TEST: {3f8gh F38. RAM 3300--33FF TEST: 4f9gh F39. RAM 3400--34FF TEST: 5f@gh F40. RAM 3500--35FF TEST: 6fAgh F41. RAM 3600--36FF TEST: 7fBgh F42. RAM 3700--37FF TEST: 8fCgh F43. RAM 3800--38FF TEST: 9fDgh F44. RAM 3900--39FF TEST: :fEgh F45. RAM 3A00--3AFF TEST: 3;fFgh  F46. RAM 3B00--3BFF TEST: JfIgh F49. RAM 3E00--3EFF TEST: ?fPgh F50. RAM 3F00--3FFF TEST: @fQgh F51. RAM 4000--40FF TEST: AfRgh F52. RAM 4100--41FF TEST: BfSgh F53. RAM 4200--42FF TEST: CfTgh F54. RAM 4300--43FF TEST: DfUgh F55. RAM 4400--44FF TEST: EfVgh F56. RAM 4500--45FF TEST: 0FfWgh F57. RAM 4600--46FF TEST: GGfXgh F58. RAM 4700--47FF TEST: ^HfYgh F59. RAM 4800--48FF TEST: uIf`gh F60. RAM 4900--49FF TEST: Jfagh F61. RAM 4A00--4AFF TEST: Kfbgh F62. RAM 4B00--4BFF TEST: Lfcgh F63. RAM 4C00--4CFF TEST: Mfdgh F64. RAM 4D00--4DFF TEST: Nfegh F65. RAM 4E00--4EFF TEST: Offgh F66. RAM 4F00--4FFF TEST: ppS YT!${P0]jlI2nlc T1S!$PZ4CYS DZ T1S!PX_P!_Z"_Z4NYS DZ[ -T1S!GP4CYS DZ{ =T1S!WeP,4CYS DZ T1`PZ4CYSDZ G1. DMA READ :4812 FROM LOC. :1FFF TEST:  **DMA READ CYCLE STARTS BEFORE INR IS EMPTIED BY DMU**  **NO DMA COMPLETION INTERRUPT**  **DMA DONE BIT OF ISTR NOT SET**  FROM  **DMA FAIL BIT OF ISTR SET** ppS YT!$LP8]jױk$lc[ ߱T1S!G4P4CYS DZ     G2. DMA READ :4812 FROM LOC. :1FFF, :8124 FROM :2000 TEST: =pƀS YT!$P:]Ylc?? tT1S!&PZ4CYS DZ T1S!P_P_YZT_PX_Z4RYS DZ[ T1S!EP4CYS DZ T1S!SP,4QYS DZ KjYk T1`PZ4CYSDZT1S!vePO4CYS DZ H1. DMA WRITE :4812 TO LOC. :1FFF TEST:  **DMA WRITE CYCLE STARTS BEFORE OUTR IS LOADED BY DMU**  AT pƀS YT!$%P@]Y뷷lc H2. DMA WRITE :4812 TO :1FFF, :8124 TO :2000 TEST: +pƐSYT!$=PB]^ pT1S!ZPZ4CYS DZ T1S! AWRarjBbF!LPSJI򪶩RI2A5oVVm SHM@DlClBl=l@5@e8ge-312 3+)((((((!w !egH!0($* 0 P XX .NP1 %T"B=w1'! @#Л.<ś *Pnh "x{X (sH ,lM- P0+&Q2 Q2L0%Q2"0#VQ2/0Q2(2 ;gU`ME<yp(    fs)"wPPqP255R" Q" 0"BҶF[KR22lP XX .NP1 %T"B=w1'! @#Л. ?7D@@@8p8q0  nIPnIWx6zz&$(('*9'C# LAC0H/%$$  !os>9 S Wu w BCD T U V XO @1Ap8p<0=q>>?>>  +++DIAGNOSTIC ABORT+++  **SENSE INT. ACK. FROM DMU FALSE **  **FAIL****FAIL****FAIL****FAIL****FAIL****FAIL** **FAIL****FAIL****FAIL****FAIL****FAIL****FAIL** pSYT!$P A. INTERRUPT TEST:  T!$ P!YSD% ..PASS.. 2pn S YT!$P] B1. DMU SET SENSE FLAGS TEST: K II!I0I?T!$n!24P5YSD9T1S!-PnT!\YS D4JIT1 S!:PnT!jT4GYS DZT1 S! 8PnT!ye4GYS j[T1S1[5Ps4CYS Dyn **SENSE FLAG 1 NOT SET**  **SENSE FLAG 2 NOT SET**  **SENSE FLAG 3 NOT SET**  **AFTER DMU RESET, CPU ENABLE SENSE FLAG NOT SET BY DMU** [n S YT!$^P]^ HH!H1T!$n!PZYSDZT1S1[NPnT![04GYS DZT1 S1[LPnT!kB4GYS DZT1S! KPZ4CYS D[ B2. DMU RESET SENSE FLAGS TEST: Y **SENSE FLAG 1 NOT RESET** l **SENSE FLAG 2 NOT RESET** | **SENSE FLAG 3 NOT RESET**  **CPU ENABLE SENSE FLAG NOT RESET AFTER DMU RESET** pn0SYT!$P]^ nT1S! PT!4EYS D"[ T1S!PpH HI*I9n1%4N T1S1[?PnT!UD4GYS DZT1 S!+tPnT!dU4GYS D[T1 S!zPnT!sf4GYS DlT1S! Ps4CYS Dy[ C. SOFTWARE RESET ON ISTR AND SENSE FLAGS TEST: 4 **ISTR NOT RESET** O ..ISTR RESET PASS.. [ **SENSE INPUT READY TRUE (NOT RESET)** h **SENSE OUTPUT READY FALSE (NOT RESET)** ~ **SENSE INT. ACK. FALSE (NOT RESET)** p@S YT!$P]^ I"XҔ T1 S!P]^Z4GT1S! P~_4EYS DZ[XrT1 S!HPPT!wZ4GYS DZ_T1 S!ZPPV_T!Z;4JYS DZ T1S104YS DZPZ T1S1`PZ4YSDZPZ T1 S!!PX" T1=Pp4K 4EYS DZT18P_4EYS DZ[H$H$HH D1. UNCONDITIONAL INPUT :1248 TEST: X ..DATA GOOD.. m **DATA BAD** w **SENSE INPUT READY FALSE** **OUTPUT READY BIT OF ISTR NOT SET AFTER CPU ACCESSED OUTR** ..ISTR OUTPU T READY BIT SET BY CPU AFTER ACCESSING OUTR.. **OUTPUT READY BIT OF ISTR NOT RESET AFTER DMU LOADED OUTR** p@S YT!$P]^ D2. UNCONDITIONAL INPUT :2481 TEST: pȞ@S YT!$P]^ D3. UNCONDITIONAL INPUT :4812 TEST: ,p@S YT!$P ]^ D4. UNCONDITIONAL INPUT :8124 TEST: SpPS YT!$P"]^ablc } T1S!dPIT1S!PZ4K 4EYSDZT1S! PZYS D4GZ\[T1 S!DdPPT!)4GYS  DZZT1 S!VdPPT!J;4GYS DZT1S!gePX_Z4EYS ZT1 S!uePX_qPZ4GYS DZT1 S! PePX_Z4GYS DZ[ E1. UNCONDITIONAL OUTPUT :1248 TEST: ..SENSE OUTPUT READY TRUE.. **SENSE OUTPUT READY FALSE**   **NEW INPUT BIT OF ISTR NOT RESET AFTER DMU ACCESSED MBOX** / **NEW INPUT BIT OF ISTR NOT SET AFTER CPU LOADED MBOX**  QpPS YT!$ P$]^iblc E2. UNCONDITIONAL OUTPUT :2481 TEST: pPS YT!$ P&]^j blc E3. UNCONDITIONAL OUTPUT :4812 TEST: pPS YT!$ P(]^kblc E4. UNCONDITIONAL OUTPUT :8124 TEST: p`S YT!$@P*]@ 8B1D{T1\4AYSDZXbIXlT1 S!ePlm Pb_Z4IYS  DZ[ F01. LOAD RAM WITH 00 TEST: * AT ;p`S YT!$P,]@P F02. LOAD RAM WITH :FF TEST: Pfgh F03. RAM 1000--10FF TEST: hfgh F04. RAM 1100--11FF TEST: fgh F05. RAM 1200--12FF TEST:  fgh F06. RAM 1300--13FF TEST: fgh F07. RAM 1400--14FF TEST: fgh F08. RAM 1500--15FF TEST: f gh F09. RAM 1600--16FF TEST: fgh F10. RAM 1700--17FF TEST: fgh F11. RAM 1800--18FF TEST: fgh F12. RAM 1900--19FF TEST: 7fgh F13. RAM 1A00--1AFF TEST: Nfgh F14. RAM 1B00--1BFF TEST: efgh F15. RAM 1C00--1CFF TEST: |fgh F16. RAM 1D00--1D FF TEST: fgh F17. RAM 1E00--1EFF TEST: fgh F18. RAM 1F00--1FFF TEST:  fgh  F19. RAM 2000--20FF TEST: !f gh F20. RAM 2100--21FF TEST: "f!gh F21. RAM 2200--22FF TEST: #f"gh F22. RAM 2300--23FF TEST: $f#gh F23. RAM 2400--24FF TEST: 4%f$gh F24. RAM 2500--25FF TEST: K&f%gh F25. RAM 2600--26FF TEST: b'f&gh F26. RAM 2700--27FF TEST: y(f'gh F27. RAM 2800--28FF TEST: )f(gh F28. RAM 2900--29FF TEST: *f)gh F29. RAM 2A00--2AFF TEST: +f0gh F30. RAM 2B00--2BFF TEST: ,f1gh F31. RAM 2C00--2CFF TEST: -f2gh F32. RAM 2D00--2DFF TEST: .f3gh F33. RAM 2E00--2EFF TEST: /f4gh F34. RAM 2F00--2FFF TEST: 1p`SPYT!$ P.]l 0f5gh F35. RAM 3000--30FF TEST: [1f6gh F36. RAM 3100--31FF TEST: r2f7gh F37. RAM 3200--32FF TEST: 3f8gh F38. RAM 3300--33FF TEST: 4f9gh F39. RAM 3400--34FF TEST: 5f@gh F40. RAM 3500--35FF TEST: 6fAgh F41. RAM 3600--36FF TEST: 7fBgh F42. RAM 3700--37FF TEST: 8fCgh F43. RAM 3800--38FF TEST: 9fDgh F44. RAM 3900--39FF TEST: *:fEgh F45. RAM 3A00--3AFF TEST: A;fFgh F46. RAM 3B00--3BFF TEST: XfIgh F49. RAM 3E00--3EFF TEST: ?fPgh F50. RAM 3F00--3FFF TEST: @fQgh F51. RAM 4000--40FF TEST: AfRgh F52. RAM 4100--41FF TEST: BfSgh F53. RAM 4200--42FF TEST: CfTgh F54. RAM 4300--43FF TEST: DfUgh F55. RAM 4400--44FF TEST: 'EfVgh F56. RAM 4500--45FF TEST: >FfWgh F57. RAM 4600--46FF TEST: UGfXgh F58. RAM 4700--47FF TEST: lHfYgh F59. RAM 4800--48FF TEST: If`gh F60. RAM 4900--49FF TEST: Jfagh F61. RAM 4A00--4AFF TEST: Kfbgh F62. RAM 4B00--4BFF TEST: Lfcgh F63. RAM 4C00--4CFF TEST: Mfdgh F64. RAM 4D00--4DFF TEST: Nfegh F65. RAM 4E00--4EFF TEST:  Offgh F66. RAM 4F00--4FFF TEST: $ppS YT!$wP0]jlcZ T1S!$PZ4CYS DZ T1S!PX_P!_Z"_Z4NYS DZ[ -T1S  {!GP4CYS DZ =T1S!WeP,4CYS DZ T1`PZ4CYSDZ G1. DMA READ :4812 FROM LOC. :1FFF TEST:  **DMA READ CYCLE STARTS BEFORE INR IS EMPTIED BY DMU**  **NO DMA COMPLETION INTERRUPT**  **DMA DONE BIT OF ISTR NOT SET**  FROM  **DMA FAIL ** ppS YT!$LP8]jбk$lc[ رT1S!G-P4CYS DZ     G2. DMA READ :4812 FROM LOC. :1FFF, :8124 FROM :2000 TEST: @pƀS YT!$P:]YlctZII T1S!&PZ4CYS DZ T1S!P_P_YZU_PY_Z4RYS DZ[ T1S!EP4CYS DZ T1S!SP,4QYS DZ KjYk T1`PZ4CYSDZT1S!vePO4CYS DZ H1. DMA WRITE :4812 TO LOC. :1FFF TEST:  **DMA WRITE CYCLE STARTS BEFORE OUTR IS LOADED BY DMU**  AT pƀS YT!$%P@]Y췷lc H2. DMA WRITE :4812 TO :1FFF, :8124 TO :2000 TEST: /pƐSYT!$=PB]^ pT1S!ZPZ4CYS DZ T1Sm! AWRarjBbF!LPSJI򪶩RI2A5oVVm SHM@DlClBl=l@5@e8ge-312 3+)(((<(((!w !egH!0($* 0 P XXm SHM@DlClBl=l@5@e8ge-312 3+)(((" # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L