IMD 1.16: 2/09/2008 10:38:27 84-93814-03-c000 (f81403) pat 495 source product diskette    @0|)wwЀЀtQql)  " }gA ` MIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOS4 MF081110213570100811116111548 8111161115480F81403 VOLPAT495 DIAGNOSTIC 84-93814-03-C000   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII M@jjggg@ o G`k_C# b# }B u[ ]e JRiCCp@<;: F8P@ G;NPCHC C GTqE'ɞ * Cϟx @0DAJL )‘ЀЀΎQBx"  i+ fEB)3 `jmBBI,v  BI,m  @EEFF)D^EF% jH@pOğv g7g4]X] PhV+s=胾c_N GF֞ؾ “@ALS)"$ C k1/j-h p vRw ppwp ki 15 !^\d X %'+Ns愾Q)s ED|{ @$ o O m J K i g. V tsFn`"FED) E`Cnrgy w"N{Rq1H }L2`0tG- Bc (>=,64K,CANNOT,BE,TESTED,WITHOUT,MMU. * ENTERED VALUE STORED IN A REG * REENTER MEMORY SIZE IN A REG * BITS 8-15 IN 64K INC'S AND RESUME. * M10180 EQU $ REPLACE MEMORY SIZE SELECTION AND =:FF00,A CLEAR LOWER BYTE OF MEMORY SIZE SELECTION  COPY DMAND2,Q GET MODE SELECT WORD 2 AND =:FF,Q STRIP OFF OLD MEMORY SIZE SELECTION OR A,Q OR IN CORRECT MEMORY SIZE COPY Q,DMAND2 STORE NEW MODE SELECT WORD 2 JMP M10100  RE-EXECUTE MEMORY SIZE CALCULATION TITL M10190 EQU $ IN 4,Q LOAD Q REG WITH MEMORY SIZE  OR A,Q OR IN MEMORY TEST CODE SELP Q,4 OUTPUT TO CONSOLE DISPLAY SHIFT A,R,8  RIGHT JUSTIFY MEMORY SIZE COPY A,MEMSIZ SAVE FOR MEMORY TEST USE COPY A,MEMSZ0 SAVE FOR MEMORY TEST USE COPY A,MEMSZ1 SAVE FOR MEMORY TEST USE COPY A,MEMSZ2 SAVE FOR MEMORY TEST USE  COPY A,MEMSZ3 SAVE FOR MEMORY TEST USE COPY =:88,X MEMORY EXCEPTION TRAP LOCATION COPY =MET1,A UNEXPECTED ME TRAP ROUTINE LOCATION COPY A,3(X) STORE AT TRAP LOCATION JMP *M10100 * MEMSIZ RES 1,0 MEMORY SIZE IN 64K INCREMENTS TEMPME RES 1,0 TEMPORARY STORAGE FOR ME TRAP LOCATION P8001 WORD :8001 POINTER TO LOCATION :8001 LPOOL TITL 64K ADDRESSABILITY TEST (TEST A) * * 64K ADDRESSABILITY TEST * * THIS IS A PRELIMINARY TEST OF ADDRESS BIT 15, AND * A TEST OF INDIRECT ADDRESSING TO THE UPPER 32K * OF LOGICAL ADDRESS SPACE. * M10200 EQU $ COPY =0,A OUT A,4 RESET MMU COPY =:0E0D,A DATA COPY A,1  INITIALIZE LOCATION 1 COPY 1,A CHECK IT CSK A,=:0E0D COMPARE TO EXPECTED DATA NOP ERROR: LOCATION,1,SHOULD,=,:0E0D COPY =:8001,X TEST ADDRESS COPY =:6666,A TEST DATA COPY A,0(X) ATTEMPT WRITE TO LOCATION :8001 (INDEXED) COPY 1,A GET LOCATION 1 CONTENTS CSK A,=:0E0D COMPARE TO EXPECTE D DATA NOP ERROR: COPY,TO,LOCATION,:8001,ALTERED,LOCATION,1 SBIT 6,S SET XA COPY *P8001,A  ATTEMPT READ FROM LOCATION :8001 (INDIRECT) CSK A,=:6666 COMPARE TO EXPECTED DATA NOP ERROR: WRONG,DATA,STORED,IN,OR,LOADED,FROM,LOC,:8001 COPY =:0E0D,A DATA COPY A,1 WRITE TO LOCATION 1 COPY 0(X),A GET CONTENTS OF LOCATION :8001 CSK A,=:6666 COMPARE TO EXPECTED DATA NOP ERROR: WRITE,TO,LOCATION,1,ALTERED,LOCATION,:8001 JMP M10290 EXIT * M10290 EQU $ JMP M10200 PATCH FOR LOOPING ORG  $-1 NOP OVERLAY WITH NOP JMP M20000 * LPOOL TITL HIGH ORDER UNIQUE ADDRESS TEST (TEST A) * * * M20000 * * HIGH ORDER UNIQUE ADDRESS TEST * * THIS TEST EXERCISES THE UPPER 16 OF THE 22 MEMORY *  ADDRESS BITS AS FOLLOWS: * EVERY 64 LOCATIONS, A WORD IS WRITTEN WITH BITS * 6-21 OF ITS ADDRESS AS DATA. THE ADDRESSES OF THE * WORDS WRITTEN HAVE BITS 0-5 EQUAL TO ZERO. THIS * IS DONE FOR THE ENTIRE MEMORY SPACE EXCLUDING THE *  FIRST 32K (I.E.- :008000=:0200, :008000=:0201, * :008080=:0202, ETC). THE WRITTEN MEMORY SPACE IS * THEN VERIFIED. * * THE TEST IS PERFORMED IN TWO PARTS- FIRST IN * FORWARD ORDER (LOW ADDRESSES TO HIGH), THEN IN * REVERSE ORDER. * * THSI TEST IS PERFORMED ONLY IF AN MMU AND MORE * THAN 64K OF MEMORY ARE INSTALLED * * M20000 EQU $ COPY MEMSIZ,A TESTABLE MEMORY SIZE CSK A,=1 IS IT 64K ? NOP JMP $+2 EXECUTE TEST JMP M20290 MEMORY TOO SMALL - SKIP TEST TITL * * FORWARD ORDER WRITE * M20100 EQU $ * COPY =0,A  INITIALIZE: JST INIT1 ..TRANSLATE TABLE COPY =:0200,Q ..DATA COPY =0,A ..PHYSICAL ADDR. POINTER (HIGH BITS) COPY =:8000,X ..PHYSICAL ADDR. POINTER (LOW BITS) M20110 COPY =:8000,Y ..LOGICAL ADDR. POINTER * M20120 COPY Q,0(Y) WRITE DATA TO MEMORY ADD =1,Q MODIFY DATA ADD =:40,X -- INCREMENT JNE X,$+2 -- PHYSICAL ADD =1,A -- ADDRESS ADD =:40,Y INCREMENT LOGICAL ADDRESS JNE Y,M20120 END OF LOGICAL SPACE ? JUMP IF NOT JST INCTB1 MODIFY TRANSLATE TABLE CSK A,MEMSIZ END OF PHYSICAL ADDRESS SPACE ? NOP JMP M20110 NO, CONTINUE * TITL * * FORWARD ORDER VERIFY * COPY =0,A INITIALIZE: JST INIT1 ..TRANSLATE TABLE COPY =:0200,A COPY A,K ..EXPECTED DATA  COPY =1,A COPY A,L ..DATA MODIFIER COPY =0,A ..PHYSICAL ADDR. POINTER (HIGHBITS) COPY =:8000,X ..PHYSICAL ADDR. POINTER (LOW BITS) M20140 COPY =:8000,Y ..LOGICAL ADDR. POINTER * M20150 COPY 0(Y),Q READ DATA CSK Q,K COMPARE TO EXPECTED NOP ERROR: HIGH,ORDER,ADDRESS,TEST,FAILURE *  Q = ACTUAL DATA * K = EXPECTED DATA * AX = PHYSICAL ADDRESS * Y = LOGICAL ADDRESS * ADD L,K MODIFY DATA ADD =:40,X -- INCRE MENT JNE X,$+2 -- PHYSICAL ADD =1,A -- ADDRESS ADD =:40,Y INCREMENT LOGICAL ADDRESS  JNE Y,M20150 END OF LOGICAL ADDR. SPACE ? JUMP IF NOT JST INCTB1 MODIFY TRANSLATE TABLE CSK A,MEMSIZ END OF PHYSICAL ADDR. SPACE ? NOP JMP M20140 NO, CONTINUE * M20190 JMP M20000 PATCH FOR LOOPING  ORG $-1 NOP OVERLAY WITH NOP TITL * * REVERSE ORDER WRITE * M20200 EQU $ COPY =1,A INITIALIZE: JST INIT1 ..TRANSLATE TABLE COPY MEMSIZ,A SHIFT A,L,10 SUB =1,A COPY A,K ..DATA COPY =1,A COPY A,L ..DATA MODIFIER COPY MEMSIZ,A SUB  =1,A ..PHYSICAL ADDR. POINTER (HIGH BITS) COPY =:FFC0,X ..PHYSICAL ADDR. POINTER (LOW BITS) COPY =:FFC0,Y ..LOGICAL ADDR. POINTER * M20210 COPY K,Q DATA TO Q COPY Q,0(Y) WRITE DATA TO MEMORY SUB L,K  MODIFY DATA COPY Y,Q LOGICAL ADDR. TO Q CSK Q,=:8000 END OF LOGICAL SPACE ? NOP JMP M20230 NO, CONTINUE CSK A,=0 YES; END OF PHYSICAL ADDR. SPACE? NOP JMP $+2 NO  JMP M20240 YES, GO TO VERIFY JST DECTB1 MODIFY TRANSLATE TABLE COPY =0,Y INITIALIZE LOGICAL ADDRESS M20230 SUB =:40,Y DECREMENT LOGICAL ADDRESS JNE X,$+2 -- DECREMENT SUB =1,A -- PHYSICAL SUB =:40,X -- ADDRESS JMP M20210 CONTINUE TITL * * REVERSE ORDER VERIFY * M20240 EQU  $ COPY =1,A INITIALIZE: JST INIT1 ..TRANSLATE TABLE COPY MEMSIZ,A SHIFT A,LO,10  SUB =1,A COPY A,K ..DATA COPY =1,A COPY A,L ..DATA MODIFIER COPY MEMSIZ,A SUB =1,A .. PHYSICAL ADDR. POINTER (HIGH BITS) COPY =:FFC0,X .. PHYSICAL ADDR. POINTER (LOW BITS)  COPY =:FFC0,Y .. LOGICAL ADDR. POINTER * M20250 EQU $ COPY 0(Y),Q GET DATA FROM MEMORY CSK Q,K  COMPARE TO EXPECTED DATA NOP ERROR: HIGH,ORDER,ADDRESS,TEST,FAILURE * Q = ACTUAL DATA * K = EXPECTED DATA * AX = PHYSICAL ADDRESS *  Y = LOGICAL ADDRESS * SUB L,K MODIFY EXPECTED DATA COPY Y,Q LOGICAL ADDRESS TO Q CSK Q,=:8000 END OF LOGICAL ADDR. SPACE? NOP JMP M20260 NO CSK A,=0 YES; END OF PHYSICAL ADDR. SPACE ? NOP JMP $+2 NO,CONTINUE JMP M20290 YES,EXIT JST DECTB1 MODIFY TRANSLATE TABLE COPY =0,Y INITIALIZE LOGICAL ADDR. M20260 SUB =:40,Y DECREMENT LOGICAL ADDR. JNE X,$+2 -- DECREMENT SUB =1,A -- PHYSICAL SUB =:40,X -- ADDRESS JMP M20250 CONTINUE * M20290 EQU $ JST SSCHK CHECK SENSE SWITCH AND BLINK DISPLAY JMP M20200 PATCH FOR LOOPING ORG $-1 NOP OVERLAY WITH NOP JMP M30000 LPOOL TITL ****** * * GROUP 1 TRANSLATE TABLE SUBROUTINES * * INIT1 * INCTB1 * DECTB1 * * THESE SUBROUTINES MODIFY THE FIRST 64 WORDS OF THE * TRANSLATE TABLE. THE FIRST 32 TRANSLATE TABLE WORDS * POINT TO THE FIRST 32 1K PHYSICAL MEMORY PAGES * RESPECTIVELY. THE SECOND 32 TRANSLATE TABLE WORDS * POINT TO 32 CONSECUTIVE PHYSICAL MEMORY PAGES RESPEC- * TIVELY WHICH START ON A 32K BOUNDRY, AND WHICH FORM * THE MEMORY BLOCK BEING TESTED. * ****** * * SUBROUTINE INIT1 * * THIS SUBROUTINE INITIALIZES THE FIRST 32 TRANSLATE * TABLE WORDS TO POINT TO THE FIRST 32K WORD PHYSICAL * MEMORY BLOCK, AND INITIALIZES THE SECOND 32 TRANSLATE * TABLE WORDS TO POINT TO THE 32K WORD BLOCK INDICATED * BY THE A REGISTER AS FOLLOWS: * * A=0 --> SECOND 32 K OF MEMORY * A=1 --> LAST 32K OF MEMORY * * THIS SUBROUTINE LEAVES THE MMU WITH ONLY TRANSLATION * ENABLED. THE A, Q, AND X REGISTER, AND OV BIT CONTENTS * ARE DESTROYED. * INIT1 ENT  TBIT 0,A COPY A REG BIT 0 TO OV COPY =1,A OUT A,5 ENABLE TABLE ACCESS COPY =:FC00,X INITIALIZE TRANS. TABLE INDEX COPY =:3000,A INITIALIZE DATA (READ, WRITE, EXEC. ENBL.) INIT1A COPY A,0(X) WRITE TO TRANSLATE TABLE ADD =1,A INCREMENT DATA ADD =1,X INCREMENT INDEX COPY X,Q INDEX TO Q CSK Q,=:FC20 END OF FIRST 32 WORDS? NOP JMP INIT1A NO, CONTINUE JF OV,INIT1B YES; SECOND OR LAST 32K SELECTED? JUMP IF 2ND COPY MEMSIZ,A MEMORY SIZE IN 64K INCREMENTS SHIFT A,L,6 MEMORY SIZE IN 1K INCREMENTS SUB =:20,A TRANS. TABLE POINTER TO START OF LAST 32K INIT1B SBIT 13,A -- READ, WRITE RBIT 12,A -- ENABLE INIT1C COPY A,0(X) WRITE TO TRANSALTE TABLE ADD =1,A INCREMENT DATA  ADD =1,X INCREMENT INDEX COPY X,Q INDEX TO Q CSK Q,=:FC40 END OF SECOND 32 WORDS? NOP JMP INIT1C NO, CONTINUE IN 7,A CLEAR PARITY ERRORR COPY =2,A OUT A,5 ENABLE TRANSLATION, DISABLE TABLE ACCESS JMP *INIT1 RETURN * * SUBROUTINE INCTB1 * SUBROUTINE DECTB1 * * THESE SUBROUTINES MODIFY THE SECOND 32 TRANSLATE * TABLE WORDS TO POINT TO ONE OF THE TWO 32K BLOCKS * ADJACENT TO THE ONE PRESENTLY POINTED TO-- INCTB1 * TO THE ONE NEXT HIGHER IN ADDRESS SPACE, AND DECTB1 * TO THE NEXT LOWER. * THESE SUBROUTINES LEAVE THE MMU WITH ONLY TRANSLATION * ENABLED. ALL REGISTER CONTENTS ARE PRESERVED. * INCTB1 ENT ENTRY POINT FOR INCTB1 COPY Y,YTEMP SAVE Y REG COPY =0,Y LOAD Y WITH INCTB1 INDEX JMP TAB1A CONTINUE * DECTB1 ENT ENTRY POINT FOR DECTB1 COPY Y,YTEMP COPY DECTB1,Y GET DECTB1 RETURN POINTER  COPY Y,INCTB1 STORE IN INCTB1 RETURN POINTER LOC. COPY =:400,Y LOAD Y WITH DECTB1 INDEX * TAB1A COPY A,ATEMP SAVE A REG COPY X,XTEMP SAVE X REG COPY =1,A OUT A,5 ENABLE TABLE ACCESS COPY =:FC20,X INITIALIZE TRANSLATE TABLE INDEX TAB1B COPY 0(X),A GET DATA FROM TRANSLATE TABLE XNX Y INDEX FOR  EITHER INCTB1 OR DECTB1 ADD CNST20,A INCTB1 - DO ADD; DECTB1 - DO SUBTRACT COPY A,0(X) RESTORE DATA TO TRANSLATE TABLE ADD =1,X INCREMENT TRANSLATE TABLE INDEX. COPY X,A INDEX TO A REG. CSK A,=:FC40 END OF SECOND 32K? NOP JMP TAB1B NO, CONTINUE IN 7,A CLEAR PARITY ERROR COPY =2,A YES OUT A,5 ENABLE TRANSLATION, DISABLE TABLE ACCESS COPY YTEMP,Y -- COPY XTEMP,X -- RESTORE REGISTERS COPY ATEMP,A -- JMP *INCTB1 RETURN * CNST20 WORD :0020 TRANSLATE TABLE INCREMENT/DECREMENT VALUE * * * SUBROUTINE SSCHK * * THIS SUBROUTINE CHECKS FOR A CHANGE IN STATE OF THE * SENSE SWITCH. WHEN THIS OCCURS, IT EXITS THE MEMORY * TEST. IT ALSO BLINKS THE PART OF THE CONSOLE DISPLAY * INDICATING THE MEMORY SIZE (BITS 8-14). THE A AND X * REGISTERS ARE ALTERED. * SSCHK ENT COPY =0,Q CLEAR Q JF SS,$+2 -- COPY SENSE SWITCH COPY =1,Q -- TO Q XOR SENSW0,Q XOR WITH PREVIOUS SENSE SWITCH CONTENTS JNE Q,SSCHKA JUMP IF SENSE SWITCH CHANGED * IN 4,Q INPUT CONSOLE DISPLAY COPY MEMSIZ,Y LOAD Y WITH MEMORY SIZE SHIFT Y,L,8 MOVE TO LEFT BYTE XOR Y,Q  COMPLEMENT MEMORY SIZE INDICATOR BITS SELP Q,4 OUTPUT TO CONSOLE DISPLAY JMP *SSCHK  RETURN SSCHKA JMP M90000 * LPOOL TITL FIRST 64K TESTING (TEST A) ******** * * M30000 * *  FIRST 64K TESTING * * THIS SECTION TESTS THE FIRST 64K OF MEMORY. TESTING * IS DONE WITH NO ADDRESS TRANSLATION (I.E. MMU RESET). * * FIRST THE SECOND 32K OF MEMORY IS TESTED, THEN THE * CONTENTS OF THE FIRST 32K OF MEMORY IS COPIED TO THE * SECOND 32K AND VERIFIED, THEN CONTROL IS TRANSFERED * TO THE COPIED PROGRAM IN THE SECOND 32K. THE FIRST * 32K OF MEMORY IS THEN TESTED, THE CONTENTS OF THE * SECOND 32K OF MEMORY IS COPIED BACK TO THE FIRST 32K * AND VERIFIED, AND FINALLY CONTROL IS TRANSFERED BACK * TO THE COPIED PROGRAM IN THE FIRST 32K. * * TESTING OF EACH OF THE 32K SECTIONS OF MEMORY IS PER- * FORMED IN THREE PARTS: 1) LOW ORDER UNIQUE ADDRESS * TEST, 2) DATA TEST, AND 3) BYTE TEST. * * THE SAME CODE IS EXECUTED FOR TESTING BOTH THE FIRST * AND THE SECOND 32K OF MEMORY, AND THUS MUST BE EXE- * CUTABLE WHEN THE PROGRAM HAS RELOCATED ITSELF. * * TESTING EXCLUDES LOCATIONS :84-:8B (UNIMPLEMENTED * INSTRUCTION TRAP AND MEMORY EXCEPTION TRAP VECTORS). * DURING PROGRAM RELOCATION, THE TWO TRAPS CONTAIN * JUMPS TO SPECIAL SERVICE ROUTINES IN THE RELOCATED * PROGRAM. OCCURRENCE OF ANY OTHER INTERRUPTS OR TRAPS * DURING PROGRAM RELOCATION WILL HAVE UNDEFINED RESULTS. * ******** TITL * * INITIALIZATION * M30000 EQU $ COPY =0,A OUT A,4 RESET MMU * COPY =:8000,A -- COPY A,LOLIMX -- SET LOW COPY A,LOLIM0 -- MEMORY-TESTING COPY A,LOLIM1 -- LIMIT COPY A,LOLIM2  -- * COPY =:FFFF,A SET HIGH MEMORY- COPY A,HILIMX -- TESTING LIMIT * COPY =DATTB0,A -- COPY A,DATTBPT0 -- COPY =ECCTB0,A -- SET UP COPY A,ECCTBPT0 -- DATA TABLE COPY =DATTB1,A -- POINTERS COPY A,DATTBPT1 -- COPY =ECCTB1,A -- COPY A,ECCTBPT1 -- TITL ADDRESS TEST -- FIRST 64K TESTING (TEST A) ******** * * M31000 * * LOW ORDER UNIQUE ADDRESS TEST * * THIS TEST EXERCISES THE LOWER 16 OF THE 22 MEMORY * ADDRESS BITS AS FOLLOWS: * EVERY WORD IS WRITTEN WITH BITS 0-15 OF ITS ADDRESS * AS DATA, AND THEN VERIFIED. THIS IS DONE IN FORWARD * ORDER AND REVERSE ORDER. * ******** SPACE 2 * * FORWARD ORDER WRITE * M31000 EQU $ COPY LOLIMX,X INITIALIZE MEMORY ADDRESS COPY HILIMX,Q ADD =1,Q COPY Q,L SET HIGH MEMORY-TESTING LIMIT * M31010 COPY X,0(X) WRITE DATA TO TEST MEMORY GENECC . GENERATE ECC BITS STRECC .  WRITE ECC BITS TO TEST MEMORY ADD =1,X INCREMENT ADDRESS CSK X,=:84 REACHED TRAP VECTOR LOCATIONS ? JMP $+3 NO JMP $+2 NO ADD =8,X YES, MOVE ADDRESS PAST TRAP LOCATIONS * CSK X,L END OF MEMORY ? JMP M31010 NO, CONTINUE JMP M31010 NO, CONTINUE TITL * * FORWARD ORDER VERIFY * M31100 EQU $ COPY =0,A HIGH ORDER PHYSICAL ADDRESS TO A COPY LOLIMX,X INITIALIZE MEMORY ADDRESS M31110 COPY 0(X),Q READ DATA FROM TEST MEMORY CSK Q,X COMPARE TO EXPECTED NOP JMP $+2 ERROR JMP M31120 OK * COPY X,Y LOAD Y WITH LOGICAL ADDRESS COPY X,K LOAD K WITH EXPECTED DATA ERROR: LOW,ORDER,ADDRESS,TEST,FAILURE * Q = ACTUAL DATA *  K = EXPECTED DATA * AX = PHYSICAL ADDRESS * Y = LOGICAL ADDRESS * M31120 ADD =1,X INCREMENT ADDRESS * CSK X,=:84 REACHED TRAP VECTOR LOCATIONS ? JMP $+3 NO JMP $+2 NO ADD =8,X YES, MOVE ADDRESS PAST TRAP LOCATIONS *  CSK X,L END OF MEMORY ? JMP M31110 NO, CONTINUE JMP M31110 NO, CONTINUE TITL * * REVERSE ORDER WRITE * M31200 EQU $ COPY HILIMX,X INITIALIZE MEMORY ADDRESS  COPY LOLIMX,Q SUB =1,Q COPY Q,L SET LOW MEMORY-TESTING LIMIT * M31210 COPY X,0(X)  WRITE DATA TO MEMORY SUB =1,X DECREMENT ADDRESS * CSK X,=:8B REACHED TRAP LOCATIONS ? JMP $+3 NO JMP $+2 NO SUB =8,X YES, MOVE ADDRESS PAST TRAP LOCATIONS * CSK X,L END OF MEMORY ? JMP M31210 NO, CONTINUE JMP M31210  NO, CONTINUE TITL * * REVERSE ORDER VERIFY * M31300 EQU $ COPY HILIMX,X INITIALIZE MEMORY ADDRESS M31310 COPY 0(X),Q READ DATA FROM TEST MEMORY CSK Q,X COMPARE TO EXPECTED NOP  JMP $+2 ERROR JMP M31320 OK * COPY X,Y LOAD Y WITH LOGICAL ADDRESS  COPY X,K LOAD K WITH EXPECTED DATA ERROR: LOW,ORDER,ADDRESS,TEST,FAILURE *  Q = ACTUAL DATA * K = EXPECTED DATA * AX = PHYSICAL ADDRESS * Y = LOGICAL ADDRESS * M31320 SUB =1,X DECREMENT ADDRESS * CSK X,=:8B REACHED TRAP VECTOR LOCATIONS ? JMP $+3 NO JMP $+2 NO SUB =8,X  YES, MOVE ADDRESS PAST TRAP LOCATIONS * CSK X,L END OF MEMORY ? JMP M31310 NO, CONTINUE JMP M31310 NO, CONTINUE * JST SSCHK0 CHECK SENSE SWITCH AND BLINK DISPLAY  JMP M31000 PATCH FOR LOOPING THROUGH ADDRESS TEST ORG $-1 NOP OVERLAY WITH NOP JMP M3200A * LOLIMX RES 1,0 LOW MEMORY-TESTING LIMIT HILIMX RES 1,0 HIGH MEMORY-TESTING LIMIT LPOOL TITL DATA TEST -- FIRST 64K TESTING (TEST A) ******** * * M32000 * * RAM AND DATA PATH TEST * * THIS IS A SURROUND-DISTURB TEST OF THE RAMS, AND * A TEST OF THE RAM AND BOARD DATA PATHS. * *  THE PATTERNS WRITTEN BY THIS TEST ARE OPTIMAL FOR * SURROUND-DISTURB TESTING OF FOUR VENDOR'S 16K RAMS * (AS OF 3-79): MOSTEK, TEXAS INSTRUMENTS, FAIRCHILD, * AND NATIONAL . * * THE TEST CONSISTS OF FOUR SECTIONS: 1) TEST DATA * RAMS WITH MOSTEK AND TI PATTERNS, 2) TEST ECC RAMS * WITH MOSTEK AND TI PATTERNS, 3) TEST DATA RAMS WITH *  FAIRCHILD AND NATIONAL PATTERNS, AND 4) TEST ECC * RAMS WITH FAIRCHILD AND NATIONAL PATTERNS. THE RAMS * ARE TESTED WITH THE TWO COMPLEMENTARY PATTERNS FOR * EACH OF THE VENDORS. * * THE ECC RAM TESTING IS PERFORMED BY WRITING THE DATA * RAMS WITH A PARTICULAR PATTERN WHICH RESULTS IN THE * DESIRED TEST PATTERN BEING GENERATED BY THE MEMORY * LOGIC TO FILL THE ECC RAMS. THIS DATA IS THEN READ * FROM THE ECC RAMS DURING VERIFICATION. * ********  TITL * * MOSTEK AND TI PATTERN TESTING * * WRITE DATA RAMS * M3200A EQU $ COPY HILIMX,A  ADD =1,A COPY A,L SET HIGH MEMORY-TESTING LIMIT M32000 COPY =0,A COPY A,INDXV0  SET VENDOR INDEX FOR MOSTEK DATA M32010 COPY =0,A COPY A,INDXP0 SET PASS INDEX FOR 1ST PASS DATA M32020 COPY LOLIM0,X INITIALIZE MEMORY ADDRESS COPY =0,Q COPY Q,COUNT03 INITIALIZE LOOP COUNT M32030  COPY COUNT03,Q GET LOOP COUNT XNX Q USE AS INDEX INTO TABLE COPY INDTB0,Q GET INDEX VALUE FROM TABLE ADD INDXP0,Q ADD PASS INDEX ADD INDXV0,Q ADD VENDOR INDEX ADD  DATTBPT0,Q ADD BASE ADDRESS OF DATA TABLE COPY Q,POINT01 STORE SUB-TABLE ADDRESS COPY =:FFF8,Q  COPY Q,COUNT04 INITIALIZE LOOP COUNT M32040 COPY POINT01,Q GET SUB-TABLE ADDRESS COPY Q,POINT02  INITIALIZE TABLE POINTER COPY =:FFF8,Q COPY Q,COUNT05 INITIALIZE LOOP COUNT M32050 COPY =:FF80,Q COPY Q,COUNT06 INITIALIZE LOOP COUNT COPY *POINT02,Q GET DATA FROM TABLE M32060 COPY Q,0(X)  WRITE DATA TO TEST MEMORY ADD =1,X INCREMENT ADDRESS JST ADCHK0 CHECK FOR TRAP LOCATIONS IMS COUNT06 INCREMENT LOOP COUNT JMP M32060 CONTINUE IMS POINT02 INCREMENT DATA TABLE POINTER IMS COUNT05 INCREMENT LOOP COUNT JMP M32050 CONTINUE IMS COUNT04 INCREMENT LOOP COUNT JMP M32040 CONTINUE IMS COUNT03 INCREMENT LOOP COUNT CSK X,L END OF MEMORY ? JMP M32030 NO, CONTINUE JMP M32030 NO, CONTINUE SPACE 11 * * VERIFY DATA RAMS * M32120 COPY LOLIM0,X INITIALIZE MEMORY ADDRESS COPY =0,Q COPY Q,COUNT03 INITIALIZE LOOP COUNT M32130 COPY COUNT03,Q GET LOOP COUNT XNX Q  USE AS INDEX INTO TABLE COPY INDTB0,Q GET INDEX VALUE FROM TABLE ADD INDXP0,Q ADD PASS INDEX ADD INDXV0,Q ADD VENDOR INDEX ADD DATTBPT0,Q ADD BASE ADDRESS OF DATA TABLE COPY Q,POINT01 STORE SUB-TABLE ADDRESS COPY =:FFF8,Q COPY Q,COUNT04 INITIALIZE LOOP COUNT M32140 COPY POINT01,Q GET SUB-TABLE ADDRESS COPY Q,POINT02 INITIALIZE TABLE POINTER COPY =:FFF8,Q COPY Q,COUNT05 INITIALIZE LOOP COUNT M32150 COPY =:FF80,Q COPY Q,COUNT06 INITIALIZE LOOP COUNT COPY *POINT02,Q GET DATA FROM TABLE COPY Q,K STORE AS EXPECTED DATA M32160 COPY 0(X),Q READ DATA FROM TEST MEMORY CSK Q,K COMPARE TO EXPECTED NOP JMP $+2 ERROR  JMP M32163 OK COPY X,Y LOAD Y WITH LOGICAL ADDRESS COPY =0,A LOAD A WITH HIGH ORDER PHYSICAL ADDRESS ERROR: DATA,TEST,ERROR,(DATA,BITS) * Q = ACTUAL DATA *  K = EXPECTED DATA * AX = PHYSICAL ADDRESS * Y = LOGICAL ADDRESS * M32163 ADD =1,X INCREMENT ADDRESS JST ADCHK0 CHECK FOR TRAP LOCATIONS  IMS COUNT06 INCREMENT LOOP COUNT JMP M32160 CONTINUE IMS POINT02 INCREMENT DATA TABLE POINTER IMS COUNT05 INCREMENT LOOP COUNT JMP M32150 CONTINUE IMS COUNT04 INCREMENT LOOP COUNT JMP M32140 CONTINUE IMS COUNT03 INCREMENT LOOP COUNT  CSK X,L END OF MEMORY ? JMP M32130 NO, CONTINUE JMP M32130 NO, CONTINUE   NOP YES, EXIT COPY INDXP0,Q GET PASS INDEX JNE Q,M32170 JUMP IF COMPLETED 2ND PASS COPY =:10,Q INDEX VALUE FOR 2ND PASS DATA COPY Q,INDXP0 STORE 2ND PASS DATA INDEX  JMP M32020 CONTINUE * M32170 EQU $ JST SSCHK0 CHECK SENSE SWITCH AND BLINK DISPLAY  JMP M32010 PATCH FOR LOOPING THROUGH MOSTEK DATA ORG $-1 NOP OVERLAY WITH NOP * COPY INDXV0,Q GET VENDOR INDEX JNE Q,M32180 JUMP IF COMPLETED TI DATA PASSES COPY =:20,Q INDEX VALUE FOR TI DATA COPY Q,INDXV0 STORE TI DATA INDEX JMP M32010 CONTINUE * M32180 EQU $ JMP M32010 PATCH FOR LOOPING THROUGH TI DATA ORG $-1 JMP M32000 PATCH FOR LOOPING THROUGH BOTH VENDORS ORG $-1 NOP OVERLAY WITH NOP JMP  M32200 TITL ******** * * SUBROUTINES AND DATA STORAGE * ******** SPACE 1 * * SUBROUTINE ADCHK0 * * THIS SUBROUTINE DETERMINES WHEN THE MEMORY ADDRESS * REACHES THE UNIMPLEMENTED INSTRUCTION TRAP (:84). *  WHEN THIS OCCURS, IT ADVANCES THE ADDRESS PAST * THE END OF THE MEMORY EXCEPTION TRAP (:8B), AND * ADVANCES THE LOOP COUNT. THE Q REGISTER IS ALTERED. * ADCHK0 ENT CSK X,=:84 REACHED UIT LOCATION ? JMP *ADCHK0 NO, RETURN JMP *ADCHK0 NO, RETURN ADD =8,X ADVANCE ADDRESS PAST TRAP LOCATIONS COPY COUNT06,A GET LOOP COUNT ADD =8,A ADVANCE LOOP COUNT COPY A,COUNT06 UPDATE LOOP COUNT JMP *ADCHK0 RETURN * * SUBROUTINE SSCHK0 * * THIS SUBROUTINE CHECKS FOR A CHANGE IN STATE OF THE * SENSE SWITCH. WHEN THIS OCCURS, IT JUMPS TO AN EXIT * ROUTINE. IT ALSO BLINKS THE PART OF THE CONSOLE * DISPLAY INDICATING THE MEMORY SIZE (BITS 8-14). * THE A AND X REGISTERS ARE ALTERED. * SSCHK0 ENT  COPY =0,Q CLEAR Q JF SS,$+2 -- COPY SENSE SWITCH COPY =1,Q -- TO Q  XOR SENSW0,Q XOR WITH PREVIOUS SENSE SWITCH CONTENTS JNE Q,SSCHK0A JUMP IF SENSE SWITCH CHANGED *  IN 4,Q INPUT CONSOLE DISPLAY COPY MEMSZ0,Y LOAD Y WITH MEMORY SIZE SHIFT Y,L,8  MOVE TO LEFT BYTE XOR Y,Q COMPLEMENT MEMORY SIZE INDICATOR BITS SELP Q,4 OUTPUT TO CONSOLE DISPLAY JMP *SSCHK0 RETURN * SSCHK0A JMP M323JMP EXIT MEMORY TEST * * DATA STORAGE * SENSW0 RES 1,0 SENSE SWITCH STATE AT MEMORY TEST ENTRY MEMSZ0 RES 1,0 MEMORY SIZE IN 64K INCREMENTS LOLIM0 RES 1,0 LOW MEMORY-TESTING LIMIT INDXV0 RES 1,0 VENDOR INDEX INDXP0 RES 1,0  PASS INDEX COUNT03 RES 1,0 LOOP COUNT COUNT04 RES 1,0 LOOP COUNT COUNT05 RES 1,0 LOOP COUNT COUNT06 RES 1,0 LOOP COUNT POINT01 RES 1,0 DATA SUB-TABLE ADDRESS POINT02 RES 1,0   DATA TABLE POINTER DATTBPT0 RES 1,0 DATA TABLE BASE ADDRESS ECCTBPT0 RES 1,0 ECC-TEST DATA TABLE BASE ADDRESS INDTB0 EQU $ TABLE OF INDEX VALUES WORD 0 WORD 8 WORD 8  WORD 0 TITL * * WRITE ECC RAMS * M32200 EQU $ COPY =0,A COPY A,INDXV0 SET VENDOR INDEX FOR MOSTEK DATA M32210 COPY =0,A COPY A,INDXP0 SET PASS INDEX FOR 1ST PASS DATA M32220 COPY LOLIM0,X INITIALIZE MEMORY ADDRESS COPY =0,Q COPY Q,COUNT03 INITIALIZE LOOP COUNT M32230 COPY COUNT03,Q GET LOOP COUNT XNX Q USE AS INDEX INTO TABLE COPY INDTB0,Q GET INDEX VALUE FROM TABLE ADD INDXP0,Q ADD PASS INDEX ADD INDXV0,Q ADD VENDOR INDEX ADD ECCTBPT0,Q ADD BASE ADDRESS OF DATA TABLE COPY Q,POINT01 STORE SUB-TABLE ADDRESS COPY =:FFF8,Q COPY Q,COUNT04 INITIALIZE LOOP COUNT M32240 COPY POINT01,Q GET SUB-TABLE ADDRESS COPY Q,POINT02 INITIALIZE TABLE POINTER COPY =:FFF8,Q COPY Q,COUNT05 INITIALIZE LOOP COUNT M32250 COPY =:FF80,Q  COPY Q,COUNT06 INITIALIZE LOOP COUNT COPY *POINT02,Q GET DATA FROM TABLE M32260 COPY Q,0(X) WRITE DATA TO TEST MEMORY ADD =1,X INCREMENT ADDRESS JST ADCHK0 CHECK FOR TRAP LOCATIONS  IMS COUNT06 INCREMENT LOOP COUNT JMP M32260 CONTINUE IMS POINT02 INCREMENT DATA TABLE POINTER IMS COUNT05 INCREMENT LOOP COUNT JMP M32250 CONTINUE IMS COUNT04 INCREMENT LOOP COUNT JMP M32240 CONTINUE IMS COUNT03 INCREMENT LOOP COUNT  CSK X,L END OF MEMORY ? JMP M32230 NO, CONTINUE JMP M32230 NO, CONTINUE  SPACE 16 * * VERIFY ECC RAMS * M32320 COPY LOLIM0,X INITIALIZE MEMORY ADDRESS COPY =0,Q  COPY Q,COUNT03 INITIALIZE LOOP COUNT M32330 COPY COUNT03,Q GET LOOP COUNT XNX Q USE AS INDEX INTO TABLE COPY INDTB0,Q GET INDEX VALUE FROM TABLE ADD INDXP0,Q ADD PASS INDEX  ADD INDXV0,Q ADD VENDOR INDEX ADD DATTBPT0,Q ADD BASE ADDRESS OF DATA TABLE COPY Q,POINT01  STORE SUB-TABLE ADDRESS COPY =:FFF8,Q COPY Q,COUNT04 INITIALIZE LOOP COUNT M32340 COPY POINT01,Q GET SUB-TABLE ADDRESS COPY Q,POINT02 INITIALIZE TABLE POINTER COPY =:FFF8,Q COPY Q,COUNT05 INITIALIZE LOOP COUNT M32350 COPY =:FF80,Q COPY Q,COUNT06 INITIALIZE LOOP COUNT COPY *POINT02,Q GET DATA FROM TABLE AND =:1F,Q WANT ONLY BITS 0-4 COPY Q,K STORE AS EXPECTED DATA M32360 LODECC . READ ECC WORD FROM TEST MEMORY CSK A,K COMPARE TO EXPECTED NOP  JMP $+2 ERROR JMP M32363 OK COPY X,Y LOAD Y WITH LOGICAL ADDRESS   COPY A,Q LOAD Q WITH ACTUAL DATA COPY =0,A LOAD A WITH HIGH ORDER PHYSICAL ADDRESS  ERROR: DATA,TEST,ERROR,(ECC,BITS) * Q = ACTUAL DATA * K = EXPECTED DATA * AX = PHYSICAL ADDRESS * Y = LOGICAL ADDRESS * M32363 ADD =1,X INCREMENT ADDRESS JST ADCHK0 CHECK FOR TRAP LOCATIONS IMS COUNT06 INCREMENT LOOP COUNT JMP M32360 CONTINUE IMS POINT02 INCREMENT DATA TABLE POINTER IMS  COUNT05 INCREMENT LOOP COUNT JMP M32350 CONTINUE IMS COUNT04 INCREMENT LOOP COUNT  JMP M32340 CONTINUE IMS COUNT03 INCREMENT LOOP COUNT CSK X,L END OF MEMORY ? JMP M32330 NO, CONTINUE JMP M32330 NO, CONTINUE NOP YES, EXIT COPY INDXP0,Q GET PASS INDEX JNE Q,M32370 JUMP IF COMPLETED 2ND PASS COPY =:10,Q INDEX VALUE FOR 2ND PASS DATA COPY Q,INDXP0 STORE 2ND PASS DATA INDEX JMP M32220 CONTINUE * M32370 EQU $ JST SSCHK0 CHECK SENSE SWITCH AND BLINK DISPLAY JMP M32210 PATCH FOR LOOPING THROUGH MOSTEK DATA ORG $-1 NOP OVERLAY WITH NOP * COPY INDXV0,Q  GET VENDOR INDEX JNE Q,M32380 JUMP IF COMPLETED TI DATA PASSES COPY =:20,Q INDEX VALUE FOR TI DATA COPY Q,INDXV0 STORE TI DATA INDEX JMP M32210 CONTINUE * M32380 EQU $  JMP M32210 PATCH FOR LOOPING THROUGH TI DATA ORG $-1 JMP M32200 PATCH FOR LOOPING THROUGH BOTH VENDORS ORG $-1 NOP OVERLAY WITH NOP JMP M32400 * M323JMP JMP SSCHK1A LINKING JUMP TO MEMORY TEST EXIT ROUTINE LPOOL TITL * * FAIRCHILD AND NATIONAL PATTERN TESTING * * WRITE DATA RAMS * M32400 EQU $ COPY =0,A COPY A,INDXV1 SET VENDOR INDEX FOR FAIRCHILD DATA M32410 COPY =0,A COPY A,INDXP1 SET PASS INDEX FOR 1ST PASS DATA M32420 COPY LOLIM1,X INITIALIZE MEMORY ADDRESS COPY =0,Q COPY Q,COUNT13 INITIALIZE LOOP COUNT M32430 COPY COUNT13,Q GET LOOP COUNT TBIT 0,Q COPY Q REG BIT 0 TO OV COPY =0,Q CLEAR Q JF OV,$+2  TEST Q REG BIT 0 COPY =4,Q LOAD Q WITH INDEX IF COUNT13 IS ODD ADD INDXP1,Q ADD PASS INDEX ADD INDXV1,Q ADD VENDOR INDEX ADD DATTBPT1,Q ADD BASE ADDRESS OF DATA TABLE COPY Q,POINT11 STORE SUB-TABLE ADDRESS COPY =:FFE0,Q COPY Q,COUNT14 INITIALIZE LOOP COUNT M32440 COPY POINT11,Q GET SUB-TABLE ADDRESS COPY Q,POINT12 INITIALIZE TABLE POINTER COPY =:FFFC,Q COPY Q,COUNT15 INITIALIZE LOOP COUNT M32450 COPY *POINT12,Q GET DATA FROM TABLE COPY Q,0(X) WRITE   DATA TO MEMORY COPY Q,1(X) WRITE DATA TO MEMORY COPY Q,2(X) WRITE DATA TO MEMORY COPY Q,3(X) WRITE DATA TO MEMORY ADD =4,X INCREMENT ADDRESS JST ADCHK1 CHECK FOR TRAP LOCATIONS IMS POINT12 INCREMENT DATA TABLE POINTER IMS COUNT15 INCREMENT LOOP COUNT  JMP M32450 CONTINUE IMS COUNT14 INCREMENT LOOP COUNT JMP M32440 CONTINUE  IMS COUNT13 INCREMENT LOOP COUNT CSK X,L END OF MEMORY ? JMP M32430 NO, CONTINUE JMP M32430 NO, CONTINUE SPACE 10 * * VERIFY DATA RAMS * M32520 COPY LOLIM1,X  INITIALIZE MEMORY ADDRESS COPY =0,Q COPY Q,COUNT13 INITIALIZE LOOP COUNT M32530 COPY COUNT13,Q GET LOOP COUNT TBIT 0,Q COPY Q REG BIT 0 TO OV COPY =0,Q CLEAR Q JF OV,$+2 TEST Q REG BIT 0 COPY =4,Q LOAD Q WITH INDEX IF COUNT13 IS ODD ADD INDXP1,Q ADD PASS INDEX ADD INDXV1,Q ADD VENDOR INDEX ADD DATTBPT1,Q ADD BASE ADDRESS OF DATA TABLE  COPY Q,POINT11 STORE SUB-TABLE ADDRESS COPY =:FFE0,Q COPY Q,COUNT14 INITIALIZE LOOP COUNT * M32540 COPY POINT11,Q GET SUB-TABLE ADDRESS COPY Q,POINT12 INITIALIZE TABLE POINTER COPY =:FFFC,Q COPY Q,COUNT15 INITIALIZE LOOP COUNT M32550 COPY =:FFFC,Q COPY Q,COUNT16 INITIALIZE LOOP COUNT COPY *POINT12,Q GET DATA FROM TABLE COPY Q,K STORE AS EXPECTED DATA M32560 COPY 0(X),Q READ DATA FROM TEST MEMORY CSK Q,K COMPARE TO EXPECTED NOP JMP $+2  ERROR JMP M32563 OK COPY X,Y LOAD Y WITH LOGICAL ADDRESS COPY =0,A LOAD A WITH HIGH ORDER PHYSICAL ADDRESS ERROR: DATA,TEST,ERROR,(DATA,BITS) * Q = ACTUAL DATA * K = EXPECTED DATA * AX = PHYSICAL ADDRESS *  Y = LOGICAL ADDRESS * M32563 ADD =1,X INCREMENT ADDRESS IMS COUNT16 INCREMENT LOOP COUNT JMP M32560 CONTINUE JST ADCHK1 CHECK FOR TRAP LOCATIONS IMS POINT12  INCREMENT DATA TABLE POINTER IMS COUNT15 INCREMENT LOOP COUNT JMP M32550 CONTINUE  IMS COUNT14 INCREMENT LOOP COUNT JMP M32540 CONTINUE IMS COUNT13 INCREMENT LOOP COUNT CSK X,L END OF MEMORY ? JMP M32530 NO, CONTINUE JMP M32530 NO, CONTINUE NOP YES, EXIT COPY INDXP1,Q GET PASS INDEX JNE Q,M32570 JUMP IF COMPLETED 2ND PASS COPY =8,Q INDEX VALUE FOR 2ND PASS DATA COPY Q,INDXP1 STORE 2ND PASS DATA INDEX JMP M32420 CONTINUE * M32570 EQU $ JST SSCHK1 CHECK SENSE SWITCH AND BL INK DISPLAY JMP M32410 PATCH FOR LOOPING THROUGH FAIRCHILD DATA ORG $-1 NOP  OVERLAY WITH NOP * COPY INDXV1,Q GET VENDOR INDEX JNE Q,M32580 JUMP IF COMPLETED NATIONAL DATA PASSES COPY =:10,Q INDEX VALUE FOR NATIONAL DATA COPY Q,INDXV1 STORE NATIONAL DATA INDEX  JMP M32410 CONTINUE * M32580 EQU $ JMP M32410 PATCH FOR LOOPING THROUGH NATIONAL DATA ORG $-1 JMP M32400 PATCH FOR LOOPING THROUGH BOTH VENDORS ORG $-1 NOP  OVERLAY WITH NOP JMP M32600 TITL ******** * * SUBROUTINES AND DATA STORAGE * ********  SPACE 1 * * SUBROUTINE ADCHK1 * * THIS SUBROUTINE DETERMINES WHEN THE MEMORY ADDRESS * REACHES THE UNIMPLEMENTED INSTRUCTION TRAP (:84). * WHEN THIS OCCURS, IT ADVANCES THE ADDRESS PAST * THE END OF THE MEMORY EXCEPTION TRAP (:8B), AND * ADVANCES THE LOOP COUNT AND DATA TABLE POINTER. * ADCHK1 ENT CSK X,=:84 REACHED UIT LOCATION ? JMP *ADCHK1 NO, RETURN JMP *ADCHK1 NO, RETURN ADD =8,X  ADVANCE ADDRESS PAST TRAP LOCATIONS IMS POINT12 INCREMENT DATA TABLE POINTER IMS POINT12  INCREMENT DATA TABLE POINTER IMS COUNT15 INCREMENT LOOP COUNT IMS COUNT15 INCREMENT LOOP COUNT JMP *ADCHK1 RETURN * * SUBROUTINE SSCHK1 * * (SEE SUBROUTINE SSCHK0) * SSCHK1 ENT  COPY =0,Q CLEAR Q JF SS,$+2 -- COPY SENSE SWITCH COPY =1,Q -- TO Q XOR SENSW1,Q XOR WITH PREVIOUS SENSE SWITCH CONTENTS JNE Q,SSCHK1A JUMP IF SENSE SWITCH CHANGED *  IN 4,Q INPUT CONSOLE DISPLAY COPY MEMSZ1,Y LOAD Y WITH MEMORY SIZE SHIFT Y,L,8  MOVE TO UPPER BYTE XOR Y,Q COMPLEMENT MEMORY SIZE INDICATOR BITS SELP Q,4 OUTPUT TO CONSOLE DISPLAY JMP *SSCHK1 RETURN * SSCHK1A JMP M327JMP EXIT MEMORY TEST * * DATA STORAGE * SENSW1 RES 1,0 SENSE SWITCH STATE AT MEMORY TEST ENTRY MEMSZ1 RES 1,0 MEMORY SIZE IN 64K INCREMENTS LOLIM1 RES 1,0 LOW MEMORY-TESTING LIMIT INDXV1 RES 1,0 VENDOR INDEX INDXP1 RES 1,0  PASS INDEX COUNT13 RES 1,0 LOOP COUNT COUNT14 RES 1,0 LOOP COUNT COUNT15 RES 1,0 LOOP COUNT COUNT16 RES 1,0 LOOP COUNT POINT11 RES 1,0 DATA SUB-TABLE ADDRESS POINT12 RES 1,0  DATA TABLE POINTER DATTBPT1 RES 1,0 DATA TABLE BASE ADDRESS ECCTBPT1 RES 1,0 ECC-TEST DATA TABLE BASE ADDRESS TITL * * WRITE ECC RAMS * M32600 EQU $ COPY =0,A COPY A,INDXV1 SET VENDOR INDEX FOR FAIRCHILD DATA M32610 COPY =0,A COPY A,INDXP1 SET PASS INDEX FOR 1ST PASS DATA M32620 COPY LOLIM1,X INITIALIZE MEMORY ADDRESS COPY =0,Q COPY Q,COUNT13 INITIALIZE LOOP COUNT M32630 CO PY COUNT13,Q GET LOOP COUNT TBIT 0,Q COPY Q REG BIT 0 TO OV COPY =0,Q CLEAR Q  JF OV,$+2 TEST Q REG BIT 0 COPY =4,Q LOAD Q WITH INDEX IF COUNT13 IS ODD ADD INDXP1,Q ADD PASS INDEX ADD INDXV1,Q ADD VENDOR INDEX ADD ECCTBPT1,Q ADD BASE ADDRESS OF DATA TABLE COPY Q,POINT11 STORE SUB-TABLE ADDRESS COPY =:FFE0,Q COPY Q,COUNT14 INITIALIZE LOOP COUNT M32640 COPY POINT11,Q GET SUB-TABLE ADDRESS COPY Q,POINT12 INITIALIZE TABLE POINTER COPY =:FFFC,Q COPY Q,COUNT15 INITIALIZE LOOP COUNT M32650 COPY *POINT12,Q GET DATA FROM TABLE COPY Q,0(X) WRITE DATA TO MEMORY COPY Q,1(X) WRITE DATA TO MEMORY COPY Q,2(X) WRITE DATA TO MEMORY COPY Q,3(X) WRITE DATA TO MEMORY ADD =4,X INCREMENT ADDRESS JST ADCHK1 CHECK FOR TRAP LOCATIONS IMS POINT12 INCREMENT DATA TABLE POINTER IMS COUNT15 INCREMENT LOOP COUNT JMP M32650 CONTINUE IMS COUNT14 INCREMENT LOOP COUNT JMP M32640 CONTINUE IMS COUNT13 INCREMENT LOOP COUNT CSK X,L END OF MEMORY ? JMP M32630 NO, CONTINUE JMP M32630 NO, CONTINUE SPACE 12 * * VERIFY ECC RAMS * M32720 COPY LOLIM1,X INITIALIZE MEMORY ADDRESS COPY =0,Q COPY Q,COUNT13 INITIALIZE LOOP COUNT M32730 COPY COUNT13,Q GET LOOP COUNT TBIT 0,Q COPY Q REG BIT 0 TO OV COPY =0,Q CLEAR Q JF OV,$+2 TEST Q REG BIT 0 COPY =4,Q LOAD Q WITH INDEX IF COUNT13 IS ODD ADD INDXP1,Q ADD PASS INDEX ADD INDXV1,Q ADD VENDOR INDEX ADD DATTBPT1,Q ADD BASE ADDRESS OF DATA TABLE COPY Q,POINT11 STORE SUB-TABLE ADDRESS COPY =:FFE0,Q COPY Q,COUNT14 INITIALIZE LOOP COUNT * M32740 COPY POINT11,Q GET SUB-TABLE ADDRESS COPY Q,POINT12 INITIALIZE TABLE POINTER  COPY =:FFFC,Q COPY Q,COUNT15 INITIALIZE LOOP COUNT M32750 COPY =:FFFC,Q COPY Q,COUNT16  INITIALIZE LOOP COUNT COPY *POINT12,Q GET DATA FROM TABLE AND =:1F,Q WANT ONLY BITS 0-4  COPY Q,K STORE AS EXPECTED DATA M32760 LODECC . READ ECC WORD FROM TEST MEMORY CSK A,K COMPARE TO EXPECTED NOP JMP $+2 ERROR JMP M32763 OK COPY X,Y LOAD Y WITH LOGICAL ADDRESS COPY A,Q LOAD Q WITH ACTUAL DATA COPY =0,A  LOAD A WITH HIGH ORDER PHYSICAL ADDRESS ERROR: DATA,TEST,ERROR,(ECC,BITS) * Q = ACTUAL DATA * K = EXPECTED DATA * AX = PHYSICAL ADDRESS *  Y = LOGICAL ADDRESS * M32763 ADD =1,X INCREMENT ADDRESS IMS COUNT16 INCREMENT LOO P COUNT JMP M32760 CONTINUE JST ADCHK1 CHECK FOR TRAP LOCATIONS IMS POINT12  INCREMENT DATA TABLE POINTER IMS COUNT15 INCREMENT LOOP COUNT JMP M32750 CONTINUE  IMS COUNT14 INCREMENT LOOP COUNT JMP M32740 CONTINUE IMS COUNT13 INCREMENT LOOP COUNT CSK X,L END OF MEMORY ? JMP M32730 NO, CONTINUE JMP M32730 NO, CONTINUE NOP YES, EXIT COPY INDXP1,Q GET PASS INDEX JNE Q,M32770 JUMP IF COMPLETED 2ND PASS COPY =8,Q INDEX VALUE FOR 2ND PASS DATA COPY Q,INDXP1 STORE 2ND PASS DATA INDEX JMP M32620 CONTINUE * M32770 EQU $ JST SSCHK1 CHECK SENSE SWITCH AND BLINK DISPLAY JMP M32610 PATCH FOR LOOPING THROUGH FAIRCHILD DATA ORG $-1 NOP  OVERLAY WITH NOP * COPY INDXV1,Q GET VENDOR INDEX JNE Q,M32780 JUMP IF COMPLETED NATIONAL DATA PASSES COPY =:10,Q INDEX VALUE FOR NATIONAL DATA COPY Q,INDXV1 STORE NATIONAL DATA INDEX  JMP M32610 CONTINUE * M32780 EQU $ JMP M32610 PATCH FOR LOOPING THROUGH NATIONAL DATA ORG $-1 JMP M32600 PATCH FOR LOOPING THROUGH BOTH VENDORS ORG $-1 NOP  OVERLAY WITH NOP JMP M33000 * M327JMP JMP M330JMP LINKING JUMP TO MEMORY TEST EXIT ROUTINE  LPOOL TITL BYTE TEST -- FIRST 64K TESTING (TEST A) ******** * * M33000 * * BYTE TEST * * THIS TEST WRITES MEMORY WITH DATA PATTERNS IN BYTE * MODE, ALTERNATING UPPER BYTE FIRST AND LOWER BYTE * FIRST, WORD BY WORD. IT THEN VERIFIES THE MEMORY * WRITTEN, READING IN BYTE MODE. * ******** * * WRITE MEMORY * M33000 EQU $ COPY LOLIM2,Y INITIALIZE MEMORY ADDRESS COPY =:55,A LOAD A WITH UPPER BYTE DATA  COPY =:AA,Q LOAD Q WITH LOWER BYTE DATA SBIT 2,S SET BYTE MODE M33010 COPY A,0(Y) WRITE DATA TO TEST MEMORY (UPPER BYTE) COPY Q,1(Y) WRITE DATA TO TEST MEMORY (LOWER BYTE) COPY Q,3(Y)  WRITE DATA TO TEST MEMORY (LOWER BYTE) COPY A,2(Y) WRITE DATA TO TEST MEMORY (UPPER BYTE) ADD  =2,Y INCREMENT ADDRESS * CSK Y,=:84 REACHED TRAP VECTOR LOCATIONS ? JMP $+3  NO JMP $+2 NO ADD =8,Y YES, MOVE ADDRESS PAST TRAP LOCATIONS CSK Y,L  END OF MEMORY ? JMP M33010 NO, CONTINUE JMP M33010 NO, CONTINUE RBIT 2,S SET WORD MODE TITL * * VERIFY MEMORY * COPY =0,A LOAD A WITH HIGH ORDER PHYSICAL ADDRESS COPY LOLIM2,Y INITIALIZE MEMORY ADDRESS SBIT 2,S SET BYTE MODE * M33020 COPY =:55,Q UPPER BYTE EXPECTED DATA COPY Q,K LOAD K WITH EXPECTED DATA COPY 0(Y),Q READ  DATA FROM TEST MEMORY (UPPER BYTE) CSK Q,K COMPARE TO EXPECTED NOP JMP $+2 ERROR JMP M33030 OK COPY Y,X LOAD X WITH LOW ORDER PHYSICAL ADDRESS RBIT 2,S  SET WORD MODE ERROR: BYTE,TEST,FAILURE,--,UPPER,BYTE * Q = EXPECTED DATA *  K = EXPECTED DATA * AX = PHYSICAL ADDRESS *  Y = LOGICAL ADDRESS * SBIT 2,S SET BYTE MODE * M33030 COPY =:AA,Q LOWER BYTE EXPECTED DATA  COPY Q,K LOAD K WITH EXPECTED DATA COPY 1(Y),Q READ DATA FROM TEST MEMORY (LOWER BYTE)  CSK Q,K COMPARE TO EXPECTED NOP JMP $+2 ERROR JMP M33040 OK COPY Y,X LOAD X WITH LOW ORDER PHYSICAL ADDRESS RBIT 2,S SET WORD MODE ERROR: BYTE,TEST,FAILURE,--,LOWER,BYTE * Q = EXPECTED DATA * K = EXPECTED DATA * AX = PHYSICAL ADDRESS * Y = LOGICAL ADDRESS * SBIT 2,S SET BYTE MODE * M33040 ADD =1,Y INCREMENT ADDRESS * CSK Y,=:84 REACHED TRAP VECTOR LOCATIONS ? JMP $+3 NO JMP $+2 NO ADD =8,Y YES, MOVE ADDRESS PAST TRAP LOCATIONS CSK Y,L END OF MEMORY ? JMP M33020 NO, CONTINUE JMP  M33020 NO, CONTINUE RBIT 2,S SET WORD MODE * JST SSCHK2 CHECK SENSE SWITCH AND BLINK DISPLAY JMP M33000 PATCH FOR LOOPING THROUGH BYTE TEST ORG $-1 NOP  OVERLAY WITH NOP JMP M34000 * M330JMP JMP M34300 LINKING JUMP TO MEMORY TEST EXIT ROUTINE LPOOL TITL RELOCATION ROUTINES -- FIRST 64K TESTING (TEST A) ******** * * RELOCATION ROUTINES * ******** M34000  EQU $ COPY LOLIM2,A LOAD A WITH LOW MEMORY-TESTING LIMIT JNE A,$+2 JUMP IF PAT NOT RELOCATED JMP M34200 PAT RELOCATED -- RESTORE TO LOW MEMORY COPY DMAND2,A GET PAT MODE SELECT WORD 2 AND =1,A TEST BIT 0 JEQ A,$+2 BIT IS RESET -- RELOCATE PAT JMP M35000  BIT IS SET -- DO NOT RELOCATE PAT -- EXIT SPACE 2 * * SET UP ADDRESS FOR RELOCATED TESTING * COPY =0,A COPY A,LOLIMX -- COPY A,LOLIM0 -- SET LOW MEMORY- COPY A,LOLIM1 -- TESTING LIMIT COPY A,LOLIM2 -- COPY =:7FFF,A COPY A,HILIMX SET HIGH MEMORY-TESTING LIMIT * COPY DATTBAD0,A -- COPY A,DATTBPT0 -- COPY ECCTBAD0,A -- SET UP COPY A,ECCTBPT0 -- DATA TABLE COPY DATTBAD1,A -- POINTERS COPY A,DATTBPT1 -- COPY ECCTBAD1,A  -- COPY A,ECCTBPT1 -- * TITL * * RELOCATE PAT TO HIGH MEMORY * M34100 COPY =0,X INIT IALIZE SOURCE ADDRESS COPY =:8000,Y INITIALIZE DESTINATION ADDRESS COPY Y,L SET SOURCE ADDRESS LIMIT M34110 COPY 0(X),A READ FROM SOURCE AREA COPY A,0(Y) WRITE TO DESTINATION AREA ADD =1,X INCREMENT SOURCE ADDRESS ADD =1,Y INCREMENT DESTINATION ADDRESS CSK X,L  SOURCE ADDRESS AT LIMIT ? JMP M34110 NO, CONTINUE JMP M34110 NO, CONTINUE * VERIFY M34120 COPY =0,X INITIALIZE SOURCE ADDRESS COPY =:8000,Y INITIALIZE DESTINATION ADDRESS M34130 COPY 0(X),A READ FROM SOURCE AREA COPY A,K SAVE IN K COPY 0(Y),Q READ FROM DESTINATION AREA CSK Q,K COMPARE SOURCE DATA WITH DESTINATION DATA NOP JMP M34140  ERROR ADD =1,X DATA OK -- INDREMENT SOURCE ADDRESS ADD =1,Y INCREMENT DESTINATION ADDRESS CSK X,L SOURCE ADDRESS AT LIMIT ? JMP M34130 NO, CONTINUE JMP M34130 NO, CONTINUE JMP M34150 YES, EXIT * M34140 HLT PROGRAM COPY VERIFY ERROR *  K = SOURCE DATA * Q = DESTINATION DATA * X = SOURCE ADDRESS * Y = DESTINATION ADDRESS * JMP M34100 RESTART PROGRAM COPY  TITL * * PREPARE TO JUMP TO RELOCATED PROGRAM * M34150 EQU $ COPY =:84,X UNIMPLELEMTED INSTRUCTION TRAP LOCATION COPY UIT2PT,A UIT SERVICE ROUTINE ADDRESS COPY A,3(X) STORE AT UIT LOCATION (:87) COPY =:BF80,A 'JST *$+1' INSTRUCTION COPY A,6(X) STORE AT MEMORY EXCEPTION TRAP LOC. (:8A) COPY MET2PT,A MET SERVICE ROUTINE ADDRESS COPY A,7(X) STORE AT MET LOCATION (8B) *  COPY MEMSIZ,A MEMORY SIZE IN 64K INCREMENTS SHIFT A,L,8 MOVE TO UPPER BYTE OR =:A,A  OR IN MEMORY TEST CODE SBIT 15,A SET PAT RELOCATION INDICATOR SELP A,4 OUTPUT OT CONSOLE DISPLAY RBIT 8,S DISABLE INTERREUPTS JMP *$+1 JUMP INTO RELOCATED PAT  WORD M31000+:8000 TITL * * DATA STORAGE AND POINTERS * SENSW2 RES 1,0 SENSE SWITCH STATE AT MEMORY TEST ENTRY MEMSZ2 RES 1,0 MEMORY SIZE IN 64K INCREMENTS LOLIM2 RES 1,0 LOW MEMORY-TESTING LIMIT UIT2PT WORD UIT2+:8000 ADDRESS OF RELOCATED UIT SERVICE ROUTINE MET2PT WORD MET2+:8000 ADDRESS OF RELOCATED MET SERVICE ROUTINE DATTBAD0 WORD DATTB0+:8000 ADDRESS OF RELOCATED DATA TABLE 0 ECCTBAD0 WORD ECCTB0+:8000  ADDRESS OF RELOCATED ECC-TEST DATA TABLE 0 DATTBAD1 WORD DATTB1+:8000 ADDRESS OF RELOCATED DATA TABLE 1 ECCTBAD1 WORD ECCTB1+:8000 ADDRESS OF RELOCATED ECC-TEST DATA TABLE 1 * LPOOL TITL * * LOCATE PAT BACK TO LOW MEMORY * M34200 JST RESTOR MOVE PAT BACK TO LOW MEMORY IN 4,A INPUT CONSOLE DISPLAY   RBIT 15,A RESET PAT RELOCATION INDICATOR SELP A,4 OUTPUT TO CONSOLE DISPLAY SIN 1 INHIBIT INTERRUPTS SBIT 8,S ENABLE INTERRUPTS JMP *$+1 -- JUMP BACK TO PAT IN LOW MEMORY AND WORD M35000 -- EXIT 1ST 64K TEST * * ORDERLY EXIT FROM MIDDLE OF MEMORY TEST * M34300 COPY LOLIM2,A GET LOW MEMORY-TESTING LIMIT JNE A,M34310 JUMP IF PROGRAM NOT RELOCATED JST  RESTOR PROGRAM RELOCATED -- RESTORE TO LOW MEMORY SIN 1 INHIBIT INTERRUPTS SBIT 8,S ENABLE INTERRUPTS M34310 JMP *$+1 EXIT MEMORY TEST (JUMP BACK TO LOW MEMORY) WORD M90000 * * CHECK SENSE SWITCH AND BLINK DISPLAY (SEE SSCHK0) * SSCHK2 ENT COPY =0,Q CLEAR Q JF SS,$+2 -- COPY SENSE SWITCH COPY =1,Q -- TO Q XOR SENSW2,Q XOR WITH PREVIOUS SENSE SWITCH CONTENTS JNE Q,M34300 JUMP IF SENSE SWITCH CHANGED IN 4,Q INPUT CONSOLE DISPLAY  COPY MEMSZ2,Y LOAD Y WITH MEMORY SIZE SHIFT Y,L,8 MOVE TO UPPER BYTE XOR Y,Q  COMPLEMENT MEMORY SIZE INDICATOR BITS SELP Q,4 OUTPUT TO CONSOLE DISPLAY JMP *SSCHK2 RETURN TITL * * ROUTINE TO MOVE PAT FROM HIGH MEMORY BACK TO LOW MEMORY * RESTOR ENT COPY =:8000,X  INITIALIZE SOURCE ADDRESS COPY =0,Y INITIALIZE DESTINATION ADDRESS COPY Y,L SET SOURCE ADDRESS LIMIT RESTOR1 COPY 0(X),A READ FROM SOURCE AREA COPY A,0(Y) WRITE TO DESTINATION AREA  ADD =1,X INCREMENT SOURCE ADDRESS ADD =1,Y INCREMENT DESTINATION ADDRESS CSK X,L SOURCE ADDRESS AT LIMIT ? JMP RESTOR1 NO, CONTINUE JMP RESTOR1 NO, CONTINUE *  VERIFY COPY =:8000,X INITIALIZE SOURCE ADDRESS COPY =0,Y INITIALIZE DESTINATION ADDRESS RESTOR2 COPY 0(X),A READ FROM SOURCE AREA COPY A,K SAVE IN K COPY 0(Y),Q READ FROM DESTINATION AREA CSK Q,K COMPARE SOURCE DATA WITH DESTINATION DATA NOP JMP RESTOR3 ERROR ADD =1,X DATA OK -- INCREMENT SOURCE ADDRESS ADD =1,Y INCREMENT DESTINATION ADDRESS CSK X,L SOURCE ADDRESS AT LIMIT ? JMP RESTOR2 NO, CONTINUE JMP  RESTOR2 NO, CONTINUE JMP *RESTOR YES, RETURN * RESTOR3 HLT PROGRAM COPY VERIFY ERROR *  K = SOURCE DATA * Q = DESTINATION DATA * X = SOURCE ADDRESS * Y = DESTINATION ADDRESS JMP RESTOR+1 RESTART PROGRAM COPY TITL * * UNEXPECTED UNIMPLEMENTED INSTRUCTION TRAP SERVICE ROUTINE * UIT2 EQU $ JST LIGHT2 HLT UNEXPECTED UIT JMP MET3 * * UNEXPECTED MEMORY EXCEPTION TRAP * MET2 ENT JST   LIGHT2 SST 2 JMP $+3 HLT UNEXPECTED TRANSLATE TABLE PARITY ERROR JMP MET3 SST 3 JMP $+3 HLT UNEXPECTED UNINSTALLED MEMORY TRAP JMP MET3 SST 4 JMP $+3 HLT UNEXPECTTED ACCESS ERROR JMP MET3 HLT UNDEFINED MEMORY EXCEPTION TRAP MET3 JST RESTOR RESTORE PAT TO LOW MEMORY JMP *$+1 RESTART MEMORY TEST WORD M00100 * LIGHT2 ENT ROUTINE TO INSERT :AAXX IN CONSOLE DISPLAY IN 4,A INPUT CONSOLE DISPLAY AND =:00FF,A MASK OFF UPPER BYTE OR DTAA00,A  INSERT :AA INTO UPPER BYTE SELP A,4 OUTPUT TO CONSOLE DISPLAY JMP *LIGHT2 RETURN DTAA00 WORD :AA00 TITL * * CACHE TEST * * THIS TEST VERIFFIES PROPER OPERATION OF THE CACHE HIT/MISS LOGIC. * IT DOES THIS BY RUNNING SHORT LOOPS WHICH ARE DESIGNED TO * PREDUCE EITHER HITS OR MISSES. THE LOOPS ARE RUN TWICE FOR DIFFERENT * PERIOD OF TIME (CONTROLLED BY THE REAL TIME CLOCK) AND RATIO OF * LOOP COUNTERS IS COMPARED TO LIMITS TO VERIFY EITHER HIT OR * MISSES. THE HIT LIMITS ARE HIGHER THAN THE MISS LIMITS A HIT * IS GENERALLY EXPECTED IF A MEMORY REFERENCE ADDRESS DOES * NOT CROSS A FOUR WORD BOUNDRY FROM THE LAST MEMORY NREFERENCE * (IF ADDRESS BITS 2-16 DO NOT CHANGE). A MISS IS EXPECTED IF * A FOUR WORD BOUNDRY IS CROSSED (IF ANY OF ADDRESS BITS 2-16 * CHANGE). * * HIT TEST * * THE CACHE IS VERIFIED TO PRODUCE HITS WITH EACH ONE OF ADDRESS * BITS 2-15 (NOT 16) CONSTANT AS BOTH 0 AND 1. THE TEST IS * RUN WITH ONLY ONE OF THESE ADDRESS BIT IN THE ZERO STATE AT * A TIME IN A FIELD OF ONES. * THE HIT TEST VERIFIES THE PRESENT/PREVIOUS ADDRESS COMPARISON * GATES IN 2 OF THEIR 4 POSSIBLE STATES (0-0,1-1). * * MISS TEST * * THE CACHE IS VERIFIED TO PRODUCE MISSES WITH EACH ONE OF ADDRESS * BITS 2-15 (NOT 16) CHANGING FROM 1 TO 0 AND FROM 0 TO 1. THE * TEST IS RUN WITH ONLY ONE OF THESE ADDRESS BITS CHANGING * AT A TIME, IN A FIELD OF ONES. * THE MISS TEST VERIFIES THE ADDRESS COMPARISON GATES * IN THEIR OTHER TWO STATES (0-1,1-0). *  SPACE 3 * * CACHE HIT TEST * M35000 EQU $ COPY =0,A INITIALIZE HIGH ORDER PHYSICAL ADDRESS RBIT 8,S DISABLE INTERRUPTS SBIT 5,S ENABLE RTC COPY =:0004,Q INITIALIZE ADDRESS BIT MASK M35010 COPY Q,K STORE CURRENT ADDRESS BIT MASK XOR =:FFFC,Q FORM CURRENT ADDRESS COPY Q,X INITIALIZE CURRENT ADDRESS 1 COPY INSTR1,Q -- COPY Q,0(X)  -- COPY INSTR2,Q -- COPY Q,1(X) -- SET UP TEST LOOP COPY INSTR3,Q -- IN MEMORY COPY Q,2(X) -- COPY INSTR4,Q -- COPY Q,3(X) -- COPY =:FFFE,Q  MINUS 2 COUNT COPY Q,RTCTIM INITIALIZE RTC INCREMENT LOCATION COPY =M35020,Q RTC INTERRUPT S ERVICE ROUTINE LOC. COPY Q,RTCPTR STORE AT RTC INTERRUPT LOCATION SBIT 8,S START RTC  JMP $ WAIT FOR RTC INTERRUPT * M35020 ENT RTC INTERRUPT SERVICE ROUTINE COPY =:FFFE,Q MINUS 2 COUNT COPY Q,RTCTIM INITIALIZE RTC INCREMENT LOCATION COPY =M35030,Q RTC INTERRUPT SERVICE ROUTINE LOC. COPY Q,RTCPTR STORE AT RTC INTERRUPT LOCATION COPY X,Y ADD =2,Y INITIALIZE CURRENT ADDRESS 2 COPY =0,Q INITIALIZE TIMING LOOP COUNTER SBIT 8,S  START RTC JMP 0(X) JUMP INTO TIMING LOOP TITL M35030 ENT RTC INTERRUPT SERVICE ROUTINE COPY Q,HITCNT1 SAVE NO. OF HITS COPY =:FFFC,Q SET -4 COUNTS COPY Q,RTCTIM INIT RTC INCREMENT CELL COPY =M35040,Q RTC SERVICE ROUTINE ADDRESS COPY Q,RTCPTR STORE IN RTC INT. ADDRESS COPY =0,Q RESET HIT COUNTS SBIT 8,S ENABLE INTERRUPT JMP 0(X) JUMP INTO TIMMING LOOP * M35040 ENT COPY Q,HITCNT2 SAVE NO. OF HITS COPY =0,A COPY =100,Q MUL HITCNT1,AQ MULT 1ST NO. OF HITS BY 100 DIV HITCNT2,AQ DIVIDE BY SECOND NO. OF HITS CSME Q,LIM1 COMPARE TIMING COUNT TO HIGH LIMIT  JMP $+3 OK NOP ERROR ERROR: CACHE,TEST,FAILURE * WITH MMU CACHE SWITCH FORCED ON TIMING LOOP COUNT OUT OF LIMIT * TIMING LOOP COUNT ABOVE LIMIT *  LOOP EXECUTED FASTER THAN EXPECTED * Q = TIMING LOOP COUNT * CSME  Q,LIM2 COMPARE TIMING COUNT TO LOW LIMIT ERROR: CACHE,TEST,FAILURE *  TIMING LOOP COUNT BELOW LIMIT * POSSIBLE ERRONEOUS CACHE MISSES * Q = TIMING LOOP COUNT * NOP COPY K,Q LOAD Q WITH CURRENT ADDRESS BIT MASK TBIT 15,Q  COPY BIT 15 TO OV JT OV,M35100 JUMP IF REACHED BIT 15 SHIFT Q,L,1 SHIFT ADDRESS BIT MASK TO NEXT BIT JMP M35010 CONTINUE LPOOL * INST1 NOP -- INST2 JMP 0(Y) -- CACHE TEST LOOP INST3 ADD =1,Q -- INSTRUCTIONS INST4 JMP 0(X) -- * LIM1 WORD :0035 53% HIGH LIMIT LIM2 WORD :002F 47% LOW LIMIT LIM3 WORD :0057 87% HIGH LIMIT LIM4 WORD :004F 79% LOW LIMIT TITL * * CACHE MISS TEST * M35100 EQU $ COPY =:FFFC,Y INITIALIZE PHYSICAL ADDRESS 2 COPY INST3,Q -- COPY Q,0(Y) -- SET UP 2ND HALF COPY INST4,Q -- TEST LOOP IN MEMORY COPY Q,1(Y) -- COPY =:0004,Q INITIALIZE ADDRESS BIT MASK * M35110 COPY Q,K STORE CURRENT ADDRESS BIT MASK XOR =:FFFC,Q FORM CURRENT ADDRESS COPY Q,X INITIALIZE PHYSICAL ADDRESS 1  COPY INST1,Q -- COPY Q,0(X) -- SET UP 1ST HALF COPY INST2,Q -- TEST LOOP IN MEMORY COPY Q,1(X) -- * COPY =:FFFE,Q MINUS 2 COUNT COPY Q,RTCTIM INITIALIZE RTC  INCREMENT LOCATION COPY =M35120,Q RTC INTERRUPT SERVICE ROUTINE LOC. COPY Q,RTCPTR STORE AT RTC INTERRUPT LOCATION SBIT 8,S START RTC JMP $ WAIT FOR INTERRUPT * M35120 ENT  RTC INTERRUPT SERVICE ROUTINE COPY =:FFFE,Q MINUS 2 COUNT COPY Q,RTCTIM INITIALIZE RTC INCREMENT LOCATION COPY =M35130,Q RTC INTERRUPT SERVICE ROUTINE LOC. COPY Q,RTCPTR STORE AT RTC INTERRUPT LOCATION COPY =0,Q INITIALIZE TIMING LOOP COUNTER SBIT 8,S START RTC  JMP 0(X) JUMP INTO TIMING LOOP TITL M35130 ENT RTC INTERRUPT SERVICE ROUTINE COPY Q,MISCNT1 SAVE NO. OF MISSES COPY =:FFFC,Q MINUS 4 COUNT COPY Q,RTCTIM INIT RTC INCREMENT CELL COPY =M35140,Q RTC INT. SERVICE ADDRESS COPY Q,RTCPTR STORE AT RTC INT. LOCATION COPY =0,Q RESET MISS COUNT SBIT 8,S ENABLE INTERRUPT JMP 0(X) JUMP INTO TIMMING LOOP * M35140 ENT COPY Q,MISCNT2 SAVE NO. OF MISSES COPY =0,A COPY =100,Q MUL MISCNT1,AQ MULT 1ST SET OF MISSES BY 100 DIV MISCNT2,AQ DIVIDE BY 2ND SET OF MISSES CSME Q,LIM1 COMPARE TIMING COUNT TO HIGH LIMIT JMP $+3  OK NOP ERROR ERROR: CACHE,MISS,TEST,FAILURE * WITH MMU CACHE SWITCH FORCED ON TIMING LOOP OUT OF LIMIT * TIMING LOOP COUNT ABOVE LIMIT *  POSSIBLE ERRONEOUS CACHE HITS * Q = TIMING LOOP COUNT * CSME Q,LIM2 COMPARE TIMING COUNT TO LOW LIMIT ERROR: CASHE,MISS,TEST,FAILURE * TIMING LOOP COUNT BELOW LIMIT * LOOP EXECUTED SLOWER THAN EXPECTED * Q = TIMING LOOP COUNT * NOP COPY K,Q LOAD Q WITH ADDRESS BIT MASK TBIT 15,Q COPY BIT 15 TO OV JT OV,M35150 JUMP IF REACHED BIT 15 SHIFT Q,L,1 SHIFT ADDRESS BIT MASK TO NEXT BIT  JMP M35110 CONTINUE M35150 EQU $ COPY =0,A COPY =100,Q MUL MISCNT2,AQ DIV HITCNT2,AQ CALCULATE MISS/HIT RATIO CSME Q,LIM3 COMPARE MISS/HIT AGAINST HIGH LIMIT JMP $+3 HLT MICRO CACHE FAILED -- MAKE SURE MMU CACHE SW. *  IS NOT FORCED ON. NOP CSME Q,LIM4 COMPARE MISS/HIT AGAINST LOW LIMIT HLT MICRO CAHCE FAILED -- MAKE SURE MMU CACHE SW. * IS NOT FORCED ON NOP * M35200 EQU $ JMP M35000 PATCH FOR LOOPING  ORG $-1 NOP OVERLAY WITH NOP JMP M30000 ORG $-1 NOP  OVERLAY WITH NOP JMP M4000A LPOOL TITL TEST DATA TABLES (TEST A) * * MOSTEK DATA RAM TEST DATA * * PASS 1 * DATTB0 EQU $ WORD :AAAA WORD :5555 WORD :5555 WORD :AAAA WORD :5555 WORD :AAAA WORD :AAAA WORD :5555 * WORD :5555  WORD :AAAA WORD :AAAA WORD :5555 WORD :AAAA WORD :5555 WORD :5555   WORD :AAAA TITL * * PASS 2 * WORD :5555 WORD :AAAA WORD :AAAA  WORD :5555 WORD :AAAA WORD :5555 WORD :5555 WORD :AAAA * WORD :AAAA  WORD :5555 WORD :5555 WORD :AAAA WORD :5555 WORD :AAAA WORD :AAAA WORD :5555 TITL * * TEXAS INSTRUMENTS DATA RAM TEST DATA * * PASS 1 * WORD :AAAA WORD :AAAA WORD :5555 WORD :5555 WORD :5555 WORD :5555 WORD :AAAA WORD :AAAA * WORD :5555 WORD :5555 WORD :AAAA WORD :AAAA WORD :AAAA WORD :AAAA WORD :5555 WORD :5555 TITL * * PASS 2 * WORD :5555 WORD :5555 WORD :AAAA WORD :AAAA WORD :AAAA WORD :AAAA WORD :5555 WORD :5555 * WORD :AAAA WORD :AAAA WORD :5555 WORD :5555  WORD :5555 WORD :5555 WORD :AAAA WORD :AAAA TITL * * MOSTEK ECC RAM TEST DATA * * PASS 1 * ECCTB0 EQU $ WORD :2000 WORD :0020 WORD :0020 WORD :2000 WORD :0020 WORD :2000 WORD :2000 WORD :0020 * WORD :0020 WORD  :2000 WORD :2000 WORD :0020 WORD :2000 WORD :0020 WORD :0020 WORD :2000 TITL * * PASS 2 * WORD :0020 WORD :2000 WORD :2000 WORD :0020 WORD :2000 WORD :0020 WORD :0020 WORD :2000 * WORD :2000 WORD :0020 WORD :0020 WORD :2000 WORD :0020 WORD :2000 WORD :2000  WORD :0020 TITL * * TEXAS INSTRUMENTS ECC RAM TEST DATA * * PASS 1 * WORD :2000 WORD :2000 WORD :0020 WORD :0020 WORD :0020 WORD :0020 WORD :2000  WORD :2000 * WORD :0020 WORD :0020 WORD :2000 WORD :2000 WORD :2000 WORD :2000 WORD :0020 WORD :0020 TITL * * PASS 2 * WORD :0020  WORD :0020 WORD :2000 WORD :2000 WORD :2000 WORD :2000 WORD :0020  WORD :0020 * WORD :2000 WORD :2000 WORD :0020 WORD :0020 WORD :0020 WORD :0020 WORD :2000 WORD :2000 TITL * * FAIRCHILD DATA RAM TEST DATA * * PASS 1 * DATTB1 EQU $ WORD :AAAA WORD :5555 WORD :5555 WORD :AAAA *  WORD :5555 WORD :AAAA WORD :AAAA WORD :5555 * * PASS 2 * WORD :5555  WORD :AAAA WORD :AAAA WORD :5555 * WORD :AAAA WORD :5555 WORD : 5555 WORD :AAAA TITL * * NATIONAL DATA RAM TEST DATA * * PASS 1 * WORD :AAAA  WORD :AAAA WORD :AAAA WORD :AAAA * WORD :5555 WORD :5555 WORD :5555  WORD :5555 * * PASS 2 * WORD :5555 WORD :5555 WORD :5555 WORD :5555 * WORD :AAAA WORD :AAAA WORD :AAAA WORD :AAAA TITL * * FAIRCHILD ECC RAM TEST DATA * * PASS 1 * ECCTB1 EQU $ WORD :2000 WORD :0020 WORD :0020  WORD :2000 * WORD :0020 WORD :2000 WORD :2000 WORD :0020 * * PASS 2 *  WORD :0020 WORD :2000 WORD :2000 WORD :0020 * WORD :2000 WORD :0020 WORD :0020 WORD :2000 TITL * * NATIONAL ECC RAM TEST DATA * * PASS 1 * WORD :2000 WORD :2000 WORD :2000 WORD :2000 * WORD :0020 WORD :0020  WORD :0020 WORD :0020 * * PASS 2 * WORD :0020 WORD :0020 WORD :0020  WORD :0020 * WORD :2000 WORD :2000 WORD :2000 WORD :2000 TITL ABOVE 1ST 64K TESTING (TEST A) ******** * * M40000 * M50000 * M60000 * M70000 * * ABOVE 1ST 64K TESTING * * THESE SECTIONS TEST ALL MEMORY EXCEPT THE 1ST 64K * IN THE SYSTEM. * * EACH SECTION TESTS MEMORY IN 64K BLOCKS. ACCESS OF * TEST MEMORY IS DONE VIA THE LOGICAL ADDRESS SPACE * :8000-:FFFF USING THE TRANSLATE TABLE IN THE MMU. * TWO MAPS ARE USED AT A TIME. THE UPPER HALVES OF * THE SYSTEM MAP AND USER MAP 1 POINT TO THE FIRST * HALF AND THE SECOND HALF RESPECTIVELY OF THE CURRENT * 64K MEMORY BLOCK UNDER TEST. * * THESE SECTIONS ARE PERFORMED ONLY IF AN MMU AND MORE * THAN 64K OF MEMORY ARE INSTALLED. * ******** M4000A EQU $ COPY MEMSIZ,A GET MEMORY SIZE CSK A,=2 MEMORY > 64K ? JMP INIT20 NO, SKIP ABOVE 64K TESTING NOP YES, CONTINUE COPY =1,A OUT A,6 INITIALIZE USER MAP NUMBER TITL ADDRESS TEST -- ABOVE 1ST 64K (TEST A) ******** * * M40000 * * LOW ORDER UNIQUE ADDRESS TEST * * THIS TEST EXERCISES THE LOWER 16 OF THE 22 MEMORY * ADDRESS BITS AS FOLLOWS: * EVERY WORD IS WRITTEN WITH BITS 0-15 OF ITS ADDRESS * AS DATA, AND THEN VERIFIED. THES IS DONE IN FORWARD * ORDER AND REVERSE ORDER. *  THIS TEST IS PERFORMED ONLY IF AN MMU AND MORE * THAN 64K OF MEMORY ARE INSTALLED. * ******** * * FORWARD ORDER WRITE * M40000 EQU $ JST INIT2 INITIALIZE TRANSLATE TABLE COPY =1,A INITIALIZE HIGH ORDER PHYSICAL ADDRESS * M41000 RBIT 10,S SET STATUS TO SYSTEM MAP COPY A,L SAVE A IN L  COPY =0,Y INITIALIZE LOW ORDER PHYSICAL ADDRESS M41010 COPY =:8000,X INITIALIZE LOGICAL ADDRESS * M41020  COPY Y,0(X) WRITE DATA TO TEST MEMORY GENECC . GENERATE ECC BITS STRECC . WRITE ECC BITS TO TEST MEMORY ADD =1,Y INCREMENT PHYSICAL ADDRESS IJNE X,M41020 INCREMENT LOGICAL ADDR -- JUMP IF NOT DONE JEQ Y,$+3 JUMP IF END OF CURRENT 64K SEGMENT SBIT 10,S SWITCH TO USER MAP JMP M41010 CONTINUE COPY L,A RESTORE A TITL * * FORWARD ORDER VERIFY * M41030 EQU $ RBIT 10,S SET STATUS TO SYSTEM MAP COPY =0,X INITIALIZE LOW ORDER PHYSICAL ADDRESS COPY X,K INITIALIZE EXPECTED DATA M41040 COPY =:8000,Y INITIALIZE LOGICAL ADDRESS * M41050 COPY 0(Y),Q READ DATA FROM TEST MEMORY CSK Q,K COMPARE TO EXPECTED  NOP ERR: LOW,ORDER,ADDRESS,TEST,FAILURE ADD =1,X INCREMENT PHYSICAL ADDRESS COPY X,K MODIFY EXPECTED DATA IJNE Y,M41050 INCREMENT LOGICAL ADDR -- JUMP IF NOT DONE JEQ X,$+3 JUMP IF END OF CURRENT 64K SEGMENT SBIT 10,S SWITCH TO USER MAP JMP M41040 CONTINUE JST SSCHK CHECK SENSE SWITCH AND BLINK DISPLAY TITL * * REVERSE ORDER WRITE * M41100 EQU $ SBIT 10,S SET STATUS TO USER MAP COPY =:FFFF,X INITIALIZE LOW ORDER PHYSICAL ADDRESS M41110 COPY =:FFFF,Y INITIALIZE LOGICAL ADDRESS * M41120 COPY X,0(Y) WRITE DATA TO TEST MEMORY SUB =1,X DECREMENT PHYSICAL ADDRESS SUB =1,Y DECREMENT LOGICAL ADDRESS COPY Y,Q  LOGICAL ADDRESS TO Q CSK Q,=:7FFF END OF LOGICAL ADDRESS SPACE ? NOP JMP M41120  NO, CONTINUE COPY X,Q YES -- PHYSICAL ADDRESS TO Q CSK Q,=:FFFF END OF CURRENT 64K SEGMENT ? NOP JMP $+2 NO JMP M41130 YES RBIT 10,S SWITCH TO SYSTEM MAP JMP M41110 CONTINUE TITL * * REVERSE ORDER VERIFY * M41130 EQU $ SBIT 10,S SET STATUS TO USER MAP COPY =:FFFF,X INITIALIZE LOW ORDER PHYSICAL ADDRESS COPY X,K  INITIALIZE EXPECTED DATA M41140 COPY =:FFFF,Y INITIALIZE LOGICAL ADDRESS * M41150 COPY 0(Y),Q READ DATA FROM TEST MEMORY CSK Q,K COMPARE TO EXPECTED NOP ERR: LOW,ORDER,ADDRESS,TEST,FAILURE SUB =1,X DECREMENT PHYSICAL ADDRESS COPY X,K MODIFY EXPECTED DATA SUB =1,Y DECREMENT LOGICAL ADDRESS COPY Y,Q LOGICAL ADDRESS TO Q CSK Q,=:7FFF END OF LOGICAL ADDRESS SPACE ? NOP NO JMP M41150 NO, CONTINUE COPY X,Q YES -- LOW ORDER PHYSICAL ADDRESS TO Q CSK Q,=:FFFF END OF CURRENT 64K SEGMENT ? NOP NO JMP $+2 NO JMP M41160 YES RBIT 10,S SWITCH TO SYSTEM MAP   JMP M41140 CONTINUE TITL M41160 EQU $ JST SSCHK CHECK SENSE SWITCH AND BLINK DISPLAY JMP M41000 PATCH FOR LOOPING THROUGH 64K ORG $-1 NOP OVERLAY WITH NOP * ADD =1,A INCREMENT HIGH ORDER PHYSICAL ADDRESS CSK A,MEMSIZ END OF PHYSICAL ADDRESS SPACE ? NOP JMP $+2 NO JMP $+3 YES JST INCTB2 MODIFY TRANSLATE TABLE JMP M41000 CONTINUE * JMP M40000 PATCH FOR LOOPING THROUGH ENTIRE MEMORY  ORG $-1 NOP OVERLAY WITH NOP JMP M50000 LPOOL TITL DATA TEST -- ABOVE 1ST 64K TESTING (TEST A) ******** * * M50000 * * DATA TEST -- ABOVE 1ST 64K TESTING * * (SEE DESCRIPTION AT BEGINNING OF SECTION M32000) * ******** M50000 EQU $ JST INIT2 INITIALIZE TRANSLATE TABLE  COPY =1,A INITIALIZE HIGH ORDER PHYSICAL ADDRESS TITL * * MOSTEK AND TI PATTERN TESTING * *  WRITE DATA RAMS * M51000 COPY =0,Q COPY Q,INDXV2 INITIALIZE VENDOR INDEX M51010 COPY =0,Q COPY Q,INDXP2 INITIALIZE PASS INDEX M51020 RBIT 10,S SET STATUS TO SYSTEM MAP COPY =0,X INITIALIZE LOW ORDER PHYSICAL ADDRESS COPY X,COUNT23 INITIALIZE PASS COUNT M5103Y COPY =:8000,Y INITIALIZE LOGICAL ADDRESS M51030 COPY COUNT23,Q GET LOOP COUNT XNX Q USE AS INDEX INTO TABLE COPY INDTB2,Q GET INDEX VALUE FROM TABLE ADD INDXP2,Q ADD PASS INDEX ADD INDXV2,Q ADD VENDOR INDEX ADD =DATTB0,Q ADD BASE ADDRESS OF DATA TABLE COPY Q,POINT21 STORE SUB-TABLE ADDRESS  COPY =:FFF8,Q COPY Q,COUNT24 INITIALIZE LOOP COUNT M51040 COPY POINT21,Q GET SUB-TABLE ADDRESS  COPY Q,POINT22 INITIALIZE TABLE POINTER COPY =:FFF8,Q COPY Q,COUNT25 INITIALIZE LOOP COUNT M51050 COPY =:FF80,Q COPY Q,COUNT26 INITIALIZE LOOP COUNT COPY *POINT22,Q GET DATA FROM TABLE M51060 COPY Q,0(Y) WRITE DATA TO TEST MEMORY ADD =1,X INCREMENT PHYSICAL ADDRESS ADD =1,Y INCREMENT LOGICAL ADDRESS IMS COUNT26 INCREMENT LOOP COUNT JMP M51060 CONTINUE IMS POINT22 INCREMENT DATA TABLE POINTER IMS COUNT25 INCREMENT LOOP COUNT JMP M51050 CONTINUE IMS COUNT24 INCREMENT LOOP COUNT JMP M51040 CONTINUE IMS  COUNT23 INCREMENT LOOP COUNT JNE Y,M51030 END OF LOGICAL ADDRESS SPACE ? JUMP IF NOT JEQ X,M51120 JUMP IF END OF CURRENT 64K SEGMENT SBIT 10,S SWITCH TO USER MODE JMP M5103Y CONTINUE SPACE 10 * * VERIFY DATA RAMS * M51120 RBIT 10,S SET STATUS TO SYSTEM MAP COPY =0,X INITIALIZE LOW ORDER PHYSICAL ADDRESS COPY X,COUNT23 INITIALIZE PASS COUNT M5113Y COPY =:8000,Y   INITIALIZE LOGICAL ADDRESS M51130 COPY COUNT23,Q GET LOOP COUNT XNX Q USE AS INDEX INTO TABLE COPY INDTB2,Q GET INDEX VALUE FROM TABLE ADD INDXP2,Q ADD PASS INDEX ADD INDXV2,Q ADD VENDOR INDEX ADD =DATTB0,Q ADD BASE ADDRESS OF DATA TABLE COPY Q,POINT21 STORE SUB-TABLE ADDRESS COPY =:FFF8,Q COPY Q,COUNT24 INITIALIZE LOOP COUNT SPACE 2 M51140 COPY POINT21,Q GET SUB-TABLE ADDRESS COPY Q,POINT22 INITIALIZE TABLE POINTER COPY =:FFF8,Q COPY Q,COUNT25 INITIALIZE LOOP COUNT M51150 COPY =:FF80,Q COPY Q,COUNT26 INITIALIZE LOOP COUNT COPY *POINT22,Q GET DATA FROM TABLE COPY Q,K STORE AS EXPECTED DATA M51160 COPY 0(Y),Q READ DATA FROM TEST MEMORY CSK Q,K COMPARE TO EXPECTED NOP ERR: DATA,TEST,ERROR ADD =1,X INCREMENT PHYSICAL ADDRESS ADD =1,Y INCREMENT LOGICAL ADDRESS IMS COUNT26 INCREMENT LOOP COUNT JMP M51160 CONTINUE IMS POINT22 INCREMENT DATA TABLE POINTER IMS COUNT25 INCREMENT LOOP COUNT JMP M51150 CONTINUE IMS COUNT24 INCREMENT LOOP COUNT JMP M51140 CONTINUE IMS COUNT23 INCREMENT LOOP COUNT JNE Y,M51130 END OF LOGICAL ADDRESS SPACE ? JUMP IF NOT JEQ X,$+3 JUMP IF END OF CURRENT 64K SEGMENT SBIT 10,S  SWITCH TO USER MODE JMP M5113Y CONTINUE * JST SSCHK CHECK SENSE SWITCH AND BLINK DISPLAY NOP COPY INDXP2,Q GET PASS INDEX JNE Q,M51170 JUMP IF COMPLETED 2ND PASS COPY =:10,Q INDEX VALUE FOR 2ND PASS DATA COPY Q,INDXP2 STORE 2ND PASS DATA INDEX JMP M51020 CONTINUE * M51170 EQU $ JMP M51010 PATCH FOR LOOPING THROUGH MOSTEK DATA ORG $-1  NOP OVERLAY WITH NOP * COPY INDXV2,Q GET VENDOR INDEX JNE Q,M51180 JUMP IF COMPLETED TI DATA PASSES COPY =:20,Q INDEX VALUE FOR TI DATA COPY Q,INDXV2 STORE TI DATA INDEX JMP M51010 CONTINUE * M51180 EQU $ JMP M51010 PATCH FOR LOOPING THROUGH TI DATA  ORG $-1 JMP M51000 PATCH FOR LOOPING THROUGH BOTH VENDORS ORG $-1 NOP  OVERLAY WITH NOP JMP M51200 TITL * * DATA STORAGE * INDXV2 RES 1,0 VENDOR INDEX INDXP2 RES 1,0 PASS INDEX COUNT23 RES 1,0 LOOP COUNT COUNT24 RES 1,0 LOOP COUNT COUNT25 RES 1,0 LOOP COUNT COUNT26 RES 1,0 LOOP COUNT POINT21 RES 1,0 DATA SUB-TABLE ADDRESS POINT22 RES 1,0 DATA TABLE POINTER INDTB2 EQU $ TABLE OF INDEX VALUES WORD 0  WORD 8 WORD 8 WORD 0 WORD 8 WORD 0 WORD 0 WORD 8 *   LPOOL TITL * * WRITE ECC RAMS * M51200 COPY =0,Q COPY Q,INDXV2 INITIALIZE VENDOR INDEX M51210 COPY =0,Q COPY Q,INDXP2 INITIALIZE PASS INDEX M51220 RBIT 10,S SET STATUS TO SYSTEM MAP COPY =0,X INITIALIZE LOW ORDER PHYSICAL ADDRESS COPY X,COUNT23 INITIALIZE PASS COUNT M5123Y COPY =:8000,Y INITIALIZE LOGICAL ADDRESS M51230 COPY COUNT23,Q GET LOOP COUNT XNX Q USE AS INDEX INTO TABLE COPY INDTB2,Q GET INDEX VALUE FROM TABLE ADD INDXP2,Q ADD PASS INDEX  ADD INDXV2,Q ADD VENDOR INDEX ADD =ECCTB0,Q ADD BASE ADDRESS OF DATA TABLE COPY Q,POINT21 STORE SUB-TABLE ADDRESS COPY =:FFF8,Q COPY Q,COUNT24 INITIALIZE LOOP COUNT M51240 COPY POINT21,Q GET SUB-TABLE ADDRESS COPY Q,POINT22 INITIALIZE TABLE POINTER COPY =:FFF8,Q COPY Q,COUNT25 INITIALIZE LOOP COUNT M51250 COPY =:FF80,Q COPY Q,COUNT26 COPY *POINT22,Q GET DATA FROM TABLE M51260 COPY Q,0(Y) WRITE DATA TO TEST MEMORY ADD =1,X INCREMENT PHYSICAL ADDRESS ADD =1,Y INCREMENT LOGICAL ADDRESS IMS COUNT26 INCREMENT LOOP COUNT JMP M51260 CONTINUE IMS POINT22 INCREMENT DATA TABLE POINTER IMS COUNT25 INCREMENT LOOP COUNT JMP M51250 CONTINUE IMS COUNT24 INCREMENT LOOP COUNT JMP M51240 CONTINUE IMS COUNT23 INCREMENT LOOP COUNT JNE Y,M51230 END OF LOGICAL ADDRESS SPACE ? JUMP IF NOT JEQ X,M51320 JUMP IF END OF CURRENT 64K SEGMENT SBIT 10,S SWITCH TO USER MODE JMP M5123Y CONTINUE SPACE 12 * * VERIFY ECC RAMS * M51320 RBIT 10,S SET STATUS TO SYSTEM MAP COPY A,Q LOAD Q WITH HIGH ORDER PHYSICAL ADDRESS COPY =0,Y INITIALIZE LOW ORDER PHYSICAL ADDRESS COPY Y,COUNT23 INITIALIZE PASS COUNT M5133Y COPY =:8000,X INITIALIZE LOGICAL ADDRESS M51330 COPY COUNT23,A  GET LOOP COUNT XNX A USE AS INDEX INTO TABLE COPY INDTB2,A GET INDEX VALUE FROM TABLE  ADD INDXP2,A ADD PASS INDEX ADD INDXV2,A ADD VENDOR INDEX ADD =DATTB0,A ADD BASE ADDRESS OF DATA TABLE COPY A,POINT21 STORE SUB-TABLE ADDRESS COPY =:FFF8,A COPY A,COUNT24 INITIALIZE LOOP COUNT SPACE 1 M51340 COPY POINT21,A GET SUB-TABLE ADDRESS COPY A,POINT22 INITIALIZE TABLE POINTER COPY =:FFF8,A COPY A,COUNT25 INITIALIZE LOOP COUNT M51350 COPY =:FF80,A  COPY A,COUNT26 INITIALIZE LOOP COUNT COPY *POINT22,A GET DATA FROM TABLE AND =:1F,A  WANT ONLY BITS 0-4 COPY A,K STORE AS EXPECTED DATA M51360 LODECC . READ ECC WORD FROM TEST MEMORY CSK A,K COMPARE TO EXPECTED NOP JMP $+2 ERROR JMP M5136 3 OK EXCH A,Q ACTUAL DATA --> Q; HIGH PHYS. ADDR. --> A EXCH X,Y LOGICAL ADDR. --> Y; LOW PHYS. ADDR. --> X ERR: DATA,TEST,ERROR EXCH X,Y LOGICAL ADDR. --> X; LOW PHYS. ADDR. --> Y COPY A,Q HIGH PHYS. ADDR. --> Q M51363 ADD =1,X INCREMENT PHYSICAL ADDRESS ADD =1,Y INCREMENT LOGICAL ADDRESS IMS COUNT26 INCREMENT LOOP COUNT JMP M51360 CONTINUE IMS POINT22 INCREMENT DATA TABLE POINTER IMS COUNT25 INCREMENT LOOP COUNT JMP M51350 CONTINUE IMS COUNT24 INCREMENT LOOP COUNT JMP M51340 CONTINUE IMS COUNT23 INCREMENT LOOP COUNT JNE X,M51330 END OF LOGICAL ADDRESS SPACE ? JUMP IF NOT JEQ  Y,$+3 JUMP IF END OF CURRENT 64K SEGMENT SBIT 10,S SWITCH TO USER MODE JMP M5133Y  CONTINUE * COPY Q,A RESTORE A WITH HIGH ORDER PHYSICAL ADDRESS JST SSCHK CHECK SENSE SWTICH AND BLINK DISPLAY NOP COPY INDXP2,Q GET PASS INDEX JNE Q,M51370 JUMP IF COMPLETED 2ND PASS COPY =:10,Q INDEX VALUE FOR 2ND PASS DATA COPY Q,INDXP2 STORE 2ND PASS DATA INDEX  JMP M51220 CONTINUE * M51370 EQU $ JMP M51210 PATCH FOR LOOPING THROUGH MOSTEK DATA  ORG $-1 NOP OVERLAY WITH NOP * COPY INDXV2,Q GET VENDOR INDEX JNE  Q,M51380 JUMP IF COMPLETED TI DATA PASSES COPY =:20,Q INDEX VALUE FOR TI DATA COPY Q,INDXV2 STORE TI DATA INDEX JMP M51210 CONTINUE * M51380 EQU $ JMP M51210 PATCH FOR LOOPING THROUGH TI DATA ORG $-1 JMP M51200 PATCH FOR LOOPING THROUGH BOTH VENDORS ORG $-1 NOP OVERLAY WITH NOP JMP M51400 LPOOL TITL * * FAIRCHILD AND NATIONAL PATTERN TESTING * * WRITE DATA RAMS * M51400 COPY =0,Q COPY Q,INDXV3 INITIALIZE VENDOR INDEX M51410 COPY =0,Q COPY Q,INDXP3 INITIALIZE PASS INDEX M51420 RBIT 10,S SET STATUS TO SYSTEM MAP  COPY =0,X INITIALIZE LOW ORDER PHYSICAL ADDRESS COPY X,COUNT33 INITIALIZE PASS COUNT M5143Y COPY =:8000,Y INITIALIZE LOGICAL ADDRESS M51430 COPY COUNT33,Q GET LOOP COUNT TBIT 0,Q COPY Q REG BIT 0 TO OV COPY =0,Q CLEAR Q JF OV,$+2 TEST Q REG BIT 0 COPY =4,Q  LOAD Q WITH INDEX IF COUNT33 IS ODD ADD INDXP3,Q ADD PASS INDEX ADD INDXV3,Q ADD VENDOR INDEX ADD =DATTB1,Q ADD BASE ADDRESS OF DATA TABLE COPY Q,POINT31 STORE SUB-TABLE ADDRESS  COPY =:FFE0,Q COPY Q,COUNT34 INITIALIZE LOOP COUNT M51440 COPY POINT31,Q GET SUB-TABLE ADDRESS  COPY Q,POINT32 INITIALIZE TABLE POINTER COPY =:FFFC,Q COPY Q,COUNT35 INITIALIZE LOOP COUNT M51 450 COPY *POINT32,Q GET DATA FROM TABLE COPY Q,0(Y) WRITE DATA TO TEST MEMORY COPY Q,1(Y)  WRITE DATA TO TEST MEMORY COPY Q,2(Y) WRITE DATA TO TEST MEMORY COPY Q,3(Y) WRITE DATA TO TEST MEMORY ADD =4,X INCREMENT PHYSICAL ADDRESS ADD =4,Y INCREMENT LOGICAL ADDRESS  IMS POINT32 INCREMENT DATA TABLE POINTER IMS COUNT35 INCREMENT LOOP COUNT JMP M51450 CONTINUE IMS COUNT34 INCREMENT LOOP COUNT JMP M51440 CONTINUE IMS COUNT33 INCREMENT LOOP COUNT JNE Y,M51430 END OF LOGICAL ADDRESS SPACE ? JUMP IF NOT JEQ X,M51520 JUMP IF END OF CURRENT 64K SEGMENT SBIT 10,S SWITCH TO USER MODE JMP M5143Y CONTINUE SPACE 9 * * VERIFY DATA RAMS * M51520 RBIT 10,S SET STATUS TO SYSTEM MAP COPY =0,X INITIALIZE LOW ORDER PHYSICAL ADDRESS COPY X,COUNT33 INITIALIZE PASS COUNT M5153Y COPY =:8000,Y  INITIALIZE LOGICAL ADDRESS M51530 COPY COUNT33,Q GET LOOP COUNT TBIT 0,Q COPY Q REG BIT 0 TO OV  COPY =0,Q CLEAR Q JF OV,$+2 TEST Q REG BIT 0 COPY =4,Q LOAD Q WITH INDEX IF COUNT33 IS ODD ADD INDXP3,Q ADD PASS INDEX ADD INDXV3,Q ADD VENDOR INDEX ADD  =DATTB1,Q ADD BASE ADDRESS OF DATA TABLE COPY Q,POINT31 STORE SUB-TABLE ADDRESS COPY =:FFE0,Q  COPY Q,COUNT34 INITIALIZE LOOP COUNT M51540 COPY POINT31,Q GET SUB-TABLE ADDRESS COPY Q,POINT32  INITIALIZE TABLE POINTER COPY =:FFFC,Q COPY Q,COUNT35 INITIALIZE LOOP COUNT M51550 COPY =:FFFC,Q COPY Q,COUNT36 INITIALIZE LOOP COUNT COPY *POINT32,Q GET DATA FROM TABLE COPY Q,K  STORE AS EXPECTED DATA M51560 COPY 0(Y),Q READ DATA FROM TEST MEMORY CSK Q,K COMPARE TO EXPECTED NOP ERR: DATA,TEST,ERROR ADD =1,X INCREMENT PHYSICAL ADDRESS ADD =1,Y INCREMENT LOGICAL ADDRESS IMS COUNT36 INCREMENT LOOP COUNT JMP M51560 CONTINUE IMS POINT32 INCREMENT DATA TABLE POINTER IMS COUNT35 INCREMENT LOOP COUNT JMP M51550 CONTINUE IMS COUNT34 INCREMENT LOOP COUNT JMP M51540 CONTINUE IMS COUNT33 INCREMENT LOOP COUNT JNE Y,M51530 END OF LOGICAL ADDRESS SPACE ? JUMP IF NOT JEQ X,$+3 JUMP IF END OF CURRENT 64K SEGMENT SBIT 10,S SWITCH TO USER MODE JMP M5153Y CONTINUE * JST SSCHK CHECK SENSE SWTICH AND BLINK DISPLAY NOP COPY INDXP3,Q GET PASS INDEX JNE Q,M51570 JUMP IF COMPLETED 2ND PASS COPY =8,Q INDEX VALUE FOR 2ND PASS DATA  COPY Q,INDXP3 STORE 2ND PASS DATA INDEX JMP M51420 CONTINUE * M51570 EQU $ JMP M51 410 PATCH FOR LOOPING THROUGH FAIRCHILD DATA ORG $-1 NOP OVERLAY WITH NOP *  COPY INDXV3,Q GET VENDOR INDEX JNE Q,M51580 JUMP IF COMPLETED NATIONAL DATA PASSES COPY =:10,Q INDEX VALUE FOR NATIONAL DATA COPY Q,INDXV3 STORE NATIONAL DATA INDEX JMP M51410 CONTINUE * M51580 EQU $ JMP M51410 PATCH FOR LOOPING THROUGH NATIONAL DATA ORG $-1 JMP M51400 PATCH FOR LOOPING THROUGH BOTH VENDORS ORG $-1 NOP OVERLAY WITH NOP  JMP M51600 TITL * * DATA STORAGE * INDXV3 RES 1,0 VENDOR INDEX INDXP3 RES 1,0  PASS INDEX COUNT33 RES 1,0 LOOP COUNT COUNT34 RES 1,0 LOOP COUNT COUNT35 RES 1,0  LOOP COUNT COUNT36 RES 1,0 LOOP COUNT POINT31 RES 1,0 DATA SUB-TABLE ADDRESS POINT32 RES 1,0  DATA TABLE POINTER * LPOOL TITL * * WRITE ECC RAMS * M51600 COPY =0,Q COPY Q,INDXV3 INITIALIZE VENDOR INDEX M51610 COPY =0,Q COPY Q,INDXP3 INITIALIZE PASS INDEX M51620 RBIT 10,S IS ENCOUNTERED DURING THE VERIFY, THE * PROGRAM HALTS WITH BAD IN THE CONSOLE DATA REGISTER. THE X REGISTER * CONTAINS THE WRITE POINTER, AND THE Y REGISTER CONTAINS THE * WRITE POINTER. PRESS RUN TO CONTINUE VERIFICATION. AT THE END * OF THE VERIFICATION, THE PROGRAM HALTS WITH :C000 IN THE CONSOLE * DATA REGISTER. * TITL * APPENDIX C * *  REVISION DESCRIPTION * * REVISION B100: * 1. ADDED FOUR MAP MMU DIAGNOSTIC. SOURCE MODULES AFFECTED * ARE PAT495P5.ASM & PAT495P6.ASM. * * 2. CHANGED MICRO CACHE TEST MISS/HIT PERCENTAGE FROM :50 * TO :49. SOURCE MODULE AFFECTED IS PAT495P7.ASM. * * * REVISION B200: * 1. CHANGED SEMAPHORE INSTRUCTION TESTS (SIGNAL & WAIT) DUE * TO UPDATE IN FIRMWARE. SOURCES AFFECTED ARE PAT495P2.ASM * PAT495P4.ASM & PATA495.MAC. * * REVISION C000: * 1. CHANGED FOUR MAP MMU REFERENCES LISTED IN B100 ABOVE * TO MMU WITHOUT CACHE REFERENCES. * 2. ADDED MMU TRANSLATED ADDRESS LOOK AHEAD LATCH TEST TO SOURCE * MODULE PAT495P5.ASM AND CHANGED MICRO CACHE MISS/HIT * PERCENTAGE IN MODULE PAT495P7 FROM :4F TO :49. *  3. ADDED MULTIPLE MAP DMA TRANSFER TEST TO SOURCE MODULE * PAT495P5.ASM. * END & WAIT) DUE * TO UPDATE IN FIRMWARE. SOURCES AFFECTED ARE PAT495P2.ASM * PAT495P4.ASM & PATA495.MAC. * * REVISION C000: * 1. CHANGED FOUR MAP MMU REFERENCES LISTED IN B100 ABOVE * TO MMU WITHOUT CACHE REFERENCES. * 2. ADDED MMU TRANSLATED ADDRESS LOOK AHEAD LATCH TEST TO IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII  IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII! 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PAT495P7 ASMPAT495 DOC SET STATUS TO SYSTEM MAP COPY =0,X INITIALIZE LOW ORDER PHYSICAL ADDRESS COPY X,COUNT33  INITIALIZE PASS COUNT M5163Y COPY =:8000,Y INITIALIZE LOGICAL ADDRESS M51630 COPY COUNT33,Q GET LOOP COUNT 1  TBIT 0,Q COPY Q REG BIT 0 TO OV COPY =0,Q CLEAR Q JF OV,$+2 TEST Q REG BIT 0 COPY =4,Q LOAD Q WITH INDEX IF COUNT33 IS ODD ADD INDXP3,Q ADD PASS INDEX  ADD INDXV3,Q ADD VENDOR INDEX ADD =ECCTB1,Q ADD BASE ADDRESS OF DATA TABLE COPY Q,POINT31  STORE SUB-TABLE ADDRESS COPY =:FFE0,Q COPY Q,COUNT34 INITIALIZE LOOP COUNT M51640 COPY POINT31,Q GET SUB-TABLE ADDRESS COPY Q,POINT32 INITIALIZE TABLE POINTER COPY =:FFFC,Q COPY Q,COUNT35 INITIALIZE LOOP COUNT M51650 COPY *POINT32,Q GET DATA FROM TABLE COPY Q,0(Y) WRITE DATA TO TEST MEMORY COPY Q,1(Y) WRITE DATA TO TEST MEMORY COPY Q,2(Y) WRITE DATA TO TEST MEMORY  COPY Q,3(Y) WRITE DATA TO TEST MEMORY ADD =4,X INCREMENT PHYSICAL ADDRESS ADD =4,Y  INCREMENT LOGICAL ADDRESS IMS POINT32 INCREMENT DATA TABLE POINTER IMS COUNT35 INCREMENT LOOP COUNT JMP M51650 CONTINUE IMS COUNT34 INCREMENT LOOP COUNT JMP M51640 CONTINUE IMS COUNT33 INCREMENT LOOP COUNT JNE Y,M51630 END OF LOGICAL ADDRESS SPACE ? JUMP IF NOT JEQ X,M51720 JUMP IF END OF CURRENT 64K SEGMENT SBIT 10,S SWITCH TO USER MODE  JMP M5163Y CONTINUE SPACE 8 * * VERIFY ECC RAMS * M51720 RBIT 10,S SET STATUS TO SYSTEM MAP COPY A,Q LOAD Q WITH HIGH ORDER PHYSICAL ADDRESS COPY =0,Y INITIALIZE LOW ORDER PHYSICAL ADDRESS COPY Y,COUNT33 INITIALIZE PASS COUNT M5173Y COPY =:8000,X INITIALIZE LOGICAL ADDRESS M51730 COPY COUNT33,A GET LOOP COUNT TBIT 0,A COPY Q REG BIT 0 TO OV COPY =0,A  CLEAR Q JF OV,$+2 TEST A REG BIT 0 COPY =4,A LOAD Q WITH INDEX IF COUNT33 IS ODD  ADD INDXP3,A ADD PASS INDEX ADD INDXV3,A ADD VENDOR INDEX ADD =DATTB1,A ADD BASE ADDRESS OF DATA TABLE COPY A,POINT31 STORE SUB-TABLE ADDRESS COPY =:FFE0,A COPY A,COUNT34  INITIALIZE LOOP COUNT SPACE 2 M51740 COPY POINT31,A GET SUB-TABLE ADDRESS COPY A,POINT32 INITIALIZE TABLE POINTER COPY =:FFFC,A COPY A,COUNT35 INITIALIZE LOOP COUNT M51750 COPY =:FFFC,A  COPY A,COUNT36 INITIALIZE LOOP COUNT COPY *POINT32,A GET DATA FROM TABLE AND =:1F,A WANT ONLY BITS 0-4 COPY A,K STORE AS EXPECTED DATA M51760 LODECC . READ ECC WORD FROM TEST MEMORY CSK A,K COMPARE TO EXPECTED NOP JMP $+2 ERROR JMP M51763  OK EXCH A,Q ACTUAL DATA --> Q; HIGH PHYS. ADDR. --> A EXCH X,Y LOGICAL ADDR. --> Y; LOW PHYS. ADDR. --> X ERR: DATA,TEST,ERROR EXCH X,Y LOGICAL ADDR. --> X; LOW PHYS. ADDR. -->2  Y COPY A,Q HIGH PHYS. ADDR. --> Q M51763 ADD =1,X INCREMENT PHYSICAL ADDRESS ADD  =1,Y INCREMENT LOGICAL ADDRESS IMS COUNT36 INCREMENT LOOP COUNT JMP M51760 CONTINUE IMS POINT32 INCREMENT DATA TABLE POINTER IMS COUNT35 INCREMENT LOOP COUNT JMP  M51750 CONTINUE IMS COUNT34 INCREMENT LOOP COUNT JMP M51740 CONTINUE IMS  COUNT33 INCREMENT LOOP COUNT JNE X,M51730 END OF LOGICAL ADDRESS SPACE ? JUMP IF NOT JEQ Y,$+3 JUMP IF END OF CURRENT 64K SEGMENT SBIT 10,S SWITCH TO USER MODE JMP M5173Y CONTINUE * COPY Q,A RESTORE A WITH HIGH ORDER PHYSICAL ADDRESS JST SSCHK CHECK SENSE SWTICH AND BLINK DISPLAY NOP COPY INDXP3,Q GET PASS INDEX JNE Q,M51770 JUMP IF COMPLETED 2ND PASS COPY =8,Q INDEX VALUE FOR 2ND PASS DATA COPY Q,INDXP3 STORE 2ND PASS DATA INDEX  JMP M51620 CONTINUE * M51770 EQU $ JMP M51610 PATCH FOR LOOPING THROUGH FAIRCHILD DATA  ORG $-1 NOP OVERLAY WITH NOP * COPY INDXV3,Q GET VENDOR INDEX JNE  Q,M51780 JUMP IF COMPLETED NATIONAL DATA PASSES COPY =:10,Q INDEX VALUE FOR NATIONAL DATA COPY Q,INDXV3 STORE NATIONAL DATA INDEX JMP M51610 CONTINUE * M51780 EQU $ JMP M51610  PATCH FOR LOOPING THROUGH NATIONAL DATA ORG $-1 JMP M51600 PATCH FOR LOOPING THROUGH BOTH VENDORS ORG $-1 NOP OVERLAY WITH NOP TITL RBIT 10,S SWITCH TO SYSTEM MAP ADD =1,A INCREMENT HIGH ORDER PHYSICAL ADDRESS CSK A,MEMSIZ END OF MEMORY ?  NOP JMP $+2 NO JMP M51790 YES, EXIT JST INCTB2 MODIFY TRANSLATE TABLE JMP M51000 CONTINUE M51790 EQU $ JMP M50000 PATCH FOR LOOPING THROUGH ALL MEMORY ORG $-1 NOP OVERLAY WITH NOP JMP M60000 LPOOL TITL BYTE TEST -- ABOVE 1ST 64K TESTING (TEST A) ******** * * M60000 * * BYTE TEST -- ABOVE 1ST 64K TESTING * * THIS TEST WRITES MEMORY WITH DATA PATTERNS IN BYTE * MODE, ALTERNATING UPPER BYTE FIRST AND LOWER BYTE * FIRST, WORD BY WORD. IT THEN VERIFIES THE MEMORY * WRITTEN, READING IN BYTE MODE. * ******** * * WRITE MEMORY * M60000 EQU  $ JST INIT2 INITIALIZE TRANSLATE TABLE COPY =1,A INITIALIZE HIGH ORDER PHYSICAL ADDRESS M61000 RBIT 10,S SET STATUS TO SYSTEM MODE COPY A,ATEMP SAVE HIGH ORDER PHYSICAL ADDRESS  COPY =0,X INITIALIZE LOW ORDER PHYSICAL ADDRESS COPY =:55,A LOAD A WITH UPPER BYTE DATA COPY =:AA,Q LOAD Q WITH LOWER BYTE DATA M61010 COPY =:8000,Y INITIALIZE LOGICAL ADDRESS SBIT 2,S 3  SET BYTE MODE M61020 COPY A,0(Y) WRITE DATA TO TEST MEMORY (UPPER BYTE) COPY Q,1(Y) WRITE DATA TO TEST MEMORY (LOWER BYTE) COPY Q,3(Y) WRITE DATA TO TEST MEMORY (LOWER BYTE) COPY A,2(Y)  WRITE DATA TO TEST MEMORY (UPPER BYTE) ADD =2,X INCREMENT PHYSICAL ADDRESS ADD =2,Y  INCREMENT LOGICAL ADDRESS JNE Y,M61020 JUMP IF NOT END OF LOGICAL ADDRESS SPACE RBIT 2,S SET WORD MODE JEQ X,$+3 JUMP IF END OF CURRENT 64K BLOCK SBIT 10,S SWITCH TO USER MODE  JMP M61010 CONTINUE TITL * * VERIFY MEMORY * M61100 EQU $ COPY A,K LOAD K WITH UPPER BYTE EXPECTED DATA COPY Q,L LOAD L WITH LOWER BYTE EXPECTED DATA COPY ATEMP,A  RESTORE A WITH HIGH ORDER PHYSICAL ADDRESS RBIT 10,S SET STATUS TO SYSTEM MODE COPY =0,X  INITIALIZE LOW ORDER PHYSICAL ADDRESS M61110 COPY =:8000,Y INITIALIZE LOGICAL ADDRESS SBIT 2,S  SET BYTE MODE M61120 COPY 0(Y),Q READ DATA FROM TEST MEMORY (UPPER BYTE) CSK Q,K COMPARE TO EXPECTED NOP JMP $+2 ERROR JMP M61123 OK RBIT 2,S SET WORD MODE ERR: BYTE,TEST,FAILURE,--,UPPER,BYTE SBIT 2,S SET BYTE MODE M61123 EXCH K,L  LOAD K WITH EXPECTED DATA COPY 1(Y),Q READ DATA FROM TEST MEMORY (LOWER BYTE) CSK Q,K COMPARE TO EXPECTED NOP JMP $+2 ERROR JMP M61126 OK RBIT 2,S  SET WORD MODE ERR: BYTE,TEST,FAILURE,--,LOWER,BYTE SBIT 2,S SET BYTE MODE M61126 EXCH K,L LOAD K WITH EXPECTED DATA ADD =1,X INCREMENT PHYSICAL ADDRESS ADD =1,Y INCREMENT LOGICAL ADDRESS JNE Y,M61120 JUMP IF NOT END OF LOGICAL ADDRESS SPACE RBIT 2,S SET WORD MODE JEQ X,$+3 JUMP IF END OF CURRENT 64K BLOCK SBIT 10,S SWITCH TO USER MODE  JMP M61110 CONTINUE * M61130 EQU $ JST SSCHK CHECK SENSE SWTICH AND BLINK DISPLAY  JMP M61000 PATCH FOR LOOPING THROUGH CURRENT 64K ORG $-1 NOP OVERLAY WITH NOP * RBIT 10,S SWITCH TO SYSTEM MAP ADD =1,A INCREMENT HIGH ORDER PHYSICAL ADDRESS  CSK A,MEMSIZ END OF PYHSICAL ADDRESS SPACE ? NOP JMP $+2 NO JMP $+3  YES JST INCTB2 MODIFY TRANSLATE TABLE JMP M61000 CONTINUE * JMP M60000  PATCH FOR LOOPING THROUGH ALL MEMORY ORG $-1 NOP OVERLAY WITH NOP JMP M70000 LPOOL TITL CACHE TEST -- ABOVE 1ST 64K TESTING (TEST A) ******** * * M70000 * * CACHE TEST -- ABOVE 1ST 64K TESTING * * (SEE DESCRIPTION AT BEGINNING OF SECTION M35000) * ******** M70000 EQU $ JST 4  INIT2 INITIALIZE TRANSLATE TABLE COPY =1,A INITIALIZE HIGH ORDER PHYSICAL ADDRESS COPY A,PHYADR * M71000 RBIT 10,S SET STATUS TO SYSTEM MODE COPY =1,Q OUT Q,5 ENABLE TRANSLATION TABLE ACCESS ONLY COPY =:FC40,X BASE ADDRESS OF TRANSLATION TABLE COPY :20(X),Q GET WORD :20 IN USER MAP 1 SUB =1,Q COPY Q,:1F(X) MODIFY WORD :1F IN USER MAP 1 IN 7,Q CLEAR PARITY ERROR COPY =2,Q OUT Q,5 ENABLE TRANSLATION ONLY SBIT 10,S SWITCH TO USER MAP 1 COPY  =:0004,Q INITIALIZE ADDRESS BIT MASK TITL * * CACHE HIT TEST * M71010 RBIT 8,S DISABLE INTERRUPTS SBIT 5,S ENABLE REAL-TIME CLOCK COPY Q,K STORE CURRENT ADDRESS BIT MASK XOR =:FFFC,Q FORM CURRENT ADDRESS COPY Q,X INITIALIZE CURRENT ADDRESS 1 COPY INSTR1,Q -- COPY Q,0(X) -- COPY INSTR2,Q -- COPY Q,1(X) -- SET UP TEST LOOP COPY INSTR3,Q -- IN MEMORY COPY Q,2(X) -- COPY INSTR4,Q -- COPY Q,3(X)  -- * COPY =:FFFE,Q -2 COUNT COPY Q,RTCTIM INITIALIZE RTC INCREMENT LOCATION COPY =M71020,Q RTC INTERRUPT SERVICE ROUTINE LOC. COPY Q,RTCPTR STORE IN RTC INTERRUPT LOCATION SBIT 8,S START RTC JMP $ WAIT FOR INTERRUPT * M71020 ENT RTC INTERRUPT SERVICE ROUTING COPY =:FFFE,Q -2 COUNT COPY Q,RTCTIM INITIALIZE RTC INCREMENT LOCATION COPY =M71030,Q RTC INTERRUPT SERVICE ROUTINE LOC COPY Q,RTCPTR STORE IN RTC INTERRUPT LOCATION COPY X,Y  ADD =2,Y INITIALIZE CURRENT ADDRESS 2 COPY =0,Q INITIALIZE TIMING LOOP COUNTER SBIT 8,S START RTC JMP 0(X) JUMP INTO TIMING LOOP TITL M71030 ENT RTC INTERRUPT SERVICE ROUTINE COPY Q,HITCNT1 SAVE NO. OF HITS COPY =:FFFC,Q SET -4 COUNTS COPY Q,RTCTIM INIT. RTC INCREMENT LOCATION COPY =M71040,Q RTC SERVICE ROUTINE ADDRESS COPY Q,RTCPTR STORE IT IN RTC INT. ADDRESS COPY =0,Q RESET HIT COUNTS SBIT 8,S ENABLE INTERRUPT JMP 0(X) JUMP INTO TIMMING LOOP * M71040 ENT COPY Q,HITCNT2 SAVE NOO. OF HITS COPY =0,A COPY =100,Q MUL HITCNT1,AQ MULT. 1ST NO. OF HITS BY 100 DIV HITCNT2,AQ DIVIDE BY 2ND NO. OF HITS CSME Q,LIMIT1 COMPARE TIMING COUNT TO HIGH LIMIT JMP $+3 OK NOP ERROR ERROR: CACHE,TEST,FAILURE * TIMING LOOP COUNT ABOVE LIMIT * LOOP EXECUTED FASTER THAN EXPECTED * Q = TIMING LOOP COUNT * CSME Q,LIMIT2 COMPARE TIMING COUNT TO LOW LIMIT ERROR: CACHE,TEST,FAILURE * TIMING LOOP COUNT BELOW LIMIT *  POSSIBLE ERRONEOUS CACHE MISSES * Q = TIMING LOOP COUNT * NOP 5  COPY K,Q LOAD Q WITH CURRENT ADDRESS BIT MASK TBIT 15,Q COPY KIT 15 TO OV JT OV,M71100 JUMP IF REACHED BIT 15 SHIFT Q,L,1 SHIFT ADDRESS BIT MASK TO NEXT BIT JMP M71010 CONTINUE LPOOL * INSTR1 NOP -- INSTR2 JMP 0(Y) -- CACHE TEST LOOP INSTR3 ADD =1,Q  -- INSTRUCTIONS INSTR4 JMP 0(X) -- * LIMIT1 WORD :0035 53% HIGH LIMIT LIMIT2 WORD :002F 47% LOW LIMIT LIMIT3 WORD :0057 87% HIGH LIMIT LIMIT4 WORD :0049 79% LOW LIMIT HITCNT1 WORD 0 HITCNT2 WORD 0 MISCNT1 WORD 0 MISCNT2 WORD 0 TITL * * CACHE MISS TEST * M71100 EQU $ COPY =:FFFC,Y INITIALIZE PHYSICAL ADDRESS 2  COPY INSTR3,Q -- COPY Q,0(Y) -- SET UP 2ND HALF COPY INST4,Q -- TEST LOOP IN MEMORY COPY Q,1(Y) -- COPY =:0004,Q INITIALIZE ADDRESS BIT MASK M71110 COPY Q,K STORE CURRENT ADDRESS BIT MASK XOR =:FFFC,Q FORM CURRENT ADDRESS COPY Q,X INITIALIZE PHYSICAL ADDRESS 1 COPY INSTR1,Q -- COPY Q,0(X) -- SET UP 1ST HALF COPY INSTR2,Q -- TEST LOOP IN MEMORY COPY Q,1(X) -- COPY =:FFFE,Q MINUS 2 COUNT COPY Q,RTCTIM INITIALIZE RTC INCREMENT LOCATION COPY =M71120,Q RTC INTERRUPT SERVICE ROUTINE LOC. COPY Q,RTCPTR STORE AT RCT INTERRUPT LOCATION SBIT 8,S START RTC JMP $ WAIT FOR INTERRUPT M71120 ENT RTC INTERRUPT SERVICE ROUTINE COPY =:FFFE,Q MINUS 2 COUNT COPY Q,RTCTIM INITIALIZE RTC INCREMENT LOCATION COPY =M71130,Q RTC INTERRUPT SERVICE ROUTINE LOC. COPY Q,RTCPTR STORE AT RTC INTERRUPT LOCATION COPY =0,Q INITIALIZE TIMING LOOP COUNTER SBIT 8,S START RTC JMP 0(X) JUMP INTO TIMING LOOP TITL M71130 ENT RTC INTERRUPT SERVICE ROUTINE COPY Q,MISCNT1 SAVE NO. OF MISSES COPY =:FFFC,Q MINUS 4 OCUNT COPY Q,RTCTIM INTIT. RTC INCREMENT CELL COPY =M71140,Q RTC INT. SERVICE ADDRESS COPY Q,RTCPTR STORE AT RTC INT. LOCATION COPY =0,Q RESET MISS COUNT SBIT 8,S ENABLE INTERRUPT JMP 0(X) JMUP INTO TIMMING LOOP * M71140 ENT COPY Q,MISCNT2 SAVE NO. OF MISSES COPY =0,A COPY =100,Q MUL MISCNT1,AQ MULT. 1ST SET OF MISSES BY 100 DIV MISCNT2,AQ DIVIDE BY 2ND SET OF MISSES CSME Q,LIMIT1 COMPARE TIMING COUNT TO HIGH LIMIT JMP $+3 OK NOP ERROR ERROR: CACHE,TEST,FAILURE *  TIMING LOOP COUNT ABOVE LIMIT * POSSIBLE ERRONEOUS CACHE HITS *  Q = TIMING LOOP COUNT * CSME Q,LIMIT2 COMPARE TIMING COUNT TO LOW ERROR ERROR: CACHE,TEST,FAILURE * TIMING LOOP COUNT BELOW LIMIT * TIMING LOOP COUNT BELOW LIMIT * LOOP EXECUTIVED LOW COUNT * LOOP EXECUTED SLOWER TH6 AN EXPECTED * Q = TIMING LOOP COUNT * NOP COPY K,Q LOAD Q WITH ADDRESS BIT MASK TBIT 15,Q COPY BIT 15 TO OV JT OV,M71150 JUMP IF REACHED BIT 15 SHIFT Q,L,1 SHIFT ADDRESS BIT MASK TO NEXT BIT JMP M71110 CONTINUE M71150 EQU $ COPY =0,A COPY =100,Q MUL MISCNT2,AQ DIV HITCNT2,AQ CALCULATE MISS/HIT RATIO CSME Q,LIMIT3 COMPARE MISS/HIT RATIO TO HIGH LIMIT JMP $+3 HLT MICRO CACHE FAILED -- MAKE SURE MMU CACHE SW. * IS NOT FORCED ON. NOP CSME Q,LIMIT4 CO,PARE MISS/HIT RATIO TO LOW LIMIT HLT MICRO CACHE FAILED -- MAKE SURE MMU CACHE SW. * IS NOT FORCED ON. NOP * M71200 JMP M71000 PATCH FOR LOOPING THROUGH CURRENT 64K ORG $-1 NOP OVERLAY WITH NOP * RBIT 10,S SWITCH TO SYSTEM MAP COPY PHYADR,A ADD =1,A INCREMENT HIGH ORDER PHYSICAL ADDRESS COPY A,PHYADR CSK A,MEMSIZ END OF PHYSICAL ADDRESS SPACE ? NOP JMP $+2  NO JMP $+3 YES JST INCTB2 MODIFY TRANSLATE TABLE JMP M71000 CONTINUE * JMP M70000 PATCH FOR LOOPING THROUGH ALL MEMORY ORG $-1 NOP OVERLAY WITH NOP JMP INIT20 PHYADR WORD 0 LPOOL TITL ****** * * GROUP2 TRANSLATE TABLE SUBROUTINES * * INIT2 * INCTB2 * * THESE SUBROUTINES MODIFY THE FIRST 128 WORDS OF * THE TRANSLATE TABLE. THE FIRST 64 ARE THE SYSTEM * MAP, AND THE SECOND 64 WORDS ARE SYSTEM MAP 1. * THE FIRST 32 SYSTEM MAP WORDS POINT TO THE FIRST * 32 1K PHYSICAL MEMORY PAGES RESPECTIVELY. THE * FIRST 32 USER MAP WORDS ARE IDENTICAL TO THE FIRST * 32 SYSTEM MAP WORDS. THE SECOND 32 SYSTEM MAP * WORDS, AND THEN THE SECOND 32 USER MAP WORDS AS * A 64 WORD BLOCK POINT TO 64 CONSECUTIVE 1K PHYSI- * CAL MEMORY PAGES RESPECTIVELY. THIS 64K WORD BLOCK * STARTS ON A 64K WORD BOUNDRY, AND IS THE MEMORY *  BLOCK CURRENTLY BEING TESTED. * ****** * * SUBROUTINE INIT2 * * THIS SUBROUTINE INITIALIZES THE FIRST 32 WORDS OF * BOTH THE SYSTEM MAP AND USER MAP 1 TO POINT TO THE * FIRST 32K WORDS OF PHYSICAL MEMORY, AND INITIALIZES * THE SECOND 32 WORDS OF THE SYSTEM MAP AND OF USER * MAP 1 TO POINT TO THE SECOND 64K WORDS OF PHYSICAL * MEMORY. * THIS SUBROUTINE LEAVES THE MMU WITH ONLY TRANSLATION * ENABLED. THE A, Q, X, AND Y REGISTER CONTENTS ARE * DESTROYED. * INIT2 ENT COPY =1,A OUT A,5 ENABLE TABLE ACCESS COPY =:FC00,X INITIALIZE TRANS. TABLE INDEX (SYSTEM MAP) COPY =:FC40,Y INITIALIZE TRANS. TABLE INDEX (USER MAP 1) COPY =:3000,A INITIALIZE DATA (READ, WRITE, EXEC. ENBL.) INIT2A COPY A,0(X) WRITE TO TRANSLATE TABLE COPY A,0(Y) WRITE TO TRANSLATE TABLE ADD =1,A INCREMENT DATA ADD =1,X INCREMENT SYSTEM MAP INDEX ADD =1,Y INCREMENT USER MAP 1 INDEX COPY X,Q INDEX TO Q CSK Q,=:FC20 END OF FIRST AND THIRD 32 WORDS? NOP JMP INIT2A 7  NO, CONTINUE COPY =:3040,A RE-INITIALIZE DATA (READ, WRITE ENBL.) INIT2B COPY A,0(X) WRITE DATA TO TRANSLATE TABLE ADD =1,A INCREMENT DATA ADD =1,X INCREMENT INDEX COPY X,Q INDEX TO Q CSK Q,=:FC40 END OF SECOND 32 WORDS? NOP JMP INIT2B NO,CONTINUE INIT2C COPY A,0(Y) WRITE DATA ADD =1,A INCREMENT DATA ADD =1,Y INCREMENT INDEX COPY Y,Q INDEX TO Q CSK Q,=:FC80 END OF FOURTH 32 WORDS? NOP JMP INIT2C NO, CONTINUE IN 7,A CLEAR PARITY ERROR COPY =2,A OUT A,5 ENABLE TRANSLATION, DISABLE TABLE ACCESS JMP *INIT2 RETURN * * SUBROUTINE INCTB2 * * THIS SUBROUTINE MODIFIES THE SECOND 32 WORDS OF THE * SYSTEM MAP AND THE SECOND 32 WORDS OF USER MAP 1 TO * POINT TO THE 64K PHYSICAL MEMORY BLOCK NEXT HIGHER IN * ADDRESS SPACE. * THIS SUBROUTINE LEAVES THE MMU WITH ONLY TRANSLATION *  ENABLED. ALL REGISTER CONTENTS ARE PRESERVED. * INCTB2 ENT COPY A,ATEMP1 SAVE A REGISTER COPY X,XTEMP1 SAVE X REGISTER COPY =1,A OUT A,5 ENABLE TABLE ACCESS COPY =:FC20,X INITIALIZE TRANSLATE TABLE INDEX TAB2A COPY 0(X),A GET DATA FROM TRANSLATE TABLE ADD =:40,A MODIFY TRANSLATE TABLE ENTRY COPY A,0(X) RESTORE DATA TO TRANSLATE TABLE ADD =1,X INCREMENT INDEX COPY X,A INDEX TO A CSK A,=:FC40 END OF SECOND 32 WORDS? NOP JMP TAB2A NO, CONTINUE ADD =:20,X RE-INITIALIZE X TO FOURTH 32 WORDS TAB2B COPY 0(X),A GET DATA FROM TRANSLATE TABLE ADD =:40,A MODIFY TRANSLATE TABLE ENTRY COPY A,0(X) RESTORE DATA TO TRANSLATE TABLE ADD =1,X COPY X,A INDEX TO A CSK A,=:FC80 END OF FOURTH 32 WORDS? NOP JMP TAB2B NO, CONTINUE IN 7,A CLEAR PARTIY ERROR COPY =2,A OUT  A,5 ENABLE TRANSLATION, DISABLE TABLE ACCESS COPY XTEMP1,X RESTORE A REGISTER COPY ATEMP1,A RESTORE X REGISTER JMP *INCTB2 RETURN * ATEMP1 RES 1,0 TEMPORARY STORAGE XTEMP1 RES 1,0 TEMPORARY STORAGE  LPOOL TITL INITIALIZATION (TEST B) ******* * * FIRST 64K TESTING * * THIS SECTION TESTS THE FIRST 64K OF MEMORY. TESTING * IS DONE WITH NO ADDRESS TRANSLATION (I.E. MMU RESET). * * FIRST THE SECOND 32K OF MEMORY IS TESTED, THEN THE * CONTENTS OF THE FIRST 32K OF MEMORY IS COPIED TO THE * SECOND 32K AND VERIFIED, THEN CONTROL IS TRANSFERED * TO THE COPIED PROGRAM IN THE SECOND 32K. THE FIRST * 32K OF MEMORY IS THEN TESTED, THE CONTENTS OF \HE * SECOND 32K OF MEMORY IS COPIED BACK TO THE FIRST 32K * AND VERIFIED, AND FINALLY CONTROL IS TRANSFERED BACK * TO THE COPIED PROGRAM IN THE FIRST 32K. * * TESTING OF EACH OF THE 32K SECTIONS OF MEMORY IS PERFORMED * IN TWO PARTS: DOUBLE BIT ERROR, AND SINGLE BIT ERRORS. * * THE SAME CODE IS EXECUTED FOR TESTING BOTH THE FIRST * AND THE SECOND 32K OF MEMORY, AND THUS MUST BE EXE- * CUTABLE WHEN THE PRO8 GRAM HAS RELOCATED IT SELF. * * TESTING EXCLUDES LOCATIONS :84-:8B (UNIMPLEMENTED * INSTRUCTION TRAP AND MEMORY EXCEPTION TRAP VECTORS). * DURING PROGRAM RELOCATION, THE TWO TRAPS CONTAIN * JUMPS TO SPECIAL SERVICE ROUTINES IN THE RELOCATED * PROGRAM. OCCURRINCE OF ANY OTHER INTERRUPTS OR TRAPS * DURING PROGRAM RELOCATION WILL HAVE UDFINED RESULTS. * ********** TITL * * * INITIALIZATION * *  * SPACE 1 ECCS EQU $ INIT20 EQU $ COPY DEMAND,A DEMAND MODE SELECTIONS  AND =:400,A TEST BIT #10 JGT A,$+3 IF BIT #10 SET, RUN MEMORY TEST B JMP *$+1  WORD PART8ST COPY DMAND2,A AND =:0004,A JEQ A,$-4 ***** COPY =:B,A MEMORY TEST CODE SELP  A,4 OUTPUT TO CONSOLE DISPLAY COPY =:33,X ADDRESS OF CONTEXT BLOCK COPY =INIT21,A JMP ADDRESS OF LOAD CONTEXT INSTRUCTION COPY A,0(X) STORE IN CONTEXT BLOCK COPY STATSV,A INITIAL STATUS COPY A,2(X) STORE IN CONTEXT BLOCK LCNTX INITIALIZE CONTEXT POINTER,STATUS ***** INIT21 EQU $ COPY =0,A JF SS,$+2 TEST SENSE SWITCH COPY =1,A COPY A,SENSW22 SAVE SENSE SWITCH JST M10100 CALCULATE MEMORY SIZE ***** INIT22 EQU $ COPY =0,A  OUT A,4 RESET MMU TITL * * * SET MEMORY TESTING LIMITS  * * * COPY =:8000,A -- COPY A,LOLIMX2 -- SET LOW  COPY A,LOLIM12 -- LIMIT COPY A,LOLIM2A -- ***** COPY =:FFFF,A -- COPY A,HILIMX2 -- SET HIGH MEMORY COPY A,HILIM02 -- TESTING LIMIT COPY ADD1B,A -- COPY  A,TRAPADD1 -- COPY ADD2B,A -- SET UP COPY A,TRAPADD2 -- TRAP SERVICE COPY ADD3B,A -- LOCATIONS IN COPY A,TRAPADD3 -- MEMORY COPY ADD4B,A -- COPY A,TRAPADD4 -- *********** * * DOUBLE BIT ERROR TEST AND SINGLE BIT ERROR TEST * * THESE TESTS WILL ONLY TEST FOR HARD ERROR ! * * THE DOUBLE BIT ERROR TEST WILL ONLY HALT WHEN TWO BITS * ARE FOUND BAD, GIVING THE MEMORY LOCATION OF THE ERROR. * * THE SINGLE BIT ERROR TEST WILL ONLY HALT WHEN ONE BIT * IS FOUND TO BE BAD, GIVING BOTH THE BAD BIT AND THE * MEMORY LOCATION OF THE ERROR. * ********** TITL FIRST 64K TESTING (TEST B) * * TEST FOR DOUBLE BIT ERRORS * F64000 EQU $ COPY =:0,A COPY A,MEMREF INITIALIZE MEMORY LOCATION  COPY A,MEMREF1 INITIALIZE MEMORY LOCATION COPY LOLIMX2,X INITIALIZE MEMORY ADDRESS COPY HILIMX2,Q ADD =1,Q COPY Q,MEMLIM SET HIGH MEMORY TESTING LIMIT JST F64020 DO DOUBLE AND SINGLE BIT ERROR TEST JMP REL0001 F64020 ENT DOUBLE AND SINGLE BIT ERROR TEST F64100 COPY =1,Y F69 4001 EQU $ COPY =:84,A SET UP TO TEST FOR TRAP LOCATIONS CSK A,X TEST FOR TRAP LOCATIONS JMP NTRAP JMP NTRAP COPY =:8C,X NTRAP COPY X,Q SAVE MEMORY LOCATION COPY =:88,X -- SET UP MEMORY COPY TRAPADD1,A -- TRAP SERVICE ROUTINE COPY A,3(X) -- COPY JMP1,A STORE JMP *$+1 COPY A,2(X) IN 3RD WORD OF TRAP COPY Q,X RESTORE MEMORY LOCATION XNX Y COPY F64VAL,Q DETERMINE DATA WORD COPY Q,0(X) WRITE MEMORY TEST WORD  COPY Q,K SAVE TEST WORD COPY 0(X),Q READ TEST WORD, DOUBLE BIT ERRORS TRAP CSK Q,K COMPARE TO EXPECTED TEST WORD NOP JMP BERROR1+1 ERROR IN DATA OR ECC CODE TITL * *  TEST FOR SINGLE BIT ERRORS * COPY X,Q SAVE MEMORY LOCATION COPY =:88,X -- SET UP MEMORY TRAP COPY TRAPADD2,A -- SERVICE ROUTINE SINGLE COPY A,3(X) -- BIT ERRORS COPY Q,X RESTORE MEMORY LOCATION COPY K,A SAVE EXPECTECD DATA JNE A,F64010 IS EXPECTED DATA EQUAL TO ZERO COPY =:8000,Q YES CHANGE TEST WORD TO 8000 JMP $+2 F64010 COPY =:7FFF,Q  NO, CHANGE TEST WORD TO 7FFF COPY Q,0(X) WRITE TEST WORD INTO MEMORY JNE A,F64011 JMP $+2 F64011 COPY =:1F,A SET A REG FOR ECC CODE STRECC . CHANGE ECC CODE TO EXPECTED ECC CODE COPY 0(X),Q READ DATA FROM MEMORY, DOUBLE BIT ERRORS TRAP CSK Q,K COMPARE TO EXPECTED TEST WORD NOP JMP BERROR2+1 ERROR IN DATA OR IN ECC CODE COPY K,A SAVE EXPECTED DATA JNE A,F64012 IS EXPECTED DATA EQUAL TO ZERO COPY =1,Q YES, CHANGE TEST WORD TO 0001  JMP $+2 TITL SPACE 2 F64012 EQU $ COPY =:FFFE,Q NO, CHANGE TEST WORD TO FFFE COPY Q,0(X) WRITE DATA INTO MEMORY JNE A,F64013 JMP $+2 F64013 COPY =:1F,A SET A REG. FOR ECC CODE STRECC . CHANGE ECC CODE TO EXPECTED ECC CODE COPY 0(X),Q  READ TEST WORD FROM MEM.DOUBLE BIT ERROR TRAP CSK Q,K COMPARE TO EXPECTED TEST WORD NOP  JMP BERROR2+1 ERROR IN DATA OR IN ECC CODE RTEST EQU $ JEQ Y,NTEST TEST FOR NEXT TEST WORD  COPY =0,Y SET UP FOR NEXT TEST WORD JMP F64001 CONTINUE TESTING MEMORY LOCATION NTEST EQU $ COPY X,MEMLOC1 SAVE MEMORY LOCATION JST SSCHK24 CHECK SENSE SWITCH AND BLINK DISPLAY COPY MEMLOC1,X RESTORE MEMORY LOCATION ADD =:1,X GET NEXT MEMORY LOCATION COPY MEMLIM,A GET MEMORY LIMIT CSK X,A COMPARE TO UPPER MEMORY LIMIT JMP F64100 CONTINUE TESTING JMP F64100 JMP *F64020 MEMREF RES 1,0 ADD1B WORD BERROR1 ADD2B WO: RD BERROR2 ADD3B WORD TRAP2 ADD4B WORD TRAP3 TRAPADD1 RES 1,0 TRAPADD2 RES 1,0 TRAPADD3 RES 1,0 TRAPADD4 RES 1,0 SENSADR WORD SSCHK24 LPOOL TITL TRAP SERVICE ROUTINE 2 (TEST B) F64VAL EQU $ WORD :FFFF WORD :0000 LOLIMX2 RES 1,0 LOW MEMORY - TESTING LIMIT HILIMX2 RES 1,0  HIGH MEMORY - TESTING LIMIT MEMLOC1 RES 1,0 MEMORY LOCATION MEMLIM RES 1,0 MEMORY LIMIT MEMREF1 RES  1,0 * * MEMORY EXCEPTION TRAP SERVICE ROUTNE * BERROR1, BERROR2 * BERROR1 ENT COPY MEMREF,A  PHYSICAL ADDRESS HLT *** *** A = PHYSICAL ADDRESS, X = LOGICAL ADDRESS * PUSH RUN TO RESUME TEST *** JMP RTEST RESUME TESTING TRAP2 ENT COPY K,A SAVE EXPECTED TEST WORD  JEQ A,T002 IS TEST WORD 0'S OR F'S JMP R0015 F'S, CONTINUE TESTING T002 JMP R0016 0'S, CONTINUE TESTING REL0001 JMP REL000 *** BERROR2 ENT COPY X,Q SAVE MEMORY LOCATION COPY =:88,X --  SET 2ND TRAP COPY TRAPADD3,A -- SERVICE ROUTINE COPY A,3(X) -- COPY Q,X RESTORE MEMORY LOCATION COPY K,A JEQ A,ZERO IS THE SECOND BIT ERROR FROM 0'S OR F'S COPY =:FFFF,Q SET TEST WORD RBIT 1,S RESET OV TITL R0015 EQU $ ROTATE Q,LO,1 RIPPLE 0 THROUGH TEST WORD COPY =:1F,A EXPECTED ECC CODE JF OV,NERROR NO ERROR FOUND IN TEST WORD TRY ECC CODE COPY Q,0(X) WRITE TEST WORD TO MEMORY STRECC . WRITE EXPECTED ECC CODE COPY  0(X),A READ TEST WORD CSK A,K COMPARE TO EXPECTED DATA NOP JMP R0015 CONTINUE LOOKING FOR ERROR JMP FERROR ERROR FOUND *** TITL SPACE 2 ZERO EQU $  COPY =0,Q SET TEST WORD SBIT 1,S SET OV R0016 ROTATE Q,LO,1 RIPPLE 1 THROUGH TEST WORD  COPY =0,A EXPECTED ECC CODE JT OV,NERROR NO ERROR FOUND IN TEST WORD TRY ECC CODE COPY  Q,0(X) WRITE TEST WORD STRECC . WRITE EXPECTED ECC CODE COPY 0(X),A READ TEST WORD  CSK A,K COMPARE TO EXPECTED DATA NOP JMP R0016 CONTINUE LOOKING FOR ERROR JMP FERROR ERROR FOUND TITL SPACE 2 TRAP3 ENT COPY K,A SAVE EXPECTED TEST WORD  JEQ A,T003 IS TEST WORD 0'S OR F'S JMP NERROR2 F'S, CONTINUE TESTING T003 JMP NERROR3 0'S, CONTINUE TESTING * * NO ERROR IN TEST WORD * TEST ECC CODE * SPACE 1 NERROR EQU $ COPY X,Q SAVE MEMORY LOCATION COPY =:88,X -- SET THIRD TRAP COPY TRAPADD4,A -- SERVICE ROUTINE  COPY A,3(X) -- COPY Q,X RESTORE MEMORY LOCATION COPY =6,A SET COUNTER COPY A,COUNT6 STORE COUNTER COPY K,A JEQ A,NERROR1 IS TEST WORD EQUAL TO 0'S OR F'S C; OPY =:FFFF,A RBIT 1,S RESET OV TITL SPACE 2 NERROR2 EQU $ ROTATE A,LO,1 ROTATE LEFT ECC CODE COPY A,ECOD1 SAVE ECC CODE COPY COUNT6,A SUB =1,A  UP DATE COUNTER COPY A,COUNT6 STORE COUNTER JNE A,NERROR4 RESUME TESTING IF ZERO, ERROR NOT FOUND RTEST1 JMP RTEST CONTINUE TESTING NERROR4 COPY ECOD1,A RESTORE ECC CODE COPY =:FFFF,Q SET TEST WORD COPY Q,0(X) WRITE TO TEST MEMORY STRECC . WRITE ECC CODE COPY 0(X),Q READ TEST WORD CSK Q,K COMPARE TO EXPECTED TEST WORD NOP JMP NERROR2  ERROR NOT FOUND TRY AGAIN JMP FERROR1 FOUND ERROR **** ECOD1 WORD :0 SSCHK24 ENT JST SSCHK22 JMP *SSCHK24 TITL SPACE 2 NERROR1 EQU $ SBIT 1,S SET OV NERROR3 EQU $ ROTATE A,LO,1 ROTATE LEFT ECC CODE COPY A,ECOD1 SAVE ECC CODE COPY COUNT6,A SUB =1,A UP DATE COUNTER COPY A,COUNT6 STORE COUNTER JNE A,NERROR5 RESUME TESTING IF ZERO, ERROR NOT FOUND JMP RTEST1 CONTINUE TESTING **** *** COUNT6 WORD :0 **** NERROR5 COPY ECOD1,A RESTOPRE ECC CODE COPY =0,Q SET TEST WORD COPY Q,0(X) WRITE TO TEST MEMORY STRECC .  WRITE ECC CODE COPY 0(X),Q READ TEST WORD CSK Q,K COMPARE TO EXPECTED TEST WORD  NOP JMP NERROR3 ERROR NOT FOUND TRY AGAIN JMP FERROR1 FOUND ERR0R TITL ERROR FOUND (TEST B) * * FOUND ERROR IN ECC CODE * FERROR1 EQU $ XOR =:FFE0,A SET ECC CODE FOR READING COPY A,Q SAVE ECC CODE SPACE 2 * * FOUND ERROR IN DATA REGISTER * FERROR EQU  $ COPY K,A JEQ A,DERROR1 TEST FOR 0'S OR F'S COMP Q,Q F'S ; COMPLEMENT REGISTER DERROR1 SELP Q,4 PRESENT BIT ERROR TO DATA REGISTER COPY MEMREF1,A PHYSICAL ADDRESS  HLT **** **** * WITH MMU CACHE SWITCH FORCED ON ECC CODE FAILS * Q = BIT ERROR * A = PHYSICAL ADDRESS, X = LOGICAL ADDRESS * TO RESUME TESTING PUSH RUN * FOR ECC CODE BIT ERROR THE UPPER BYTE WILL BE FFXX * BITS 0 THRU 4 ARE ECC CODE BITS **** SPACE 1 JMP RTEST1 RESUME TESTING  TITL RELOCATION ROUTINES -- FIRST 64K (TEST B) ***** * * RELOCATION ROUTINES * ***** REL000 EQU $  COPY LOLIM2A,A LOAD A WITH LOW MEMORY-TESTING LIMIT JNE A,$+2 JUMP IF PAT NOT RELOCATED  JMP REL200 PAT RELOCATED -- RESTORE TO LOW MEMORY COPY DMAND2,A GET PAT MODE SELECT WORD 2 AND =1,A TEST BIT 0 JEQ A,$+2 BIT IS RESET -- RELOCATE PAT JMP RELB000 BIT IS SET -- DO NOT RELOCATE PAT -- EXIT SPACE 2 * * SET UP ADDRESS FOR RELOCATED TESTING < * COPY =0,A COPY A,LOLIMX2 -- SET LOW MEMORY COPY A,LOLIM2A -- TESTING LIMIT  COPY =:7FFF,A COPY A,HILIMX2 SET HIGH MEMORY-TESTING LIMIT COPY ADD1A,A --  COPY A,TRAPADD1 -- COPY ADD2A,A -- SET UP COPY A,TRAPADD2 -- TRAP SERVICE COPY ADD3A,A -- LOCATION COPY A,TRAPADD3 -- IN MEMORY COPY ADD4A,A -- COPY A,TRAPADD4 -- * TITL * * RELOCATE PAT TO HIGH MEMORY * REL100 COPY =0,X INITIALIZE SOURCE ADDRESS  COPY =:8000,Y INITIALIZE DESTINATION ADDRESS COPY Y,L SET SOURCE ADDRESS LIMIT REL110 COPY 0(X),A READ FROM SOURCE AREA COPY A,0(Y) WRITE TO DESTINATION AREA ADD =1,X INCREMENT SOURCE ADDRESS ADD =1,Y INCREMENT DESTINATION ADDRESS CSK X,L SOURCE ADDRESS AT LIMIT ?  JMP REL110 NO, CONTINUE JMP REL110 NO, CONTINUE * * VERIFY * REL120 COPY =0,X  INITIALIZE SOURCE ADDRESS COPY =:8000,Y INITIALIZE DESTINATION ADDRESS REL130 COPY 0(X),A READ FROM SOURCE AREA COPY A,K SAVE IN K COPY 0(Y),Q READ FROM DESTINATION AREA CSK Q,K COMPARE SOURCE DATA WITH DESTINATION DATA NOP JMP REL140 ERROR ADD =1,X  DATA OK -- INCREMENT SOURCE ADDRESS ADD =1,Y INCREMENT DESTINATION ADDRESS CSK X,L SOURCE ADDRESS AT LIMIT ? JMP REL130 NO,CONTINUE JMP REL130 NO,CONTINUE JMP REL150 YES,EXIT REL140 HLT PROGRAM COPY VERIFY ERROR * K = SOURCE DATA , Q = DESTINATION DATA * X = SOURCE ADDRESS , Y = DESTINATION ADDRESS SPACE 1 JMP REL100 RESTART PROGRAM COPY TITL * * PREPARE TO JUMP TO RELOCATED PROGRAM * REL150 EQU $ COPY =:84,X UNIMPLELEMTED INSTRUCTION TRAP LOCATION COPY UIT2PT2,A UIT SERVICE ROUTINE ADDRESS COPY A,3(X) STORE AT WIT LOCATION (:87) COPY =:BF80,A 'JST *$+1' INSTRUCTION COPY A,6(X) STORE AT MEMORY EXCEPTION TRAP LOC. (:8A) COPY MET2PT2,A MET SERVICE ROUTINE ADDRESS COPY A,7(X) STORE AT MEM LOCATION (8B) * COPY MEMSZ3,A MEMORY SIZE IN 64K INCREMENTS SHIFT A,L,8 MOVE TO UPPER BYTE  OR =:B,A OR IN MEMORY TEST CODE SBIT 15,A SET PAT RELOCATION INDICATOR SELP A,4 OUTPUT TO CONSOLE DISPLAY RBIT 8,S DISABLE INTERREUPTS JMP *$+1 JUMP INTO RELOCATED PAT WORD F64000+:8000 TITL * * DATA STORAGE AND POINTERS * SENSW22 RES 1,0  SENSE SWITCH STATE AT MEMORY TEST ENTRY MEMSZ3 RES 1,0 MEMORY SIZE IN 64K INCREMENTS LOLIM2A RES 1,0  LOW MEMORY - TESTING LIMIT UIT2PT2 WORD UIT22+:8000 ADDRESS OF RELOCATED UIT SERVICE ROUTINE MET2PT2 WORD MET22= +:8000 ADDRESS OF RELOCATED MET SERVICE ROUTINE ADD1A WORD BERROR1+:8000 ADDRESS OF RELOCATED TRAP SERVICE ROUTINE ADD2A WORD BERROR2+:8000 ADDRESS OF RELOCATED TRAP SERVICE ROUTINE ADD3A WORD TRAP2+:8000 ADDRESS OF RELOCATED TRAP SERVICE ROUTINE ADD4A WORD TRAP3+:8000 ADDRESS OF RELOCATED TRAP SERVICE ROUTINE LPOOL TITL * * RELOCATE PAT BACK TO LOW MEMORY * REL200 JST RESTORB MOVE PAT BACK TO LOW MEMORY IN 4,A INPUT CONSOLE DISPLAY RBIT 15,A RESET PAT RELOCATION INDICATOR SELP A,4 OUTPUT TO CONSOLE DISPLAY SIN 1 INHIBIT INTERRUPTS SBIT 8,S ENABLE INTERRUPTS JMP  *$+1 -- JUMP BACK TO PAT IN LOW MEMORY AND WORD RELB000 -- EXIT 1ST 64K TEST * * ORDERLY EXIT FROM MIDDLE OF MEOORY TEST * REL300 COPY LOLIM2A,A GET LOW MEMORY-TESTING LIMIT JNE A,REL310 JUMP IF PROGRAM NOT RELOCATED JST RESTORB PROGRAM RELOCATED -- RESTORE TO LOW MEMORY SIN 1 INHIBIT INTERRUPTS SBIT 8,S ENABLE INTERRUPTS REL310 JMP *$+1 EXIT MEMORY TEST (JUMP BACK TO LOW MEMORY) WORD M90000 * * CHECK SENSE SWITCH AND BLINK DISPLAY (SEE SSCHK0) * SSCHK22 ENT COPY =0,Q CLEAR Q JF SS,$+2 -- COPY SENSE SWITCH COPY =1,Q -- TO Q XOR SENSW22,Q XOR WITH PREVIOUS SENSE SWITCH CONTENTS JNE Q,REL300 JUMP IF SENSE SDWITCH CHANGED IN 4,Q INPUT CONSOLE DISPLAY COPY MEMSZ3,Y LOAD Y WITH MEMORY SIZE SHIFT Y,L,8 MOVE TO UPPER BYTE XOR Y,Q COMPLEMENT MEMORY SIZE INDICATOR BITS SELP Q,4 OUTPUT TO CONSOLE DISPLAY JMP *SSCHK22 RETURN TITL * * ROUTINE TO MOVE PAT FROM HIGH MEMORY BACK TO LOW MEMORY * RESTORB ENT COPY  =:8000,X INITIALIZE SOURCE ADDRESS COPY X,LOLIM2A INITIALIZE LOW MEMORY LIMIT COPY =0,Y INITIALIZE DESTINATION ADDRESS COPY Y,L SET SOURCE ADDRESS LIMIT RESTOR4 COPY 0(X),A READ FROM SOURCE AREA  COPY A,0(Y) WRITE TO DESTINATION AREA ADD =1,Y INCREMENT DESTINATION ADDRESS ADD =1,X INCREMENT SOURCE ADDRESS CSK X,L SOURCE ADDRESS AT LIMIT ? JMP RESTOR4  NO, CONTI_UE JMP RESTOR4 NO, CONTINUE * * VERIFY * COPY =:8000,X INITIALIZE SOURCE ADDRESS COPY =0,Y INITIALIZE DESTINATION ADDRESS RESTOR5 COPY 0(X),A READ FROM SOURCE AREA  COPY A,K SAVE IN K COPY 0(Y),Q READ FROM DESTINATION AREA CSK Q,K  COMPARE SOURCE DATA WITH DESTINATION DATA NOP JMP RESTOR6 ERROR ADD =1,X DATA OK -- INCREMENT SOURCE ADDRESS ADD =1,Y INCREMENT DESTINATION ADDRESS CSK X,L SOURCE ADDRESS AT LIMIT ? JMP RESTOR5 NO, CONTINUE JMP RESTOR5 NO, CONTINUE JMP >  *RESTORB YES,RETURN RESTOR6 HLT PROGRAM COPY VERIFY ERROR * K = SOURCE DATA , Q = DESTINATION DATA * X = SOURCE ADDRESS , Y = DESTINATION ADDRESS JMP RESTORB+1 RESTART PROGRAM COPY TITL * *  UNEXPECTED UNIMPLEMENTED INSTRUCTION TRAP SERVICE ROUTINE * UIT22 EQU $ JST LIGHT22 HLT  HUNEXPECTED UIT JMP MET32 * * UNEXPECTED MEMORY EXCEPTION TRAP * MET22 ENT JST  LIGHT22 SST 2 JMP $+3 HLT UNEXPECTED TRANSLATE TABLE PARITY ERROR  JMP MET32 SST 3 JMP $+3 HLT UNEXPECTED UNINSTALLED MEMORY TRAP JMP MET32 SST 4 JMP $+3 HLT UNEXPECTED ACCESS ERROR  JMP MET32 HLT UNDEFINED MEMORY EXCEPTION TRAP MET32 JST RESTORB RESTORE PAT TO LOW MEMORY JMP *$+1 RESTART MEMORY TEST WORD INIT20 * LIGHT22 ENT ROUTINE TO INSERT :AAXX IN CONSOLE DISPLAY IN 4,A INPUT CONSOLE DISPLAY AND =:00FF,A MASK OFF UPPER BYTE OR DAA00,A INSERT :AA00 INTO UPPER BYTE SELP A,4 OUTPUT TO CONSOLE DISPLAY JMP *LIGHT22 RETURN DAA00 WORD :AA00 TITL RELB000 EQU $ JMP AF6400A LOLIM12 RES 1,0 LOW MEMORY - TESTING LIMIT HILIM02 RES 1,0 HIGH MEMORY - TESTING LIMIT LPOOL  TITL ABOVE 1ST 64K TESTING (TEST B) ********** * * ABOVE 1ST 64K TESTING * * THESE SECTIONS TEST ALL MEMORY EXCEPT THE 1ST 64K * IN THE SYSTEM. * * EACH SECTION TESTS MEMORY IN 64K BLOCKS. ACCESS OF * TEST MEMORY IS DONE VIA THE LOGICAL ADDRESS SPACE * :8000-:FFFF USING THE TRANSLATE TABLE IN THE MMU. * TWO MAPS ARE USED AT A TIME. THE UPPER HALVES OF * THE SYSTEM MAP AND USER MAP 1 POINT TO THE FIRST * HALF AND THE SECOND HALF RESPECTIVELY OF THE CURRENT * 64K MEMORY BLOCK UNDER TEST. * *********** AF6400A EQU $ COPY MEMSZ3,A GET MEMORY SIZE CSK A,=2 MEMORY > 64K ? JMP M80000 NO,SKIP ABOVE 64K TESTING  NOP COPY =1,A OUT A,6 INITIALIZE USER MAP NUMBER TITL DOUBLE BIT ERROR -- ABOVE 1ST 64K TESTING (TEST B) AF64000 EQU $ JST INIT2 INITIALIZE TRANSLATE TABLE COPY =1,A INITIALIZE HIGH ORDER PHYSICAL ADDRESS * AF64010 RBIT 10,S SET STATUS TO SYSTEM MAP COPY A,L SAVE A IN L COPY A,MEMREF SAVE A IN MEMREF COPY A,MEMREF1 STORE MEMREF COPY =:0,A  COPY A,MEMLIM SET HIGH MEMORY TESTING LIMIT AF64020 EQU $ COPY =:8000,X INITIALIZE LOGICAL ADDRESS JST F64020 TEST MEMORY TBIT 10,S JT OV,AF64030 STATUS TO SYSTEM MAP ON SBIT 10,S NO,SET STATUS TO SYSTEM MAP JMP AF64020 CONTINUE TESTING AF64030 ? EQU $ RBIT 10,S JST INCTB2 COPY L,A HIGH ORDER PHYSICAL ADDRESS ADD =1,A CSK A,MEMSZ3 COMPARE MEMORY LIMITS NOP JMP $+2 CONTINUE TESTING JMP M90000 END JUMP OUT OF MEMORY TEST COPY A,L COPY A,MEMREF JMP AF64010 TITL MEMORY DIAGNOSTIC (TEST A AND TEST B) END * M80000 EQU $ M90000 EQU $ COPY =:88,X MEMORY EXCEPTION TRAP LOCATION COPY TEMPME,A GET ME TRAP SERVICE ADDRESS COPY A,3(X) RESTORE ME TRAP LOCATION COPY =:5C35,A COPY A,2(X) STORE SCNTX IN 3RD WORD OF TRAP JMP PART8ST EXIT MEMORY TEST LPOOL *  RES $;:1F-$&:1F+1,0 PART8ST SET $ SAVE END COPY A,MEMREF JMP AF64010 TITL MEMORY DIAGNOSTIC (TEST A AND TEST B) END * M80000 EQU $ M90000 EQU $ COPY =:88,X MEMORY EXCEPTION TRAP LOCATION COPY TEMPME,A GET ME TRAP SERVICE ADDRESS COPY A,3(X) RESTORE ME TRAP LOCATION COPY =:5C35,A COPY A,2(X) STORE SCNTX IN 3RD WORD OF TRAP JMP PART8ST EXIT MEMORY TEST LPOOL *  SPACE 9 * * PPPPPP AAA TTTTTTTT 444 999 5555555 * PP PP AA AA TT 44444  999 999 55 * PP PP AA AA TT 44 44 999 999 55 * PPPPPP AAAAAAAAA TT 4444444  99999999 555555 * PP AA AA TT 44 999 555 * PP AA AA TT  44 999 555 * PP AA AA TT 44 999 55555 * * U S E R S G U I D E * * N A K E D M I N I 4 / 9 5 * P R O C E S S O R A C C E P T A N C E T E S T * * 8 4 - 9 3 8 1 4 - 0 0 C 0 0 0 * * N O V E M B E R 1 9 8 1 * TITL NAKED MINI 4/95 PROCESSOR ACCEPTANCE TEST (PAT495) 84-93814-00 TITL TABLE OF CONTENTS * SECTION 1 INTRODUCTION............................................6 * * SECTION 2 FUNCTIONAL DESCRIPTION..................................6 * * 2.1 HARDWARE REQUIRED..................................6 * * 2.2 SOFTWARY REQUIRED..................................6 * * 2.3 ADDITIONAL HARDWARE SUPPORTED......................6 * * SECTION 3  REFERENCE DOCUMENTATION.................................7 * * SECTION 4 GENERAL DESCRIPTION.....................................7 * * SECTION 5 PROGRAM OPERATION.......................................8 * * 5.1 LOADING AND START UP...............................8 * * 5.1.1 DEFAULT MODE -- ADDR=:100...................8 * 5.1.2 DEMAND MODE -- ADDR=:101...................8 * 5.1.3 RESTART MODE -- ADDR=:102...................9 * *  5.2 RUN INDICATION.....................................9 * * 5.3 TERMINATION.......................................10 * * 5.3.1 NORMAL TERMINATION.........................10 * 5.3.2 ERROR TERMINATION..........................10 * * 5.4 CONSOLE INTERRUPT TESTING.........................10 * * 5.5 POWER F@ AIL/POWER UP TESTING.......................10 * * 5.6 UNEXPECTED TRAPS..................................11 * * * SECTION 6 TEST DESCRIPTIONS......................................11 * * 6.1 TEST 1, BASIC INSTRUCTION DIAG (BIDP).............11 * * 6.1.1 BASIC INSTR. TESTING.......................12 * 6.1.2 SINGLE WORD MEM. REF. TESTING..............12 * 6.1.3 REGISTER TO REGISTER TESTING...............12 * 6.1.4 SHIFT/ROTATE & BIT MANIPULATION............12 * 6.1.5 IMMEDIATE LITERAL TESTING..................13 *  6.1.6 CONDITIONAL JUMP TESTING...................13 * 6.1.7 MULTIPLE WORD MEM.REF.TESTING..............13 * 6.1.8 STACK TESTING..............................13 * 6.1.9 TRAP EMULATION TESTING.....................13 * * 6.2 TEST 2, UNIMPLEMENTED INSTR. TEST (UIT)...........14 * * 6.3 TEST 3, REAL-TIME CLOCK TEST (RTC)................14 * * 6.4 TEST 4, INPUT/OUTPUT TEST (IOT)...................15 * *  6.5 TEST 5, FLOATING POINT TEST (FLPT)................15 * * 6.6 TEST 6, 4/95 NEW INSTR. TEST (NIDP)...............16 * * 6.6.1 DOUBLE WORD STACK RELATIVE INSTRUCTIONS....16 * 6.6.2 CONTEXT SWITCH INSTRUCTIONS TESTING........16 * 6.6.3 PROCEDURE ENTER & RETURN INSTR. TESTING....16 * 6.6.4 DOUBLE PRECISION ARITHMETIC INSTR. TEST....16 * 6.6.5 QUEUE INSTRUCTION TESTING..................17 *  6.6.6 BIT MANIPULATION INSTR. TESTING............17 * 6.6.7 SINGLE REG. PUSH & POP INSTR. TESTING......17 * 6.6.8 SEMAPHORE INSTRUCTION TESTING..............17 * 6.6.9 BLOCK MOVE WORD INSTRUCTION TEST...........17 * 6.6.10 ECC INSTRUCTIONS TESTING...................17 * 6.6.11 SINGLE WORD STACK RELATIVE INSTR. TEST.....18 * * 6.7 TEST 7, MMU MEMORY CHECK & * MEMORY MANAGEMENT UNIT TEST (MMU).................18 * * 6.7.1 MMU MEMORY CHECK...........................18 * * 6.7.2 MEMORY MANAGEMENT UNIT TEST (MMU)..........18 * * 6.7.2.1 MMU REGISTER TEST.......................19 *  6.7.2.2 TRANSLATION TABLE ACCESS BIT TEST.......19 * 6.7.2.3 MEMORY TEST OF TRANSLATION TABLE........19 * 6.7.2.4 TRANSLATION & ACCESS MODES TESTING......19 * 6.7.2.5 LOOK AHEAD LATCH TEST...................21 * 6.7.2.6 MULTIPLE MAP DMA TRANSFER TEST..........21 * * 6.8 TEST 8, CACHE TEST (CACHE)........................21 * * 6.8.1 CACHE HITS ENABLE BIT TEST................21 *  6.8.2 RESTRICTED CACHE HITS ENABLE BIT TEST.....22 * 6.8.3 UPDATE AND HIT RULES TESTING..............22 * * 6.9 TEST 9, PRIVILEGED OPERATION TRAP & * STRU/LODU INSTR. TESTS (PRIV).............22 * * 6.9.1 COPY TO/FROM USER SPACE TEST..............22 * 6.9.2 PRIVILEGED OPERATIONA  TRAP TEST............22 * 6.9.3 SYSTEM STACK EXCEPTION TRAP TEST..........22 * * 6.10 TEST A, LONG MEM TEST (W/ECC) (ECCL).............23 * * 6.10.1 FUNCTIONAL/ORGANIZATIONAL DESCRIPTION....23 * *  6.10.2 INDIVIDUAL TEST DESCRIPTIONS.............24 * * 6.10.3 ERROR HALTS..............................25 * * 6.10.4 PROGRAM RELOCATION.......................26 * * 6.11 TEST B, SHORT MEM TEST (W/ECC) (ECCS)............26 * * 6.11.1 INDIVIDUAL TEST DESCRIPTIONS.............26 * * 6.12 TEST C, AUTOLOAD TEST (ALT)......................27 * * SECTION 7 OPERATION SUMMARY......................................28 * *  7.1 DEFAULT MODE......................................28 * * 7.2 DEMAND MODE.......................................28 * * 7.3 RESTART MODE......................................29 * * 7.4 AUTOLOAD TEST.....................................29 * * * APPENDICES * * APPENDIX A LINK MAP DESCRIPTION...................30 * * APPENDIX B MOVE UTILITY...........................31 * * APPENDIX C REVISION DESCRIPTION...................32 * TITL * PAT495 USERS GUIDE * SECTION 1. INTRODUCTION * * THE NAKED MINI 4/95 PROCESSOR ACCEPTANCE TEST PROGRAM VERIFIES * THE OPERATIONAL CAPABILITY OF THE NM4/95 COMPUTER BY MEANS OF * TESTS THAT CHECK FOR: * * 1. COMPLETE INSTRUCTION REPERTOIRE, * 2. MEMORY INTEGRITY, AND * 3. PROCESSOR FEATURES (POWER FAIL, REAL-TIME CLOCK, * AUTOLOAD, CONSOLE INTERRUPT, TRAPS). * 4. MEMORY MANAGEMENT UNIT & CACHE INTEGRITY * *  SECTION 2. ENVIRONMENT * * THE MINIMUM HARDWARE AND SOFTWARE REQUIREMENTS TO RUN THIS * PROGRAM ARE LISTED IN THIS SUBSECTION. * * 2.1 HARDWARE REQUIRED * * THE FOLLOWING HARDWARE IS REQUIRED: * *NM4/95 PROCESSOR WITH PIGGYBACK CARD & PROGRAMMERS CONSOLE * *FLOPPY DISK DRIVE FOR PROGRAM LOADING * *I/O TEST MODULE (REQUIRED ONLY FOR TEST 4) * *MEMORY (MUST BE 64K MINIMUM) * 2.2 SOFTWARE REQUIRED * * PAT495 ON FLOPPY DISKETTE (84-93814-04) * **NOTE** 'PAT495.BIN' IS RENAMED 'OS::.SYS' ON THE FLOPPY SO THAT * THE PROGRAM MAY BE AUTOLOADED WITHOUT AN OPERATING SYSTEM. * * 2.3 ADDITIONAL HARDWARE SUPPORTED * * THE FOLLOWING HARDWARE IS OPTIONAL. * *ADDITIONAL MEMORY, UP TO 4M * *ASR-33 TTY OR EQUIVALENT (TO USE DEBUG4) * * SECTION 3. REFERENCE DOCUMENTATION * * REFER TO THE FOLLOWING DOCUMENTS FOR SUPPLEMENTARY INFORMATION. * *  *NAKED MINI 4 ASSEMBLERS USERS MANUAL 90-93500-01 * *ENGINEERING SPEC, MEMORY MANAGEMENT UNIT, 76-53794-01 * *ENGINEERING SPEC, PI SERIES CPU, 76-20797-00 * * SECTION 4. GENERAL DESCRIPTION * * PAT495 IS COMPRISED OF NINE PARTS ASSEMBLED IN ONE PART (THIS * ELIMINATES THE NEED TO USE A LINK MAP TO DETERMINE LABEL * LOCATIONS IN MEMORY FOR PARTS TWO THRU NINE). * * FILE NAME CONTENTS * ------------------------------------------------------------- * PAT495P1 .ASM TEST 1 BASIC INSTRUCTION DIAGNOSTIC (BIDP) * PAT495P2 .ASM TEST 2 UNIMPLEMENTED INSTRUCTION TEST (UIT) * TEST 3B  REAL-TIME CLOCK TEST (RTC) * TEST 4 INPUT/OUTPUT TEST (IOT) * PAT495P3 .ASM TEST 5 FLOATING POINT INSTRUCTION TEST (FLPT) * PAT495P4 .ASM TEST 6 NM4/95 NEW INSTRUCTION DIAGNOSTIC (NIDP) * PAT495P5 .ASM TEST 7 MEMORY MANAGEMENT UNIT TEST (MMU) * TEST 8 CACHE TEST (CACHE) * PAT495P6 .ASM TEST 9 PRIVILEGED OPERATION TRAP TEST, * STRU/LODU INSTRUCTION TESTS & * SYSTEM STACK EXCEPTION TRAP TEST (PRIV) * PAT495P7 .ASM TEST A LONG MEMORY TEST (WITH ECC) (ECCL) * TEST B SHORT MEMORY TEST (WITH ECC) (ECCS) * PAT495P8 .ASM TEST C AUTOLOAD TEST (ALT) * PAT495P9 .ASM DEBUG4 UTILITY PROGRAM MODIFIED FOR PAT495 * * PAT495 INCLUDES THE UTILITY PROGRAM - DEBUG4 - TO ALLOW THE USER * TO INSPECT, PRINT, AND MODIFY ANY MEMORY LOCATION. REFER TO * THE MEMORY LINK MAP FOR THE STARTING LOCATION OF DEBUG4. * * SECTION 5. PROGRAM OPERATION * * 5.1 LOADING AND START UP * * PAT495 LOADS & HALTS AT LOC. :100. HERE, THE A-REG MUST BE LOADED * FOR DEFAULT MODE; THE A-REG, DATA-REG, & THE P-REG MUST BE LOADED * FOR BOTH DEMAND AND RESTART MODES. THREE NORMAL HALTS WILL FOLLOW. * * 5.1.1 DEFAULT MODE -- ADDRESS :100 * * THE PAT495 PROGRAM IS SUPPLIED AS AN AUTOLOADABLE FLOPPY DISK. * PAT495 CAN BE STARTED AT LOCATION :100. AT THIS LOCATION, TESTS * 1,2,3,5,6,7,8,9,A & B ARE EXECUTED CONTINUOUSLY. REFER TO 5.1.2 * FOR A REGISTER RUN OPTIONS (THESE MUST BE SPECIFIED). * TEST 4 (IOT) EXECUTES IF THE I/O TEST CARD IS PRESENT. * * 5.1.2 DEMAND MODE -- ADDRESS :101 * * THE PROGRAM CAN BE STARTED AT LOCATION :101 IF SPECIFIC TESTS OR RUN * OPTIONS ARE DESIRED. ENTER THE FOLLOWING INFORMATION IN THE CONSOLE * DATA REGISTER AT THIS ADDRESS. * * CONSOLE DATA REG. BIT HEX 1= * ------------------------ ----- ----------- * 0 :0001 NOT USED * 1 :0002 RUN TEST 2 (UIT) * 2  :0004 RUN TEST A (ECCL) * 3 :0008 RUN TEST 3 (RTC) * 4  :0010 RUN TEST 4 (IOT) * 5 :0020 RUN TEST 5 (FLPT) * 6 :0040 RUN TEST 6 (NIDP) * 7 :0080 RUN TEST 7 (MMU) * 8 :0100 RUN TEST 8 (CACHE) * 9 :0200 RUN TEST 9 (PRIV) * 10 :0400 RUN TEST B (ECCS) *  11-15 NOT USED * * TEST 1, BIDP, IS ALWAYS RUN, REGARDLESS OF TEST SELECTION. * TEST C, AUTOLOAD TEST (ALT), CANNOT BE RUN AT ADDRESS :101. REFER * TO SECTION 6.9 FOR TEST C START UP PROCEDURES. * ENTER THE FOLLOWING RUN OPTIONS IN THE A REGISTER AT ADDRESS :101 * * A REGISTER BIT RUN OPTION * ---------------- ----------------------------------------- * 0 1= BYPASS RELOCATION AND LOW MEMORY TESTING * DURING TEST A (ECCL), & TEST B (ECCS). * * 0= RELOCATE PAT495 AND PERFORM LOW MEMORY *  TESTING DURING TESTS A,B. * * 1 1= DO NOT HALT THE PROGRAM IF POWER UP AND * C  DOWN COUNTERS ARE UNEQUAL. (SEC. 5.5) * * 0=HALT IF COUNTERS ARE UNEQUAL. * * 2 0=BYPASS ERROR CORRECTON CODE DIAGNOSTIC * IN TEST 6, AND TEST B. * *  1=RUN ERROR CORRECTION CODE DIAGNOSTIC * IN TEST 6, AND TEST B. * * 3-7 NOT USED, ENTER ZERO * * 8-15 ENTER THE TEST MEMORY SIZE (IN INCREMENTS OF * 64K) AS A BINARY NUMBER. (SYSTEM MEMORY SIZE * IF MMU INSTALLED, 64K IF MMU NOT INSTALLED) * * PRESS RUN AFTER ENTERING A REGISTER AND DATA REGISTER INFORMATION. * PAT495 EXECUTES BIDP AND SELECTED TESTS CONTINUOUSLY. * * 5.1.3 RESTART MODE -- ADDRESS :102 * * PAT495 CAN BE RESTARTED AT LOCATION :102. PASS COUNTERS AND POWER * FAIL COUNTERS REMAIN ACCUMULATIVE AT THIS ADDRESS. ENTER A REGISTER * RUN OPTIONS AND DATA REGISTER TEST SELECTIONS BEFORE RESTARTING * THE PROGRAM AT THIS ADDRESS. * * 5.2 RUN INDICATION * * DURING EXECUTION, THE LOWER NIBBLE (BITS 0-3) OF THE CONSOLE DATA * REGISTER NORMALLY DISPLAY THE TEST NUMBER. REFER TO THE SPECIFIC * TEST DESCRIPTION FOR DETAILED RUN INDICATION DESCRIPTIONS. * ******NOTE*****THE ERROR CORRECTION LIGHT ON THE 128K MEMORYS * SHOULD BLINK DURING RUNNING OF TESTS 4 AND B. * (I.E. IOT AND ECCS) * NIDP (TEST 6,A & B) MUST FAIL IF THE CACHE IS FORCED ON. * CACHE (TEST 8) MUST FAIL IF THE CACHE IS FORCED * ON OR OFF. CACHE MUST NOT BE FORCED ON DURING ECCL * (TEST A) OR ECCS (TEST B). SWITCH SETTING DOESN'T * MATTER FOR OTHER TESTS. * * 5.3 TERMINATION * * 5.3.1 NORMAL TERMINATION * * PRESS STOP TO TERMINATE PAT495. (DURING TEST A (ECCL), * AND TEST B (ECCS), REVERSE THE STATE OF THE SENSE SWITCH * BEFORE PRESSING STOP.) THE PROGRAM CAN BE SUBSEQUENTLY * RESTARTED AT LOCATION :102. * * 5.3.2 ERROR TERMINATION * * PAT495 HALTS ON ANY ERROR CONDITION. EXAMINE THE P REGISTER AND * REFER TO THE PROGRAM LISTING TO DETERMINE THE CAUSE OF THE ERROR. * * 5.4 CONSOLE INTERRUPT TESTING * * PRESS INT DURING PAT495 EXECUTION TO TEST CONSOLE INTERRUPT * RECOGNITION. THE CONSOLE DATA REGISTER FLASHES AN ALTERNATING * :AAAA/:5555 PATTERN AND THE OV INDICATOR REMAINS ON FOR * APPROXIMATELY THREE SECONDS. IF INT IS PRESSED WHEN INTERRUPTS * ARE DISABLED, THE INT INDICATOR REMAINS LIT UNTIL INTERRUPTS * ARE ENABLED. THE ALTERNATING PATTERN IS DISPLAYED WHEN * THE INTERRUPT IS SERVICED. * 5.5 POWER FAIL/POWER UP TESTING * * ALL VOLATILE REGISTERS AND SIN STATE ARE SAVED AND THE POWER * DOWN COUNT (PDNCT) IS INCREMENTED IF A POWER FAILURE OCCURS. * * WHEN POWER IS RESTORED, THE POWER UP COUNT (PUPCT) IS INCREMENTED, * THE CONTENTS OF VOLATILE REGISTERS ARE RESTORED, AND IF TESTS 1,2, * A, OR B WERE EXECUTING, PROGRAM EXECUTION IS RESUMED AT THE LOCATION * WHERE THE POWER FAILURE OCCURRED. IF TESTS 3,4,5,6,7,8, OR 9 * WERE EXECUTING, PAT495 IS RESUMED AT THE BEGINNING OF BIDP. * * AN ERROR HALT OCCURS IF PDNCT AND PUPCT ARE NOT EQUAL UNLESS THIS * HALT WAS SUPPRESSED (A-REGISTER RUN OPTION BIT 1=1) PRIOR TO PAT495 * EXECUTION. PRESS RUN FOLLOWING THIS ERROR HALT TO RESUME EXECUTION AD T * THE BEGINNING OF BIDP. THE THREE HALTS (SEE SEC. 6.1) ARE BYPASSED. * * 5.6 UNEXPECTED TRAPS * * PAT495 HALTS IMMEDIATELY IF UNEXPECTED MEMORY EXCEPTION, * UNIMPLEMENTED INSTRUCTION, ARITHMETIC ERROR, OR SYSTEM/USER STACK * EXCEPTION TRAPS OCCUR. CONSOLE DATA REGISTER BITS 8-15 DISPLAY * :AA; BITS 0-7 REMAIN UNCHANGED. PRESS RUN TO RESTART PAT495. * BIDP BEGINS EXECUTION, ALTHOUGH THE THREE INITIAL HALTS ARE BYPASSED. * * SECTION 6. TEST DESCRIPTIONS * * 6.1 TEST 1, BASIC INSTRUCTION DIAGNOSTIC (BIDP) * * BIDP EXERCISED ALL BASIC LSI4 NON-I/O INSTRUCTIONS IN THE NAKED MINI * 4 INSTRUCTION REPERTOIRE AND DETERMINES WHETHER EACH INSTRUCTION * PERFORMS AS EXPECTED, ALTHOUGH IT DOES NOT CHECK THE EFFECTS OF * INSTRUCTION EXECUTION ON UNINVOLVED REGISTERS OR MEMORY CELLS. * * DURING BIDP, BITS 0-3 OF THE CONSOLE DATA REGISTER DISPLAY :1. * THIS TEST CAN BE RUN WITHOUT THE PIGGYBACK CARD INSTALLED. * THE TESTING IS CONDUCTED IN THE FOLLOWING ORDER. TITL * 6.1.1 BASIC INSTRUCTION TESTING * * THIS PART OF BIDP VERIFIES BASIC INSTRUCTIONS WHICH ARE REQUIRED * TO EXTENSIVELY TEST REMAINING INSTRUCTIONS. TESTING IS PERFORMED * USING ABSOLUTE DIRECT ADDRESSING, WORD MODE ONLY. * * THREE HALTS OCCUR AT THE BEGINNING OF THIS TEST, DURING THE FIRST * PASS OF BIDP. PRESS RUN AFTER EACH HALT TO CONTINUE PROGRAM * EXECUTION AFTER VERIFYING THE CONSOLE DATA REGISTER CONTENTS. * ALL HALTS AFTER HALT 3 ARE ERROR HALTS. * * HALT ACTION * ---- ------ * HALT 1  CONSOLE DATA REGISTER SHOULD DISPLAY :B300 * HALT 2 CONSOLE DATA REGISTER SHOULD DISPLAY :0117 * HALT 3  CONSOLE DATA REGISTER SHOULD DISPLAY :0023 * * 6.1.2 SINGLE WORD MEMORY REFERENCE TESTING * * SINGLE WORD MEMORY REFERENCE INSTRUCTION TESTING IS PERFORMED * AFTER BASIC INSTRUCTION TESTING. EXTENSIVE TESTING IS PERFORMED * ON COPY AND EXCH IN ALL MEMORY REFERENCE MODES; OTHER INSTRUCTIONS * ARE TESTED LESS EXTENSIVELY. * * 6.1.3 REGISTER TO REGISTER TESTING * * THE COPY INSTRUCTION IS TESTED WITH ALL REGISTER PAIR COMBINATIONS; * OTHER INSTRUCTIONS ARE TESTED WITH ONE REGISTER PAIR. THE OV BIT * IS CHECKED FOLLOWING THE EXECUTION OF NEG, ADD, OR SUB INSTRUCTION. * * 6.1.4 SHIFT/ROTATE AND BIT MANIPULATION TEST * * SINGLE REGISTER SHIFT/ROTATES ARE TESTED WITH ALL REGISTERS. ALL * SHIFT COUNTS (1-16) ARE TESTED WITH THE AREG. DOUBLE REGISTER * SHIFTS/ROTATES ARE TESTED WITH REGISTER PAIRS AQ, AX, AND AY. * * BIT MANIPULATION INSTRUCTION SBIT IS TESTED ON REGISTER BITS 0-15; * ALL OTHER BIT MANIPULATION INSTRUCTIONS ARE TESTED ON ONE BIT ONLY. * * 6.1.5 IMMEDIATE LITERAL TESTING * * EACH INSTRUCTION IS TESTED WITH ONE REGISTER. THE OV BIT IS CHECKED * FOLLOWING THE EXECUTION OF AN ADD OR SUB INSTRUCTION. * * 6.1.6 CONDITIONAL JUMP TESTING * * EACH CONDITION WHICH CAUSES OR DOES NOT CAUSE A JUMP IS VERIFIED. * * 6.1.7 MULTIPLE WORD MEMORY REFERENCE TESTING * * ALL MEMORY REFERENCE MODES AARE CHECKED ON THE ADDC INSTRUCTION; * OTHER INSTRUCTIONS ARE TESTED LESS EXTENSIVELY. THE OV BIT IS * CHECKED FOLLOWING EXECUTION OF AN ADDE, SUBE, IMSE, OR DMSE * INSTRUCTION; THE OV AND CY BITS ARE CHECKED FOLLOWING EXECUTION * OF AN ADDC OF SUBC INSTRUCTION. MUL AND DIV ARE TESTED FOR THE * FOUR COMBINATIONS OE F POSITIVE AND NEGATIVE ARGUMENTS. ARITHMEIC * EXCEPTION TRAPS AND STACK EXCEPTION TRAPS (JSKE) ARE ALSO TESTED. * * 6.1.8 STACK TESTING * * INSTRUCTIONS ARE TESTED ON ALL ASPECTS OF CORRECT OPERATION. * STACK OVERFLOW TRAP OPERATION IS VERIFIED FOR JSK AND PUSH. * REGISTER EFFECTS ARE CHECKED FOR PUSH AND POP. * * 6.1.9 TRAP EMULATION TESTING * * STRAP AND UTRAP INSTRUCTIONS ARE VERIFIED FOR PROPER OPERATION. * EACH PASS OF BIDP TESTS EACH OF THE ABOVE GROUPS 64 TIMES. * TITL * 6.2 TEST 2, UNIMPLEMENTED INSTRUCTION TEST (UIT) * * IN THIS TEST, ALL UNIMPLEMENTED INSTRUCTIONS ARE EXECUTED TO VERIFY * THE OPERATION OF THE UNIMPLEMENTED INSTRUCTION TRAP. * * DURING UIT, BITS 0-3 OF THE CONSOLE DATA REGISTER DISPLAY :2 AND * BITS 8-15 DISPLAY THE UPPER 8 BITS OF THE UNIMPLEMENTED INSTRUCTION * CURRENTLY BEING TESTED. * * 6.3 TEST 3, REAL-TIME CLOCK TEST (RTC) * * RTC VERIFIES THAT THE REAL-TIME CLOCK CAN GENERATE TIMING ('TICK') * INTERRUPTS AND CHECKS THAT RTC INTERRUPTS OCCUR WHEN THE INCREMENT * LOCATION COUNT REACHES ZERO. RTC MONITORS LOCATION :91 UNTIL THE * COUNT REACHES ZERO. * * AN ERROR HALT OCCURS UNDER ANY OF THE FOLLOWING CONDITIONS: * * 1. THE TIMING LOOP EXPIRES BEFORE A TIMING INTERRUPT ('TICK') * OCCURS. * 2. INCREMENT LOCATION :91 IS INCREMENTED BY A VALUE OTHER * THAN 1. * 3. A RTC INTERRUPT IS NOT TAKEN WHEN LOCATION :91 IS ZERO. * 4. A RTC INTERRUPT IS TAKEN WHEN LOCATION :91 IS NOT ZERO. * 5. INCREMENT LOCATION :91 IS NOT -1 IMMEDIATELY PRIOR TO THE * RTC INTERRUPT. * * RTC ALSO PERFORMS A REAL-TIME CLOCK CONSISTANCY TEST. THE RTC IS * RUN FOR ABOUT .25 SECOND AND AN AVERAGE 2-TICK SOFTWARE COUNT IS * TAKEN. A +/-6% WINDOW IS CALCULATED ON THIS SOFTWARE COUNT, AND * USED TO DETERMINE THE CONSISTENCY OF THE RTC OVER A 4-SECOND SPAN. * * DURING RTC, BITS 0-3 OF THE CONSOLE DATA REGISTER DISPLAY :3. * DURING THE FIRST PART OF RTC, THE OV INDICATOR BLINKS (ABOUT 2 SEC.), * DURING THE SECOND PART OF RTC, BITS 12-15 OF THE CONSOLE DATA * REGISTER DISPLAY A COUNTER INCREMENTING FROM 0 TO F (ABOUT 4 SEC.). TITL * 6.4 TEST 4, I/O TEST (IOT) * IOT TESTS ALL INPUT/OUTPUT FUNCTIONS OF THE PROCESSOR. IN ADDITION * IT VERIFIES ALL MOTHERBOARD SIGNALS AND FEATURES OF PROCESSOR * OPERATION ASSOCIATED WITH INTERRUPTS. * ********NOTE****** AN I/O TEST MODULE IS REQUIRED FOR THIS TEST. * MBOT FROM THE PROCESSOR MUST BE CONNECTED TO * MBIN OF THE TEST MODULE. * * THE INDIVIDUAL TESTS IN IOT ARE: * 1. DEVICE ADDRESS FUNCTION CODE EXERCISE * 2. PROGRAMMED I/O INSTRUCTION TESTING * 3. I/O CLOCKS TESTING * 4. INTERRUPT INSTRUCTION TESTING * 5. AUTO I/O INSTRUCTION TESTING * 6. INSTRUCTION NON-INTERRUPTABILITY TESTING * 7. DMA TESTING * 8. POWER-FAIL TESTING * * DURING IOT, BITS 0-3 OF THE CONSOLE DATA REGISTER DISPLAY :4. * BITS 8-15 DISPLAY :0F FOR ABOUT .25 SECOND, AND THEN :FF FOR ABOUT * 3.0 SECONDS. (THE TEST LASTS ABOUT 4.0 SECONDS.) * * 6.5 TEST 5, FLOATING POINT INSTRUCTION TEST (FLPT) * * THIS TEST VERIFIES THE CORRECT OPERATION OF THE FLOATING POINT CLASS * OF INSTRUCTIONS, PLUS FIX AND FLOAT (CONSOLE AND CONTROL CLASS). * THE TEST CHECKS FOR CORRECT RESULTS WITH A F WIDE RANGE OF OPERANDS * FOR EACH INSTRUCTION TESTED. THE ADDRESSED MEMORY LOCATIONS AND * THE X AND Y REGISTERS ARE TESTED FOR SIDE EFFECTS. ARITHMETIC * ERROR TRAP OPERATION IS CHECKED. ONLY RELATIVE ADDRESSING MODE * IS TESTED. * * DURING FLPT, BITS 0-3 OF THE CONSOLE DATA REGISTER DISPLAY :5. * TITL * 6.6 TEST 6, 4/95 NEW INSTRUCTION DIAGNOSTIC (NIDP) * * NIDP EXERCISES TESTS ALL NEW NON-I/O INSTRUCTIONS AND DETERMINES * WHETHER EACH INSTRUCTION PERFORMS AS EXPECTED. AS WITH BIDP, NIDP * DOES NOT CHECK THE EFFECTS OF INSTRUCTION EXECUTION ON UNINVOLVED * REGISTERS OR MEMORY CELLS. * * DURING NIDP, BITS 0-3 OF THE CONSOLE DATA REGISTER DISPLAY :6. * * 6.6.1 DOUBLE WORD STACK RELATIVE INSTRUCTION TESTING * * MOST NEW DOUBLE WORD STACK RELATIVE ARE TESTED IN THIS SECTION. * DURING BIDP, EACH OF THESE INSTRUCTIONS WERE TESTED EXTENSIVELY * AND CONFIDENCE HAS BEEN OBTAINED AS TO THEIR FUNCTIONAL OPERATION. * THIS SECTION MAKES SURE THAT THE STACK-RELATIVE FEATURE FUNCTIONS * PROPERLY. ALL ADDRESSING MODES ARE USED WITH THE VARIOUS INSTRUCTIONS. * * 6.6.2 CONTEXT SWITCH INSTRUCTION TESTING * * SCNTX (SAVE CONTEXT) AND LCNTX (LOAD CONTEXT) INSTRUCTIONS ARE * TESTED HERE FOR THEIR ABILITY TO PROPERLY SAVE AND RESTORE THE * VOLATILE REGISTERS WHEN THE CONTEXT POINTER IS BOTH EQUAL AND NOT * EQUAL TO ZERO. * * 6.6.3 PROCEDURE ENTER AND RETURN INSTRUCTION TESTING * * ENTER AND RETURN INSTRUCTIONS ARE TESTED HERE. PROPER OPERATION * IS CHECKED AS WELL AS ALL EFFECTED REGISTERS AND MEMORY LOCATIONS. * * 6.6.4 DOUBLE PRECISION ARITHMETIC TEST * * THIS SECTION TESTS THE FOLLOWING ISNSTRUCTIONS FOR PROPER OPERATION: * CVTDBL (CONVERT TO DOUBLE PRECISION) * DBLADD (DOUBLE PRECISION ADD) * DBLSUB (DOUBLE PRECISION SUBTRACT) * TITL * 6.6.5 QUEUE INSTRUCTION TESTING * * EACH QUEUE INSTRUCTION IS THROUGHLY TESTED ON ALL BOUNDARY * CONDITIONS FOR PROPER OPERATION. THE FOLLOWING INST. ARE TESTED: * ENQUEB (INSERT BEFORE QUEUE ELEMENT) * DEQUEN (REMOVE NEXT QUEUE ELEMENT) * ENQUEA (INSERT AFTER QUEUE ELEMENT) * DELQUE (DELETE THIS QUEUE ELEMENT) * NEXTQUE (POINT TO NEXT QUEUE ELEMENT) * * 6.6.6 BIT MANIPULATION INSTRUCTIONS TESTING * * EACH BIT MANIPULATION INSTRUCTION IS THROUGHLY TESTED ON ALL * BOUNDARY CONDITIONS FOR PROPER OPERATION. * * 6.6.7 SINGLE REGISTER PUSH AND POP INSTRUCTION TESTING * * BOTH INSTRUCTIONS ARE TESTED USING THE FOUR REGISTERS A,Q,X,Y. * * 6.6.8 SEMAPHORE INSTRUCTION TESTING * * THE SEMAPHORE INSTRUCTIONS, SIGNAL AND WAIT, ARE TESTED IN THIS * SECTION FOR PROPER OPERATION. * * 6.6.9 BLOCK MOVE WORD INSTRUCTION TESTING * * THE MOVE INSTRUCTION IS TESTED HERE FOR PROPER OPERATION. * * 6.6.10 ERROR CORRECTION CODE INSTRUCTIONS TESTING * * STRECC, LODECC, AND GENECC INSTRUCTIONS ARE TESTED HERE FOR * PROPER OPERATION. ALL BOUNDARY CONTITIONS ARE CHECKED. * TITL * 6.6.11 SINGLE WORD STACK RELATIVE INSTRUCTION TESTING * * THE SINGLE WORD COPY INSTRUCTION IS TESTED HERE IN STACK RELATIVE * MODE FOR PROPER OPERATION. * * 6.7 TEST 7, MMU MEMORY CHECK & MEMORY MANAGEMENT UNIT TEST (MMU) * * 6.7.1 MMU MEMORY CHECK * * THIS MEMORY TEST IS PLACED BEFORE THE MMU TEST TO VERIFY THE * INTEGRITY OF THE SYSTEM MEMORY (UPPER 48K ONLY). THIS TEST IS * NEG CESSARY SINCE THE MMU TEST MUST BE RUN IN KNOWN GOOD MEMORY. * THE MEMORY CHECK USES THE CHECKERBOARD PATTERN TEST TO VERIFY *  THE INTEGRITY OF THE MEMORY IN WHICH THE MMU DIAGNOSTIC IS RUN. * * A CHECKERBOARD PATTERN IS WRITTEN IN MEMORY; I.E. THE FIRST BLOCK * HAS :AAAA, :5555, :AAAA, .... THE SECOND BLOCK HAS :5555, :AAAA, * :5555, .....ETC. THE PATTERN IS SCANNED STARTING AT THE LOW * END OF TESTABLE MEMORY. AT EACH LCATION, THE DATA IS READ AND * VERIFIED, AND THE COMPLIMENT IS WRITTEN. THE COMPLIMENT PATTERN * IS SCANNED FROM LOW MEMORY. AT EACH LOCATION, THE DATA IS READ * AND VERIFIED AND THE ORIGINAL PATTERN IS WRITTEN. FINALLY THE * SCANNING PROCEDURES ARE REPEATED IN REVERSE STARTING AT THE HIGH * END OF TESTABLE MEMORY. * * THE ROW SIZE ASSUMED IN THE CHECKERBOARD PATTERN IS 64 BITS. THIS * CORRESPONDS TO THE RAM INTERNAL ARRAY ROW SIZE. ALL ONBOARD ROM * MUST BE INSTALLED ABOVE ONBOARD RAM. ANY WRITABLE MEMORY INSTALLED * ABOVE ROM WILL BE IGNORED BY THE MEMORY TEST. * *  DURING MEM, THE CONSOLE DATA REGISTER DISPLAYS THE FOLLOWING: * :0107 WHERE 7 => TEST NUMBER, 1 => MEMORY SIZE (64K) * * 6.7.2 MEMORY MANAGEMENT UNIT TEST (MMU) * * THE MEMORY MANAGEMENT UNIT TEST VERIFIES THE INTEGRITY OF THE MMU * BY EXERCISING ALL REGISTERS, THE TABLE RAM, AND ALL INSTRUCTIONS * ASSOCIATED WITH THE MMU. * * 6.7.2.1 MMU REGISTER TEST * * THE DMA#, USER#, AND CONTROL REGISTERS ARE TESTED TO INSURE THAT * ALL BITS FUNCTION PROPERLY. * * 6.7.2.2 TRANSLATION TABLE ACCESS BIT TEST * * THE FUNCTIONALITY OF THE TABLE ACCESS BIT IS TESTED HERE. MEMORY * FROM :FC00 TO :FFFF IS FILLED WITH THE PATTERN :AAAA. TRANSLATION * ACCESS IS ENABLED AND THE TABLE IS FILLED WITH THE PATTERN :5555. * WHEN TABLE ACCESS IS ENABLED, THE TABLE RESPONDS AS IS MEMORY FROM * :FC00 TO :FFFF. TRANSLATION ACCESS IS THEN DISABLED AND MEMORY * FROM :FC00 TO :FFFF IS VERIFIED FOR THE :AAAA PATTERN. TRANSLATION * ACCESS IS AGAIN RE-ENABLED AND THE TABLE IS VERIFIED FOR THE :5555 * PATTERN. * * 6.7.2.3 MEMORY TEST OF THE TRANSLATION TABLE * * THIS SECTION CHECKS THE INTEGRITY OF EACH BIT OF THE TRANSLATION * TABLE RAM BY ACCESSING EACH TABLE ENTRY AND TESTING IT AS THOUGH IT * IS A MEMORY LOCATION. WALKING 1'S, WALKING 0'S, AND ADDRESS *  PATTERNS ARE WRITTEN INTO EACH TABLE ENTRY AND THEN VERIFIED. * * 6.7.2.4 TRANSLATION AND ACCESS MODES TESTING * * THE FOLLOWING IS DONE IN THIS TEST: * 1) THE TRANSLATION ENABLE BIT IS CHECKED FOR SETTING AND * RESETTING IN THE CONTROL REGISTER. * 2) PAGES ARE SET UP TO TEST THE FOLLOWING ACCESS MODES: * READ/FETCH * READ/WRITE * NOT MAPPED (NO ACCESS) * READ/WRITE/FETCH * 3) NORMAL AND FAULT CONDITIONS ARE TESTED ON EACH PAGE. WITH EACH * FAULT CONDITION, THE LAST P REGISTER IS * VERIFIED FOR CORRECT DATA. ALL ACCESS ERRORS ARE TESTED AND * CHECKED FOR. TRANSLATION TABLE PARITY ERRORS ARE CHECKED FOR * ON EACH ACCESS. * * 6.7.2.5 TRANSLATED ADDRESS LOOK AHEAD LATCH TEST (MMU W/O CACHE ONLY) * * 1) A FOUR WORD LOOP IS EXECUTED WITHIN AND ACCROSS A 1K * PAGE BOUNDARY WITH A LOOP COUNTER IN EACH CASE. THE * COUNTS ARE USED TO FORM A RATIO FOR COMPARISON TO * KNOWN LIMITS. * * 6.7.2.6 MULTIH PLE MAP DMA TRANSFER TEST (I/O MODULE REQUIRED) * * 1) A CHECK IS MADE TO DETERMINE IF THE I/O MODULE IS PRESENT. *  IF THE MODULE IS NOT PRESENT THE TEST IS SKIPPED. * 2) FOUR ONE-WORD DMA TRANSFERS ARE DONE INTO FOUR SEPERATE * USER MAPS (ONE WORD PER MAP). THE TRANSFER IS THEN VERIFIED * BY READING THE PHYSICAL ADDRESS WHERE THE DATA WAS TO BE MAPPED. * THE TRANSFERS ARE DONE ONE AT A TIME, AND TAKE PLACE IN * USER MAPS 1,2,4, AND 8. * * 6.8 CACHE TEST (CACHE) * * THE INTEGRITY OF THE HIGH SPEED CACHE LOGIC ON THE MMU IS VERIFIED * IN THIS TEST. MAPPING MUST BE DISABLED AND THIS TEST MUST RESIDE * IN THE LOWER 16K OF PHYSICAL MEMORY (ADDRESS < :4000). * * 6.8.1 CACHE HITS ENABLE BIT TEST * * THIS TEST VERIFIES THE FUNCTIONALITY OF THE CACHE HITS ENABLE BIT. * THE FOLLOWING IS VERIFIED: * 1) NO HIT SHOULD OCCUR WHEN C=0 AND R=0. *****NOTE**** C => CACHE HITS ENABLE R => RESTRICTED CACHE HITS ENABLE * 2) WITH C=1, A HIT SHOULD OCCUR ONLY AFTER THE SECOND READ OF * A LOCATION. * 3) NO HIT SHOULD OCCUR ON THE FIRST READ TO LOCATION+:400. * 4) HITS SHOULD OCCUR ON THE SECOND READ TO LOCATION+:400. * 5) NO HIT SHOULD OCCUR ON THE NEXT READ TO LOCATION. * PARITY ERRORS IN THE CACHE ARE CHECKED FOR AFTER EACH READ. TITL * 6.8.2 RESTRICTED CACHE HITS ENABLE BIT TEST * * THIS TEST VERIFIES THE FUNCTIONALITY OF THE RESTRICTED CACHE * HITS ENABLE BIT. * THE FOLLOWING IS VERIFIED: * 1) 1K WORDS BELOW :4000 (16K) ARE READ TWICE. * 2) NO HITS SHOULD OCCUR ON THE FIRST READ OF ANY WORD IN * THE 1K BLOCK. * 3) HITS SHOULD OCCUR ON THE SECOND READ OF ANY WORD IN * THE 1K BLOCK. * 4) 1K WORDS ABOVE :4000 ARE READ TWICE. * 5) NO HITS SHOULD OCCUR ON EITHER THE FIRST OR THE SECOND READ * TO ANY WORD IN THE 1K BLOCK ABOVE :4000. * * 6.8.3 UPDATE AND HIT RULES TESTING * * THIS SECTION TESTS TO SEE THAT THE CACHE DOES NOT UPDATE AND WILL * NOT HAVE A HIT IF THE DATA HAS BEEN PREVIOUSLY STORED AS AN ENTRY * IN THE CACHE. THE FOLLOWING CONDITIONS ARE TESTED: * BYTE READS *  ACCESS FAULTS * TABLE ACCESS (READS) * TABLE ACCESS (WRITES) * ECC READS (LODECC) * ECC WRITES (STRECC) TITL * 6.9 PRIVILEGED OPERATION TRAP & STRU/LODU INSTR. TESTS (PRIV) * * 6.9.1 COPY TO/FROM USER SPACE TEST * * THE LODU AND STRU INSTRUCTIONS ARE VERIFIED FOR PROPER OPERATION. * THIS TEST FOLLOWS THE MMU TEST SINCE IT REQUIRES A KNOWN GOOD MMU * FOR PROPER TESTING. * * 6.9.2 PRIVILEGED OPERATION TRAP TEST * * THIS TEST VERIFIES THE PROPER OPERATION OF THE PRIVILEGED OPERATION * TRAP. THE FOLLOWING OPERATIONS ARE TESTED: * 1) ATTEMPTED EXECUTION OF A PRIVILEGED INSTRUCTION WHEN * UP=1 (USER PROTECT BIT IN THE STATUS REGISTER =1). * 2) ATTEMPT TO CHANGE PRIVILEGED BITS IN THE STATUS REGISTER * WHEN UP =1. THE PRIVILEGED BITS ARE AS FOLLOWS: * UP -- USER PROTECT * UM -- USER MAP * RES -- RESERVED BITS * INT -- INTERRUPT ENABLE * RI --- REAL-TIME CLOCK ENABLE * CI --- CONSOLE INTERRUPT ENAI BLE * INTERRUPT LEVEL BITS 12-15 * 3) ATTEMPT TO DISSALLOW INTERRUPTS FOR MORE THAN 64 MICROSECONDS. * THE SIN STATE REGISTER IS ALSO CHECKED FOR PROPER SETTING OF FAULT * FLAGS DURING THE TRAP. * * 6.9.3 SYSTEM STACK EXCEPTION TRAP TEST * * THIS TEST VERIFIES THE PROPER OPERATION OF THE SYSTEM STACK * EXCEPTION TRAP. TITL * 6.10 TEST A, LONG RUNNING MEMORY TEST (ECCL) * * THIS TEST VERIFIES THE INTEGRITY OF THE MEMORIES USED IN THE * LSI-4/95 CONFIGURATION (128K MEMORIES W/ECC). * * SOME SINGLE BIT ERRORS ARE CORRECTED BY THE MEMORY AND ARE INVIS- * IBLE TO THE PROGRAM. THE ERROR CORRECTION LIGHT ON THE BACK OF A * MEMORY WILL BLINK IF THAT MEMORY HAS DETECTED AN ERROR. THE USER * MUST OBSERVE THE LIGHTS ON ALL MEMORIES TO INSURE THAT NO ERRORS * ARE OCCURING DURING THIS TEST. DETECTABLE DOUBLE BIT ERRORS WILL * RESULT IN AN UNINSTALLED MEMORY TRAP. * PAT495 SHOULD NOT BE STOPPED DURING ECCL EXECUTION, AS IT MAY STOP * DURING THE TIME PAT495 IS RELOCATED. PROGRAM RELOADING MAY BE NEC- * ESSARY IF THIS OCCURS. TO ABORT ECCL BEFORE COMPLETION, REVERSE * THE STATE OF THE SENSE SWTICH. THIS WILL CAUSE AN IMMEMIATE AND * ORDERLY EXIT TO THE NEXT TEST IN SEQUENCE. PAT495 MAY BE STOPPED * AT THAT TIME. * * DURING ECCL, BITS 0-7 OF THE CONSOLE DATA REGISTER DISPLAY :0A, * BITS 8-14 DISPLAY THE MEMORY SIZE IN 64K INCREMENTS (FLASHING), * AND BIT 15 WILL DISPLAY 1 WHEN PAT495 IS RELOCATED. * * 6.10.1 FUNCTIONAL/ORGANIZATIONAL DESCRIPTION * * ECCL CONSISTS OF THE FOLLOWING SECTIONS: * * 6.10.1.1 PRELIMINARY ROUTINES * * CONSISTS OF MEMORY SIZE CALCULATION AND 64K ADDRESSABILITY TEST. * *  6.10.1.2 SYSTEM LEVEL TESTING * * CONSISTS OF HIGH ORDER UNIQUE ADDRESS TEST AND TRANSLATE TABLE * ROUTINES. * * 6.10.1.3 FIRST 64K TESTING * * CONSISTS OF LOW ORDER UNIQUE ADDRESS TEST, RAM AND DATA PATH TEST, * BYTE TEST, AND RELOCATION ROUTINES. TESTING IS DONE WITH NO ADDRESS * TRANSLATION (I.E. MMU RESET). * * 6.10.1.4 ABOVE FIRST 64K TESTING * * CONSISTS OF LOW ORDER UNIQUE ADDRESS TEST, RAM AND DATA PATH TEST, * BYTE TEST, AND TRANSLATE TABLE ROUTINES. MEMORY IS TESTED IN 64K * BLOCKS. THIS SECTION IS RUN ONLY IF AN MMU AND MORE THAN 64K OF * MEMORY ARE INSTALLED. * * 6.10.2 INDIVIDUAL TEST DESCRIPTIONS * * 6.10.2.1 64K ADDRESSABILITY TEST * * THIS IS A PRELIMINARY TEST OF ADDRESS BIT 15, AND A TEST OF ADDRESS- * ABILITY TO THE UPPER 32K OF LOGICAL ADDRESS SPACE. * * 6.10.2.2 HIGH ORDER UNIQUE ADDRESS TEST * * THIS TEST WRITES ONE WORD EVERY 64 WORDS WITH THE UPPER 16 BITS OF * ITS 22 BIT PHYSICAL ADDRESS, AND VERIFIES THE LOCATIONS WRITTEN. * THIS IS DONE IN FORWARD ORDER AND REVERSE ORDER. THIS TEST VERIFIES * WORD READS AND WORD WRITES. * * 6.10.2.3 LOW ORDER UNIQUE ADDRESS TEST * * THIS TEST WRITES EACH WORD WITH THE LOWER 16 BITS OF ITS 22 BIT * PHYSICAL ADDRESS, AND THEN VERIFIES THE LOCATIONS WRITTEN. THIS IS * DONE IN FORWARD AND REVERSE ORDER. THIS TEST VERIFIES WORD READS, * WORD WRITES, AND ECC WRITES. * * 6.10.2.4 RAM AND DATA PATH TEST * * THIS IS A SURROUND-DISTURB TEST OF THE RAMS AND A TEST OF THE RAM * AND BOARD DATA PATHS. THE PATTERNS WRITTEN BY THIS TEST ARE OPTIMAL * FOR SURROUND-DISTURB TESTING OF FOUR VENDORS 16K RAMS (CURRENT * VERSIONS AS OF 5-79): MOSTEK, TEXAS INSTRJ UMENTS, FAIRCHILD, AND * NATIONAL. THIS TEST VERIFIES WORD READS, WORD WRITES, AND ECC READS. * * 6.10.2.5 BYTE TEST * * THIS TEST WRITES MEMORY WITH DATA IN BYTE MODE, ALTERNATING UPPER * BYTE FIRST AND LOWER BYTE FIRST WITH EACH WORD. IT THEN VERIFIES * THE MEMORY WRITTEN, READING IN BYTE MODE. THIS TEST VERIFIES BYTE * READS AND BYTE WRITES. * * 6.10.2.6 MEMORY MICRO CACHE TEST * * THIS TEST VERIFIES PROPER OPERATION OF THE MICRO CACHE HIT/MISS LOGIC * IT DOES THIS BY RUNNING SHORT LOOPS WHICH ARE DESEGNED TO PRODUCE * EITHER HITS OR MISSES. THE LOOPS ARE RAN FOR A CERTAIN PERIOD OF * TIME (CONTROLLED BY THE REAL TIME CLOCK) AND A LOOP COUNTER IS * COMPARED TO LIMITS TO VERIFY EITHER HITS OR MISSES. THE HIT * LIMITS ARE HIGHER THAN THE MISS LIMITS. A HIT IS GENERALLY * EXPECTED IF A MEMORY REFERENCE (IF ADDRESS BITS 2-16 DO NOT * DO NOT CHANGE). A MISS IS EXPECTED IF A FOUR WORD BOUNDRY IS * CROSSED (IF ANY OF ADDRESS BITS 2-16 CHANGE). * * 6.10.3 ERROR HALTS * * UPON OCCURRENCE OF A HALT IN ECCL, READ THE P REGISTER AND REFER * TO THE PROGRAM LISTING TO DETERMINE THE CAUSE OF THE ERROR. * * AN ERROR HALT WILL OCCUR IN THE MEMORY SIZE CALCULATION IF THE USER * ENTERED TEST MEMORY SIZE DOES NOT EQUAL THE AMOUNT OF MEMORY THE * PROGRAM FOUND (ONLY 64K IS ACCESSABLE WITHOUT AN MMU). REENTER THE * MEMORY SIZE INTO THE A REGISTER BITS 8-14 IN 64K INCREMENTS AND * RESUME. THE PROGRAM WILL REPEAT THE MEMORY SIZE CALCULATION SEQUENCE. * TO TEST AN AMOUNT OF MEMORY SMALLER THAN THAT FOUND BY THE PROGRAM, * ENTER THE DESIRED TEST SIZE IN THE A REGISTER AS ABOVE, ENTER :FFFF * IN THE Q REGISTER, AND RESUME. * * DURING THE TIME THAT THE PROGRAM IS RELOCATED (CONSOLE DATA REGISTER * BIT 15 ON), ACTUAL PROGRAM LOCATIONS DO NOT MATCH LISTING ADDRESSES. * IF AN ERROR HALT OCCURS DURING THIS PERIOD, SUBTRACT :8000 FROM THE * P REGISTER CONTENTS TO OBTAIN THE CORRESPONDING LISTING ADDRESS. * * 6.10.4 PROGRAM RELOCATION * * IMMEDIATELY FOLLOWING TESTING OF THE 2ND 32K OF MEMORY, PAT495 IS * RELOCATED TO THAT PART OF MEMORY AND TESTS THE 1ST 32K. FOLLOWING * THIS IT IS MOVED BACK TO ITS ORIGINAL POSITION IN THE 1ST 32K. * * TESTING EXCLUDES LOCATIONS :84-:8B (UNIMPLEMENTED INSTRUCTION TRAP * AND MEMORY EXCEPTION TRAP VECTORS). DURING THE TIME PAT495 IS RELO- * CATED, THESE TWO TRAPS CONTAIN JUMPS TO SERVICE ROUTINES IN THE * RELOCATED PROGRAM. OCCURENCE OF ANY OTHER TRAPS OR INTERRUPTS DURING * THIS PERIOD WILL HAVE UNDEFINED RESULTS. * * 6.11 TEST B SHORT RUNNING MEMORY TEST (W/ECC) (ECCS) * * 6.11.1 DOUBLE AND SINGLE BIT ERROR TEST * * THIS TEST FINDS HARD DOUBLE AND SINGLE BIT ERROR ONLY. * ON DOUBLE BIT ERRORS THE TEST WILL HALT STORING ONLY THE LOCATION * IN MEMORY OF THE FIALURE. FOR SINGLE BIT ERRORS THE TEST WILL * HALT STORING THE BIT ERROR IN Q AND IN THE DATA REGISTER. THE * LOCATION OF THE FIALURE IS STORED IN AX. * FOR ECC CODE BIT FIALURE FFXX WILL BE PLACED IN THE UPPER BYTE. * FOR TEST B PROGRAM RELOCATION SEE 6.10.4 ABOVE * TITL * 6.12 TEST C, AUTOLOAD TEST (ALT) * * THIS TEST VERIFIES THE PROPER LOADING OF THE AUTOLOAD PROGRAM FROM * THE AUTOLOAD ROM. THIS TEST CANNOT BE ENTERED FROM ADDRESS :100, * :101, OR :102. ENTER THE STARTING ADDRESS OF ALT (AVAILABLE ON THE * LINK MAP) IN THE P REGISTER AND PRESK S RUN TO BEGIN EXECUTION. * * MEMORY LOCATIONS :00-:FF ARE COPIED TO ANOTHER 256-WORD AREA OF * MEMORY. THE PROCESSOR THEN HALTS WITH :FFFF IN THE CONSOLE DATA * REGISTER. THE OPERATOR THEN PERFORMS THE FOLLOWING STEPS. * * 1) SET THE SENSE SWITCH OFF TO ENSURE THAT THE AUTOLOAD * PROGRAM WILL BE LOADED BUT NOT EXECUTED. * 2) PRESS AUTO. THE PROCESSOR HALTS WITH THE AUTOLOAD * PROGRAM IN MEMORY LOCATIONS :00-:FF. * 3) ENTER ADDRESS ALTRTN (AVAILABLE ON THE LINK MAP) IN THE *  P REGISTER AND PRESS RUN. * * THE AUTOLOAD PROGRAM IS THEN MOVED TO THE AUTOLOAD TEST BUFFER * ALTBUF (ADDRESS AVAILABLE ON THE LINK MAP) AND THE ORIGINAL CONTENTS * OF :00-:FF ARE RESTORED. ALT COMPUTES THE CHECKSUM OF THE AUTOLOAD * PROGRAM INSTRUCTIONS AND LOADS IT INTO THE A REGISTER. IF THE * CHECKSUM IS CORRECT, :FF00 IS DISPLAYED IN THE CONSOLE DATA REGISTER; * AN INCORRECT CHECKSUM DISPLAYS :00FF. * * IF PAT495 WAS EXECUTED AT :100, :101, :102 PRIOR TO THE AUTOLOAD * TEST, THE PRIOR TEST SEQUENCE CAN NOW BE RESUMED BY PRESSING RUN. * ******NOTE*******INTERRUPTS AND TRAPS ARE INOPERABLE DURING THE *  AUTOLOAD TEST. IF A POWER FAIL, INTERRUPT, OR * TRAP OCCURS DURING ALT, PAT495 MUST BE RELOADED *  TO RESTORE LOCATIONS :00-:FF. DO NOT TEST CONSOLE * INTERRUPT RECOGNITION DURING ALT. * TITL * SECTION 7 OPERATION SUMMARY * * 7.1 DEFAULT MODE * * 1) LOAD AND EXECUTE THE PAT495 PROGRAM AT ADDRESS :100. * BIDP, UIT, ECCL, RTC, FLPT, NIDP, MMU, CACHE, * AND PRIV ARE EXECUTED CONTINUOUSLY. (PRESS RUN AFTER * EACH OF THE THREE HALTS DURING THE FIRST PASS OF BIDP.) * 2) PRESS STOP TO TERMINATE EXECUTION (DURING ECCL, AND * ECCS REVERSE THE STATE OF THE SENSE SWITCH BEFORE PRESSING * STOP). PRESS RUN TO CONTINUE EXECUTION FOLLOWING ANY *  ERROR HALTS. * * 7.2 DEMAND MODE * 1) LOAD THE PAT495 PROGRAM AND ENTER ADDRESS :101 INTO THE * P REGISTER. * 2) ENTER RUN OPTIONS IN THE A REGISTER AS FOLLOWS: * BIT 0 0 => RUN ECCL, ECCS RELOCATION TESTS. *  1 => BYPASS THE RELOCATION TESTS. * BIT 1 0 => HALT IF PDNCT AND PUPCT ARE NOT EQUAL. * 1 => DO NOT HALT IF PDNCT AND PUPCT ARE NOT EQUAL. * BITS 2-7 ARE NOT USED * BITS 8-15 ENTER MEMORY SIZE AS A BINARY NUMBER * (IN INCREMENTS OF 64K) * 3) SET THE CONSOLE DATA REGISTER BITS CORRESPONDING TO * THE DESIRED TESTS, AS FOLLOWS: * BIT 1 RUN UIT * BIT 2 RUN ECCL * BIT 3 RUN RTC * BIT 4 RUN IOT * BIT 5 RUN FLPT * BIT 6 RUN NIDP * BIT 7 RUN MMU * BIT 8 RUN CACHE * BIT 9 RUN PRIV * BIT 10 RUN ECCS * * 4) PRESS RUN. BIDP AND SELECTED TESTS ARE RUN CONTINUOUSLY. * (PRESS RUN AFTER EACH OF THE THREE HALTS DURING THE FIRST * PASS OF BIDP). * 5) PRESS STOP TO TERMINATE EXECUTION (DURING ECCL, AND * ECCS, REVERSE THE STATE OF THE SENSE SWITCH BEFORE * PRESSING STOP). PRESS RUN TO CONTINUE EXECUTION FOLLOWING * ANY ERROR HALTS. * * 7.3 RESTART MODE * * 1) LOAD THE PAT495 PROGRL AM AND ENTER ADDRESS :102 INTO THE * P REGISTER. * 2) FOLLOW STEPS 2 THROUGH 5 AS DESCRIBED IN DEMAND MODE. *  PASS COUNTERS AND POWER FAIL COUNTERS REMAIN ACCUMULATIVE * AT THIS ADDRESS. * * 7.4 AUTOLOAD TEST * *  1) LOAD THE PAT495 PROGRAM AND ENTER LINK MAP ADDRESS ALT * INTO THE P REGISTER. PRESS RUN. THE DATA REGISTER WILL * DISPLAY :FFFF. * 2) TURN SENSE OFF. * 3) PRESS AUTO. * 4) PRESS RUN. * 5) ENTER LINK MAP ADDRESS ALTRTN IN P REGISTER. PRESS RUN. * THE DATA REGISTER DISPLAYS :FF00 IF THE TEST WAS SUCCESSFUL, *  00FF IF THE TEST FAILED. * 6) PRESS RUN IF PAT495 WAS PREVIOUSLY EXECUTED AT ADDRESS * :100, :101, OR :102 TO RESUME EXECUTION OF OTHER PAT495 * TESTS. * TITL * APPENDIX A * OS4 LINK MEMORY MAP * * AN OS4 MEMORY LINK MAP IS DELIVERED WITH EACH PAT495 PROGRAM. * THIS MAP LISTS EACH LABEL IN THE PROGRAM WHICH HAS BEEN USED IN * A NAM DIRECTIVE, ALONG WITH ITS ACTUAL ADDRESS IN MEMORY WHEN * LOADED. * * MEMORY MAP LABEL DEFINITIONS * * COUNT1 BITS 0-15 OF A 32-BIT PASS COUNTER * COUNT2 BITS 16-32 OF A 32-BIT PASS COUNTER * PUPCT POWER UP COUNT * PDNCT POWER DOWN COUNT * PFERRS POWER UP/DOWN MISCOMPARE COUNT * A01000 STARTING ADDRESS OF BIDP (FIRST PASS) * A02000 STARTING ADDRESS OF BIDP (SUBSEQUENT PASSES) * PARTX STARTING ADDRESS OF PARTX (CONTAINS MOVE & ALT) * ALTRTN  SECOND ADDRESS LOADED BY THE OPERATOR DURING ALT EXECUTION * EXECUTION * ALT STARTING ADDRESS OF THE AUTOLOAD TEST * ALTBUF STARTING ADDRESS OF BUFFER CONTAINING THE AUTOLOAD * PROGRAM DURING ALT * MOVE STARTING ADDRESS OF THE MOVE UTILITY * DEBUG4 STARTING ADDRESS OF THE DEBUG4 UTILITY * PATEND HIGHEST PAT495 LOCATION * DEFAULT TEST SELECTION DURING DEFAULT MODE * UIT STARTING ADDRESS OF UNIMPLEMENTED INSTR. TEST * RTC STARTING ADDRESS OF REAL-TIME CLOCK TEST * IOT STARTING ADDRESS OF INPUT/OUTPUT TEST * FLPT STARTING ADDRESS OF FLOATING POINT INSTR. TEST * NIDP STARTING ADDRESS OF 4/95 NEW INSTR. TESTS * MMU STARTING ADDRESS OF MEMORY MANAGEMENT UNIT TEST * CACHE STARTING ADDRESS OF CACHE TEST * PRIV STARTING ADDRESS OF NEW TRAP TEST & LODU/STRU INSTR. TESTS * ECCL STARTING ADDRESS OF SHORT MEMORY DIAGNOSTIC TITL * APPENDIX B * * MOVE UTILITY * * A GENERAL PURPOSE MOVE ROUTINE IS INCLUDED IN PAT495. * OPERATION IS AS FOLLOWS. * * 1) ENTER REGISTER VALUES: * *  A REGISTER - LENGTH OF CODE SEGMENT TO BE MOVED * Q REGISTER - STARTING ADDRESS OF CODE SEGMENT TO BE MOVED *  X REGISTER - STARTING ADDRESS OF DESTINATION AREA * * 2) ENTER THE STARTING ADDRESS OF THE MOVE ROUTINE IN THE * P REGISTER. * 3) PRESS RUN. * * AFTER THE TRANSFER HAS COMPLETED, THE MOVE ROUTINE VERIFIES THE * TRANSFER. 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