IMD 1.18: 12/07/2013 8:44:55  åååååååååååååååååååååååååå åååååååå CPUMAN±¥ 3.TEXT2Ü&¼Ð ƒ¤4AP.TEXT2Ü&¼Ð ƒ¤48ST.TEXT2Ü&¼Ð ƒ¤8<S2.TEXT2Ü&¼Ð ƒ¤<Œ4D.TEXT2Ü&¼Ð ƒ¤Œ®4E.TEXT2Ü&¼Ð ƒ¤®Î5A.TEXT2Ü&¼Ð ƒ¤Îæ5B.TEXT2Ü&¼Ð ƒ¤æ4C.TEXT2Ü&¼Ð ƒ¤TC.TEXT2Ü&¼Ð ¥1.TEXT2Ü&¼Ð ¥.2.TEXT2Ü&¼Ð ¥.F4A.TEXT2Ü&¼Ð ¥Fx4B.TEXT2Ü&¼Ð ¥x€ TC.FIG.TEXT&¼Ð #¥åååååååååååå CPUMAN±¥ 3.TEXT2Ü&¼Ð ƒ¤4AP.TEXT2Ü&¼Ð ƒ¤48ST.TEXT2Ü&¼Ð ƒ¤8<S2.TEXT2Ü&¼Ð ƒ¤<Œ4D.TEXT2Ü&¼Ð ƒ¤Œ®4E.TEXT2Ü&¼Ð ƒ¤®Î5A.TEXT2Ü&¼Ð ƒ¤Îæ5B.TEXT2Ü&¼Ð ƒ¤æ4C.TEXT2Ü&¼Ð  ƒ¤TC.TEXT2Ü&¼Ð ¥1.TEXT2Ü&¼Ð ¥.2.TEXT2Ü&¼Ð ¥.F4A.TEXT2Ü&¼Ð ¥Fx4B.TEXT2Ü&¼Ð ¥x€ TC.FIG.TEXT&¼Ð #¥ååååååååååååBACK $LAST $EQUAL $CURSOR @@@O.«¡ƒ¤ .option (S1 F+)  .title PDQ-3 Hardware User's Manual  .input (H` U_ B~)  .paragraph (F% I5)  .margin (L5 R72)  .subtitle Bootstrapping UCSD Pascal  .odd  .page3  .inx Bootstrapping  _3. BOOT PROMS_  3.0 Bootstrapping UCSD Pascal (CPU Version PDQ-3/1)   %Once the PDQ-3 has been powered up, it is ready to boot.  .inx Diskettes  .inx Write-protect  .inx UCSD Pascal  Bootstrapping the UCSD Pascal system on the PDQ-3 re`quires  the disk`ette label`led "BOOT",  pro`vided with the PDQ- 3, and a blank disk.  The scratch disk must not be write-pro`tected. If the diskette has a  write-pro`tect notch in the lower right corner (see Figure 3.2.0), the  notch must be covered with the silver tape pro`vided with the disk`ette  before pro`ceeding.   .page29   .skip25  .inx Write-protect  .inx Diskettes  .indent22  A) Write-protect notch   .indent10  Figure ?????? The Diskette Write-Protect Notch   %To boot`strap the PDQ-3:   .inx Reset Button  .margin(L+5)  .undent3  1) Press the Reset button on the front panel.   .inx Diskettes  .undent3  2) Insert the "BOOT" disk into the left floppy disk drive as fol`lows:   .inx Floppy Disk Drives  .margin(L+5)  .undent3  a) Push in the bar below the door.  The door of the drive will pop open.   .undent3  b) Holding the diskette at the label end, with the label up,  slide the disk`ette into the left disk drive (see Figure 3.2.1) until  the disk`ette touches the back of the drive.   .undent3  c) Push the door of the floppy disk drive back down to close it. The  door makes an audible "click" when it latches.  .margin   .page28   .skip26  .inx Floppy Disk Drives  .inx Diskettes  .indent16  Figure ????? Inserting a Diskette   .inx UCSD Pascal  .inx Jumpers  .inx Reset Button  .inx Bootstrapping  .undent3  3) The PDQ-3 requires ap`proxi`mately fif`teen(15) sec`onds to boot  the UCSD Pascal System.  The jum`per op`tions (see sec`tion ?????) de`ter`mine the state of  the PDQ-3 after the Reset button is pressed:   .inx Diskettes  .inx Floppy Disk Drives  .inx HDT  .margin(L+5)  .undent3  --~The PDQ-3 comes up in the HDT state, prompt`ing the user with  a '#' (see Appendix A for de`tails on HDT). Once a boot`able  disk`ette has been in`serted into the left floppy disk drive, the user can  press `R` to boot the UCSD Pascal System.   .inx Floppy Control Cable  .inx CPU Module  .inx Run/Halt Button  .undent3  --~The machine comes up in an auto`matic boot`strap rou`tine.  As`suming a boot`able diskette has been in`serted in the left drive,  the floppy disk drives should start run`ning. If they do not,  check to make sure the disk`ette has been  in`serted correct`ly, and that the Run/`Halt button (front panel)  is in the Run (out) position. Also check that the floppy control  cable is securely connected to the CPU Module (refer to section ??? for  details).  .margin   .inx Configuration  .inx Console CRT  .inx Work Disk  .undent3  4) The "BOOT" disk boots a con`figur`ation pro`gram. Un`de`ci`pher`able  char`acters ap`pear on certain types of con`sole CRTs. This  prob`lem is cleared up once the screen is con`figured (later in the  initial bootstrapping process).  Read the text on the screen. The user is in`structed  to insert a scratch disk into  the right-hand drive and press the car`riage re`turn key on the key`board.  The program pro`ceeds to make a bootable work disk from the  scratch disk. Hence`forth, this work disk should be used  for boot`ing, and the "BOOT" disk should be saved as a backup.   .inx Console CRT  .undent3  5) After the work disk is made, the program prompts the user for  the type of console CRT to be used with the PDQ-3.   .inx Reset Butt on  .undent3  6) The pro`gram has finished when "Done." ap`pears on the  screen. Re`move the disk`ettes  from the drives as follows:   .inx Floppy Disk Drives  .inx Diskettes  .margin(L+5)  .undent3  a) Press down on the lever below the drive. The door should pop  open, and the edge of the disk`ette should be vis`ible.   .undent3  b) Gently pull the diskette forward, out of the drive.  .margin   .inx Bootstrapping  .undent3  7) In`sert the new`ly cre`ated work disk  into the left-`hand  disk drive, and bootstrap it (starting at step 1 above). IT IS RECOMMENDED  THAT THE BOOT DISK BE SAVED AS A BACKUP AND THAT THE WORK DISK BE USED  HENCEFORTH.   $LAST A $EQUAL $CURSOR $TAG ÀùlÀ³@@@O.«¡ƒ¤& .title PDQ-3 Hardware User's Manual  .subtitle Appendix A: Hexadecimal Debugging Tool (HDT)  .odd  .inx HDT  _A. HEXADECIMAL DEBUGGING TOOL (HDT)_   .inx I/O Devices  .inx Debugging  .inx Memory  .inx Bootstrapping  .inx UCSD Pascal  %The Hexadecimal Debugging Tool (HDT) is a powerful, low level  debugger capable of examining memory, examining I/O device reg`i`sters,  bootstrapping the UCSD Pascal system,  and recovering from power failures. It is implemented as a UCSD Pascal  .inx CPU Module  program resident in PROMS located on the PDQ-3 CPU Module. The PROMS  occupy memory locations F400 hex through F7FF hex. HDT uses memory  between 22 and 25 hex and 100 and 130 hex for temporaries.    _A.1 Invoking HDT_   %HDT is activated under one of the following con`ditions:  .margin(L+5)   .undent3  .inx Jumpers  --~ Initiation of the BDCOK L signal on the Q-Bus. HDT is automatically  executed when the BDCOK L signal is negated. (This will cause a full  system reset).   If the E14 jumper is installed on the PDQ-3 CPU Module (see section 3.2.1),  HDT immediatly attempts to boot`strap the UCSD Pascal system from the  boot`strap device.  If the E12 jumper is installed, HDT prints a '#' on  the console and waits for an HDT command. Activating the 'R' command causes  HDT to boot the UCSD Pascal system from the bootstrap device.   .inx Powering Up  .inx Power Fail  .undent3  --~Initial power up. HDT checks for a power fail restart in progress.  If a restart is in progress, HDT restarts the UCSD Pascal system at  the point where  a power failure interrupted it. If a restart is not in progress, HDT  behaves as if it were an initial power up sequence.   .inx Priority  .inx Console CRT  .undent3  --~Invocation of the control-p key. HDT is invoked as a high priority  process (priority 255) and the UCSD Pascal system is suspended.  It prints a '#' on the console and waits for an  .inx Interrupts  .inx UCSD Pascal  HDT command. During the execution of HDT, all interrupts are latcheä and  any outstanding DMA operations continue. Re`sump`tion of the UCSD Pascal  system occurs on receipt of the 'P' command from the console.   .undent3  --~Invocation of the HALT procedure from a Pascal program. This invokes  HDT in the same manner as the invocation of the conrtol-p key.  .margin     _A.2 HDT Commands_   %HDT can be commanded to examine and modify a 'current location' in memory,  boot the UCSD Pascal system from the bootstrap device, or proceed with a  UCSD Pascal program currently executing. All numbers are input and output  by HDT in hexadecimal format (eg. 1 hex = 1 decimal, A hex = 10 decimal,  and 10 hex = 16 decimal). All addresses point to 16-bit word quantities.  The commands are as follows:   .margin(L+5)  .inx Bootstrapping  .undent4  'R'~HDT reboots the UCSD Pascal system from the bootstrap device  specified by for standard systems as follows (custom systems may  differ):   .margin(L+5)  .undent3  --~If is empty, the PDQ-3 boots as if were 0.   .undent3  --~If is 0, the PDQ-3 boots from the left single-sided floppy disk drive.   .undent3  --~If is 1, the PDQ-3 boots from the right single-sided floppy disk drive.   .undent3  --~If is 4, the PDQ-3 boots from the left double-sided floppy disk drive.   .undent3  --~If is 5, the PDQ-3 boots from the right double-sided floppy disk drive.  .margin   .inx UCSD Pascal  .undent4  'P'~The currently executing UCSD Pascal program is resumed.   .undent4  .inx Memory  '/'~If a number has been entered, that number becomes the new current  location. HDT then displays the contents of the new current location.   .inx Memory  .undent5  ~If a number has been entered, that number is stored into the current  location. HDT then displays the HDT prompt '#'.   .inx Memory  .undent5  ~If a number has been entered, that number is stored into the current  location. HDT then increments the current location, and displays  the contents of the new current location.   .inx Memory  .undent4  '^'~If a number has been entered, that number is stored into the current  location. HDT then decrements the curr ent location, and displays  the contents of the new current location.   .inx Memory  .undent4  '@'~If a number has been entered, that number is stored into the current  location. The contents of the current location then becomes  the new current location, and HDT  displays the contents of the new current location.  .margin  .subtitle Appendix B: Reserved Memory Locations  .page  .inx Memory  _B. RESERVED MEMORY LOCATIONS_   _B.0 Bus Address Assignments_   .inx I/O Devices  %Since I/O device registers are mapped into the mem`ory space,  loca`tions F000 through FFFF are  .inx CPU Module  re`served for these registers. The PDQ-3 CPU Module on`board 'devices'  are as`signed ad`dresses  F400 through F7FF and FC00 through FC7F.   _B.0.1 PDQ-3 Onboard Device Addresses_   .inx Interrupt Vectors  %The following word addresses and inter`rupt vec`tors  are as`signed to de`vices lo`cated on the PDQ-3 CPU Module:   .option( F- )  DEVICE ADDRESS  INTERRUPT VECTOR   .inx HDT  HDT ROM F400 (lowest)  F5FF (CPU Module Serial #) FF7FF (highest)  .inx USART Control Register #1  .inx USART Control Register #2  Console terminal control register 1 FC10  Console terminal control register 2 FC11  .inx USART Status Register  Console terminal status register FC12  .inx Receiver Holding Register  Console terminal input register FC13 000E  .inx Transmitter Holding Register  Console terminal output register FC14 0012 (data) R0016 (protocol)  .inx Switches  System environment switch FC18 0002 (bus error) R0006 (pwr fail)  .inx Clocks  .inx Baud Rate Clock Counter  Console baud rate generator FC20  .inx System Clock Counter  System clock counter FC21 001A  .inx Interval Timer  Interval timer FC22 001E  .inx Counter Mode Register  Timer mode control byte FC23   .inx System Status Register  System status register FC24   .inx Floppy Disk Interface Registers  .inx Floppy Status Register  .inx Floppy Command Register  Floppy disk status/command register FC34  000A  .inx Track Register  Floppy disk track register FC35  .inx Sector Register  Floppy disk sector register FC36  .inx Floppy Data Register  Floppy disk data register FC37   .inx DMA Interface Registers  .inx DMA Command Register  DMA controller command register FC38 000A  .inx DMA Status Register  DMA controller status register FC39  .inx Byte Count Registers  DMA controller byte transfer count FC3A (low) FFC3B (high)  .inx Memory Address Registers  DMA controller memory start address FC3C (low) E FC3D (high)  DMA controller memory extension FC3E   Reserved FC4x  Reserved FC5x  .inx HDT  Pointer to HDT ROM FC68  Reserved FC6x  Reserved FC7x   NOTE: x = don't care  .option  .page  _B.0.2 Q-Bus Device Addresses_   .inx Q-Bus  .inx Interrupt Vectors  %Addres ses are reserved for certain devices on the Q-Bus. Their word  addresses and interrupt vectors are as follows:   .option ( F- )  DEVICE FIRST LAST VECTOR   Reserved F000 F003  IEEE std.~488 IBV11-A F033 F036 008A  bus interface  Parallel line DRV11 #3  0000-007F "unit  Parallel line DRV11 #2 0000-007F "unit  Parallel line DRV11 #1 0000-007F "unit  Analog-to-digital ADV11-A F880 F882  0084 "converter  Programmable RTC KWV11-A F889 F897 0090  Digital-to Analog AAV11-A F890 F893 "converter  Parallel line DRV11-B #1 FA84 FA87 002A "unit  Parallel line DRV11-B #2 FA88 FA8B 0000-00FF "unit  Parallel line DRV11-B #3 FA8C FA8F 0000-00FF "unit  Magnetic Tape  TM-11 FAA8 FAAE 004A  256 word ROM BDV11 FB00 FB5F  .inx Floppy Disk Drives  RX01 Floppy disk RXV11 FE3C FE7E 005A  .inx Mass Storage  Hard Disk RP-02 FEE0 FEEE  0056  RKO5 Mass storage RKV11 FF80 FF87 0048  .inx Printer  Printer LAV11,LPV11 FFA6 FFA7 0040  Terminals: "partial modem DLV-11 FEB8 FFBB 0030 $control "full modem DLV-11 E FEB8 FEBB 0030 $control "no modem DLV-11 F FEB8 FEBB 0030 $control "4 channel with DLV-11 J FEB8 FEBB 0030 $partial modem FFA0 FFAE 006x  control   .option  .subtitle Appendix C: Recommended CRTs  .page   .inx Console CRT  _C. RECOMMENDED CRTs_  .option( F- )    MODEL COMPANY   Elite 1521A DataMedia (manufacturer)  .undent1  *Elite 3052A 7300 North Crescent Blvd.  DT80-1 Pennsauden, NJ 08110 :(609) 665-2382 :  .undent1  *Zephyr Zentec Corporation (manufacturer) :2400 Walsh Ave. :Santa Clara, CA 95050 :(408) 246-7662 8  IQ120 Soroc Corporation (manufacturer)  .undent1  *IQ140 165 Freedom Ave. :Anaheim, CA 92801 :(714) 992-2860 :  .undent1  *Z-19 Advanced Digital Products (distributor) :7584 Trade St. :San Diego, CA 92121 :(714) 578-9595   .undent1  * Highly recommended  .option  .subtitle Appendix D: Cabling Recommendations  .page  .inx Cabling  _D. CABLING RECOMMENDATIONS_   _D.0 Cable Length vs Baud Rate_   .inx Baud Rate  .inx CPU Module  %The recommended maximum cable lengths  for the baud rates supported by the PDQ-3 CPU Module are:   .option(F-) 0Baud Rate Cable Length @(ft) (m) 2 3110 400 122 3300 400 122 3600 400 122 21200 400 122 22400 400 122 24800 200 61 29600 100 30.5 119200  50 15.25  .option   %Bellden 2464 cable or the equivalent is recommended.    _D.1 PDQ-3 Cable Requirements_    .inx RS-232C  .inx Printer  %The use of the RS-232C console connector on the PDQ-3 CPU module is  multiplexed between terminal data and printer data. All terminal data  is transmitted on the primary transmission lines, and all printer data  is transmitted on the secondary lines. Thus, an RS-232C cable that services  both a terminal and a printer must start with a common connector to the  PDQ-3 CPU Module console connector, then split into a terminal cable and  a printer cable. Such a cable is avail`able with the PDQ-3 System and is  wired as follows:   .page13  .inx CPU Module  .option(F-) 7 ACONNECTED PINS 3 3PDQ-3 CPU Module Terminal Connector 3 31 (Signal Ground)* 1 (Frame Ground) 32 (Recv Data) 2 (Xmit Data) 33 (Xmit Data) 3 (Recv Data) 37 (Signal Ground) 7 (Signal Ground) 216 (Car Det) 4 (Clear To Send) 220 (Data Set Rdy) 20 (Data Term Rdy)  .option   %Note: On the PDQ-3 CPU Module cable end, pins 4 (CTS) and 5  (RTS) must be shorted. On the Terminal Connector, pins 4 (RTS),  5 (CTS), and 8 (CARD) must be shorted.  .inx RS-232C  %Using this cable it is possible to communicate with any RS-232C terminal  in full duplex. If handshaking is necessary, it must be carried out using  a data sequence such as X-ON, X-OFF.    .subtitle Appendix E: Reference Materials  .page  _E. Reference Materials_  .inx Reference Materials  .margin(L+5)  .option ( F- )   .undent4  ***~PDQ-3 System User's Manual Advanced Computer Design   PDQ-3 Programmer's Manual Advanced Computer Design   Programming in Pascal Peter Grogono DAddison-Wesley FPublishing Co., Inc. DReading, Mass., 1978   Beginner's Guide For the Kenneth Bowles, UCSD  UCSD Pascal System Byte Publications, Inc. @  Pascal User's Manual & Report Jensen & Wirth DSpringer-Verlag DNew York, 1974 !  Microcomputer Handbook Digital Equipment Corp. DDigital Publishing Corp. DMaynard, Mass., 1979 @ C  .undent4  ***~ADDENDA Advanced Computer Design  .option  .margin %  .margin(L+5)  .undent4  ***~Provided by Advanced Computer Design as refer`ence mater`ial with  this manual.  .margin  .page  .subtitle Appendix F: Memory Modules   _F. Memory Modules_  .inx Memory Modules   %A wide variety of Q-Bus memory devices may be used with the PDQ-3T  system because of the systems ability to interface with the Q-Bus. There  are several factors to consider when obtaining a memory device for the  PDQ-3T system. The CPU needs the top 4K words of memory to address  peripheral devices and system con`trol-`status registers. The minimum  memory needed to run the operating system is 32K words. The maximum  amount of memory that the system can address is 64K words. A nominal  cycle time for the memory would be 500 nsec. with a 300 nsec. access  time. ACD will provide a list of authorized memory vendors upon request.       $LAST $EQUAL $CURSOR ONE TWO ûûûO.¹ ƒ¤ .output (ASC E+)  .option (S1 F+)  .title PDQ-3 Hardware User's Manual  .form ([// #30 t /// l56 // E #30 'Page ' p ///]  + [// #20 s /// l56 // #30 'Page ' p #63 E ///])  .input (H` U_ B~)  .paragraph (F% I5)  .margin (L5 R72)  $LAST $EQUAL $CURSOR ONE TWO {{{O.¹ ƒ¤ .option (S1 F+)  .title PDQ-3 Hardware User's Manual  .input (H` U_ B~)  .paragraph (F% I5)  .margin (L5 R72)    $EQUAL $TAG $CURSOR $CURSOR º”}O.Q¢ƒ¤ .title PDQ-3 Hardware User's Manual  .input (H` U_ B~)  .paragraph (F% I5)  .subtitle Chapter Four: The PDQ-3 CPU Module   .inx DMA Controller  .inx Floppy Disk Controller  .inx WD-Bus  .page3  _4.11 DMA Floppy Disk Controller_   %The DMA Floppy Disk Controller consists of the Western Digital WD1883 DMA  con`troller, the WD1793-02 Floppy con`troller and their supporting logic.  The DMA con`troller interfaces the floppy con`troller to the WD-bus for  control/status operations, inter`rupt operations, and DMA data transfers.    .page3  .inx Floppy Disk Controller  _4.11.0 Floppy Controller_   .inx Stepping Rate  .inx CRC  %The floppy con`troller provides all necessary floppy drive  control functions including  stepping pulse gen`eration and timing, track 0 de`tection, CRC gen`eration  .inx Formatting Diskettes  .inx Write Precompensation  and checking, write pre`compen`sation, receive data recovery and diskette  formatting.  .inx Floppy Disk Drives  The floppy con`troller is capable of controlling  up to four (4) single sided or double sided disk  drives in either single density (IBM 1 and 1D FM)  or double density (IBM 2 and 2D MFM) formats. Density selection  is software controllable, enabling transfers between disks formatted in either  single or double density format.   %The floppy controller communicates with the DMA con`troller (see section  4.11.1) to perform floppy data trans`fers and status inter`rupts. The  floppy con`troller  signals the DMA control`ler to trans`fer a byte between  memory and the floppy control`ler. It also signals the DMA con`troller  upon com`pletion of any floppy oper`ation. The DMA con`troller processes  the com`pletion signal from then on.   .inx Floppy Disk Interface Registers  %The floppy con`troller provides five interface registers. There are two  copies of each register in memory. One copy is a 16-`bit register containing  a copy of  .inx Floppy Select Register  the Floppy Drive Select register (see section 4.11.0.0) in the most significant  8 bits, and a copy of the interface register in the least significant 8 bits.  The second copy is an 8-bit register containing the interface  register in the least significant 8 bits (the most significant 8 bits is  undefined). Table 4.11.0 shows the device addresses of  these registers.   .page14  .option(F-)   .inx Floppy Status Register  .inx Floppy Command Register  .inx Floppy Select Register  .inx Floppy Data Register  .inx Track Register  .inx Sector Register  REGISTER WIDTH ADDRESS WIDTH ADDRESS ACCESS /(bits) (word) (bits) (word)  /With Drive Select Without Drive Select 3Register Register   COMMAND  16 FC34 8 FC30 Write Only  STATUS 8 FC34 8 FC30 Read Only  TRACK 16 FC35 8 FC31 Read/Write  SECTOR 16 FC36 8 FC32 Read/Write  DATA 16 FC37 8 FC33 Read/Write >  .option  .indent10  Table 4.11.0 Floppy Disk Interface Registers    .page3  _4.11.0.0 Drive Select Register_   .inx Floppy Select Register  %The Drive Select register resides in the most siginificant byte of the 16-bit  copies of the floppy interface registers. It is a write-only register,  containing the floppy drive, side and recording density select bits.   .page4  .option(F-)  BITS $|----15----|--14--|-13-12-|--11---|--10---|---9---|---8---| $| SIDE SEL | SDEN | xxxxx | SEL-3 | SEL-2 | SEL-1 | SEL-0 | $|----------|------|-------|-------|-------|-------|-------|  .option   .margin(L+5)  .page2  .inx Floppy Disk Drives  .undent3  --~SIDE SEL:  %This bit selects side 1 when set  to 1, and side 0 of a double sided  drive when set to 0. It should be set to 0 for single-sided drives.   .page2  .inx Track Number  .undent3  --~SDEN:  %This bit selects single density  operation when set to 1, and  selects double density when set  to 0. Operations on Track 0 are  in single density mode, regardless  of the value of this bit.   .page2  .undent3  --~SEL3:0:  %These bits select floppy disk  drives 3, 2, 1, and 0, respectively,  when set to 1. Only one drive  should be selected at any one time.  .margin    .page3  _4.11.0.1 Command Register_   .inx Floppy Command Register  %The Command register is an 8-bit or 16-bit write-only register (depending  on its address).  .inx Floppy Select Register  The most significant byte of the 16-bit version is a copy of the drive select  register. The most significant byte of the 8-bit   version is undefined. The  least significant byte of both versions contains the command  issued to the floppy con`troller. The eleven commands are divided into four  .inx Type I Commands  .inx Type II Commands  .inx Type III Commands  .inx Type IV Commands  groups: read/write head move commands (Type 1), data read/write commands  (Type 2), formatting commands (Type 3) and forced inter`rupt commands (Type 4). 0  %Note that the floppy con`troller cannot execute more than one command  at a time. Unpredictable results occur when the command register is loaded  .inx Floppy Status Register  without either the Not-Ready bit of the Floppy Status register  set, or the Busy bit reset (see section 4.11.0.2). The exception to this  rule is the Type 4 inter`rupt command described in section 4.11.0.1.3.   .page18  .option(F-) KBit # .Type Command 7 6 5 4 3 2 1 0 5 /I Restore 0 0 0 0 h V R r /I Seek 0 0 0 1 h V R r /I Step 0 0 1 u h V R r /I Step In 0 1 0 u h V R r /I Step Out 0 1 1 u h V R r /II Read Sector 1 0 0 m S 1 C 0 /II Write Sector 1 0 1 m S 1 C a /II Read Address 1 1 0 0 0 1 0 0 /III Read Track 1 1 1 0 0 1 0 0 /III Write Track 1 1 1 1 0 1 0 0 /IV Force Interrupt 1 1 0 1 p q s t  8flags reviewed below < 3Table 4.11.1.A Command Summary 4 4  .page15  .inx Type I Commands  .inx Track Register  .inx Stepping Rate .TYPE I 0 0h = Head Load Flag (bit 3) 2h = 1, Load head at beginning 2h = 0, Unload head at beginning 0V = Verify Flag (bit 2) 2V = 1, Verify on last track 2V = 0, No verify 0R,r = Stepping Motor Rate (bits 1,0) /(see Table 4.11.1.E for rate summary) 0u = Update Flag (bit 4) 2u = 1, Update Track register 2u = 0, No update " 0Table 4.11.1.D Flag Summary (Type I)   .page16  .inx Data Address Mark  .inx Deleted Data Mark  .inx Type II Commands /TYPE II 1 1m = Multiple Record Flag (bit 4) 3m = 0, Single Record 3m = 1, Multiple Records 1S = Side Select Flag (bit 3) 3S = 0, Select Side 0 3S = 1, Select Side 1 1C = Side Compare Flag (bit 1) 3C = 0, Disable Side Comparison 3C = 1, Enable Side Comparison 1a = Data Address Mark (bit 0) 3a = 0, FB (Data Mark) 3a = 1, F8 (Deleted Data Mark) , /Table 4.11.1.D Flag Summary (Type II)   .page10  .inx Interrupts  .inx Type IV Commands *TYPE IV 6 *p,q,s,t = Interrupt Condition Flags (bits 3-0) .all 0, Immediate Interrupt(1) .p = 1, Immediate Interrupt(2) (bit 3) .q = 1, Index Pulse (bit 2) .s = 1, Ready to Not-Ready Transition (bit 1) .t = 1, Not-Ready to Ready Transition (bit 0)  1Table 4.11.1.D Flag Summary (Type IV) 4   .page9  .inx Stepping Rate 9R r Per Track 9 90 0 3 ms 90 1 6 ms 91 0 10 ms 91 1 15 ms # # 3Table 4.11.1.E Stepping Rates  .option    .page3  .inx Type I Commands  _4.11.0.1.0 Type I Commands_   .inx Floppy Select Register  %Type I commands are used to control the positioning and loading  of the read/write head of the drive selected in the Drive Select  register. With the exception of the Seek command, the only action   necessary to invoke a Type 1 command is the storage of the command in  .inx Floppy Command Register  the Floppy Command register. Type 1 commands are executed regardless of  the ready status of the floppy drive.   .inx Floppy Disk Controller  %The Head Load bit of the Floppy Command register causes the  floppy con`troller to load or unload the read/write head before the  head is moved. The head is automatically unloaded either when the  drive is re-selected or three seconds after the head is last used  by the floppy con`troller.   .inx Track Number  .inx Sector ID  .inx Stepping Rate  %After the Head Load command is complete, the head is stepped at a rate  corresponding to the state of the R and r bits in the command  register. If the Verify bit of the command register indicates that the  head position is to be verified at the destination track, the head is  loaded at the conclusion of the stepping operation (if it is not  already loaded), and a 15 millisecond head settling delay commences.  When the Head Load settling timer expires, the first encountered  sector ID is read in the format spec`ified in the Drive Select  register. A verification is performed by comparing the track number  in the sector ID with the contents of the Track Register. The  verification can terminate in three ways:   .margin(L+5)  .inx Track Number  .inx Sector ID  .inx CRC  .undent3  --~The track numbers do not match and the CRC field of the  sector ID is valid. The Seek-Error bit of the status  register is set, and the command is terminated.   .inx CRC  .inx Sector ID  .undent3  --~For four revolutions of the floppy, no sector ID can  be found with a valid CRC field. The CRC-Error bit  of the status register is set, and the command is  terminated.   .inx Track Number  .inx Sector ID  .inx CRC  .undent3  --~The track numbers match and the CRC field of the sector  ID is valid. The command is successful.  .margin   .inx Floppy Status Register  .inx Interrupts  %Type I commands terminate when either the status register Not Ready bit  is set, or the Busy bit is reset.  They may be prematurely terminated by a Force Interrupt  command (Type IV). *   .page3  _4.11.0.1.0.0 Restore_   .inx Track Register  .inx Track Number  %This command steps the read/write head out (toward lower track  numbers) until track 0 is encountered or until 255 steps have been  performed. If track 0 is found, the Floppy Track register is set to  zero. If track 0 has not been found after 255 steps, the command is  .inx Seek  terminated and the Seek-Error bit of the status register is set. This  may be the result of a restore operation on a drive whose head is  outside of track 0. 5   .page3  _4.11.0.1.0.1 Seek_   .inx Seek  .inx Track Register  .inx Floppy Data Register  %This command steps the read/write head to the track spec`ified by  the contents of Floppy Data register. The track register is updated on  each step until it equals the data register. If no head movement is  necessary, the floppy con`troller terminates the command with`in  200 micro`seconds. ?   .page3  _4.11. 0.1.0.2 Step_  %This command steps the read/write head one track in the direction  the head was last moved. If the Update bit of the command register is  .inx Track Register  set, the track register is updated. $   .page3  _4.11.0.1.0.3 Step In_  .inx Track Number  %This command steps the read/write head one track towards the  center of the disk (higher track numbers). If the Update bit of the  .inx Floppy Command Register  .inx Track Register  command register is set, the track register is incremented. ?   .page3  _4.11.0.1.0.4 Step Out_   .inx Track Number  %This command steps the read/write head one track  towards the edge of the disk (lower track numbers). If the Update bit  .inx Floppy Command Register  .inx Track Register  of the command register is set, the track register is decremented. ;   .page3  _4.11.0.1.1 Type II Commands_   .inx Type II Commands  %Type II commands are used to read or write sector data fields on  .inx DMA Controller  the diskette. A Type II command requires that the DMA con`troller be  programmed to transfer the required number of bytes from/to the  appropriate buffer address (see section 4.11.1).  .inx Floppy Disk Drives  .inx Floppy Select Register  The floppy drive (selected in the  Drive Select register) must be on-line and ready,  and the floppy read/write head must be  po`sitioned over the desired track.   .inx Sector Number  .inx Sector Register  .inx Floppy Command Register  %A Type II command is issued by loading the desired sector number into  the Floppy Sector register and storing the command into the Floppy  Command register.   .inx CRC  .inx Sector ID  %Upon receipt of the Type II command, the floppy con`troller sets the  Busy bit of the Floppy Status register, loads the read/write head, and  waits 15 milliseconds for the head to settle. After expiration of the  head load timer, the floppy con`troller searches the track for a sector ID  whose CRC field is valid, and whose track and sector fields  match the contents of the Track and Sector registers.  In addition, if the command's Side Compare bit is set to 1,  the floppy-`side bit of the  sector ID must match the Side Sel bit of the Drive Select register.  The command can proceed in three ways:   .margin(L+5)  .undent3  .inx Record-Not-Found  .inx Floppy Status Register  --~For four revolutions of the floppy, no match is found.  The Record-Not-Found bit of the status register is  set, and the command is terminated.   .inx CRC  .inx Record-Not-Found  .inx Floppy Status Register  .undent3  --~A match is found, but a CRC error is detected in the  sector ID. The CRC-Error bit and the Record-Not-Found  bits of the status register are set, and the command is  terminated.   .inx CRC  .inx Sector ID  .undent3  --~A match is found, and the CRC field of the sector ID is  valid. The data field of the sector is located and data  transfer is initiated.  .margin   %Each of the Type II commands contains a Multiple Sector bit which  specifies multiple sector operations. If this bit is 0, a single  sector is transferred. If this bit is 1, the requested sector is  transferred, the Sector regis ter is incremented, and another  transfer is attempted. This sequence continues until a floppy error  .inx Sector Number  occurs. Since there are 26 sectors on a track, when a transfer is  attempted on sector 27, a Record-Not-Found error will occur, and the  command will terminate. Thus, the Multiple Sector bit is a directive  to transfer until the end of the track is reached.   .inx Floppy Status Register  %Type II commands terminate when either the status register Not-Ready bit  is set, or the Busy bit is reset.  .inx Interrupts  .inx Type IV Commands  They may be prematurely terminated by a Force Interrupt  command (Type IV). *   .page3  _4.11.0.1.1.0 Read Sector Command_ $  .inx Sector ID  .inx Sector Register  .inx Data Address Mark  .inx Record-Not-Found  .inx Floppy Status Register  %The Read Sector command causes the floppy con`troller to read the  data field of the sector named in the Floppy Sector register. The  floppy con`troller must find the Data Address Mark of the Data Field  within 30 bytes of the last byte of a single density sector ID CRC  field (within 43 bytes for double density); otherwise the  Record-Not-`Found bit of the Status register is set, and the command is  terminated.   .inx DMA Controller  %Upon receipt of a data byte from the floppy drive, the floppy  con`troller signals the DMA con`troller to transfer the byte from the  .inx Floppy Data Register  Floppy Data register into memory. If the DMA con`troller has not read  the Data register by the time a new byte is ready, an overrun  condition occurs. The Lost-Data bit of the Status register is set, and the  command is terminated.   .inx CRC  .inx Data Address Mark  .inx Floppy Status Register  %At completion of the data transfer, the Record-Type bit of the  status register is set according to the type of Data Address Mark found  at the beginning of the sector. If the CRC field computed from the  sector data does not match the data CRC field on the floppy, the CRC  Error bit of the status register is set. 6   .page3  _4.11.0.1.1.1 Write Sector Command_  .inx DMA Controller  %The Write Sector command causes the floppy con`troller to write to the  .inx Sector Register  .inx Floppy Data Register  .inx Sector ID  data field of the sector named in the Floppy Sector register. The  floppy con`troller signals the DMA con`troller to load the Floppy Data  register with a data byte from memory. The floppy con`troller activates  .inx Floppy Disk Drives  the floppy drive write logic 11 bytes (22 bytes in double density)  .inx Sector ID  after the last byte of the sector ID CRC field. ?  .inx Data Address Mark  .inx Deleted Data Mark  .inx Lost-Data  .inx Floppy Data Register  .inx Floppy Status Register  %If the DMA con`troller has not loaded a data byte into the Data  register by this time, the Lost-Data bit in the Floppy Status register  is set, and the command is terminated. If the Data register has been  loaded, six bytes of zeros (12 bytes in double density) are written  onto the disk. The Data Address Mark is then written according to the  Address Mark field of the write sector command. If this bit is 0, a  Data Mark is written. If this bit is 1, a Deleted  Data Mark is  written.   %A data request is made to the DMA con`troller for each byte  .inx Floppy Data Register  written to the floppy. If the Data register has not been loaded by the  appropriate time, the Lost-Data bit in the Status register is set, and  a zero byte is written to the floppy. Transfer continues until the  .inx CRC  last data byte is written. The two-byte CRC field is computed and  written, followed by a byte containing FF hex (4F hex in double  density). The Write Gate is then deactivated.    .page3  _4.11.0.1.2 Type III Commands_   .inx Type III Commands  .inx DMA Controller  %Type III commands are used to read or write track diskette formatting  information. A Type III command requires that the DMA con`troller be  programmed to transfer the required number of bytes from/to the  appropriate buffer address (see dection 6.11.2), and that the  floppy read/write head be  .inx Floppy Disk Drives  po`sitioned over the desired track. The floppy drive (selected in the  Drive Select register) must be on-line and ready,  and the floppy read/write head must be  positioned over the desired track.   .inx Floppy Command Register  %A Type III command is issued by storing the command into the Floppy  Command register.   .inx Floppy Disk Controller  .inx Floppy Status Register  %Upon receipt of the Type III command, the floppy con`troller sets the  Busy bit of the Floppy Status register, loads the read/write head, and  waits 15 milliseconds for the head to settle.   %Type III commands terminate when either the Status register Not-Ready bit  is set, or the Busy bit is reset.  .inx Interrupts  .inx Type IV Commands  They may be prematurely terminated by a Force Interrupt  command (Type IV). *   .page3  _4.11.0.1.2.0 Read Address_   .inx Sector ID  %The Read Address command causes the floppy con`troller to  transfer the sector ID field of the next sector  to arrive under the floppy read/write head. The sector ID field contains  six bytes and appears in memory as follows: 1  .page8  .inx Sector Number  .inx Track Number  .option(F-) 4Byte Contents 5 50 Track Number 51 Side Number 52 Sector Number 53 Sector Length 54 CRC1 55 CRC2  .option    .inx CRC  %If the CRC field of the sector ID is not valid (CRC1 and CRC2)  the CRC-Error bit of the Floppy Status register is set. In any case, the  floppy con`troller stores the track number found in the sector ID  .inx Sector Register  into the Floppy Sector register. 6 6  .page3  _4.11.0.1.2.1 Read Track_   .inx Index Mark  %The Read Track command causes the floppy con`troller to wait for the  floppy Index Mark. It then transfers all bytes on the floppy until the next  Index mark is encountered. This includes sector ID's, sector data fields,  and track formatting information. No CRC checking is performed. 6  %Note that there is an indeterminable number of bytes of formatting  information on each track. Thus, either a transfer byte count under-`run should  .inx Lost-Data  be expected from the DMA con`troller, or a Lost-Data status should be   expected from the floppy con`troller.    .page3  _4.11.0.1.2.2 Write Track_   %The Write Track command causes the floppy con`troller to write one  full track of formatting information to the disk. The information  .inx Sector ID  .inx CRC  contains sector IDs, CRC fields, reserved clocking patterns,  and other information as described in  Table 4.11.2.   .inx Index Mark  %The floppy con`troller starts writing at the leading edge of the Index  Pulse and continues until the next Index Pulse. Prior to the first write  .inx DMA Controller  .inx Lost-Data  .inx Floppy Data Register  .inx Floppy Status Register  operation, the floppy con`troller requests one byte from the DMA con`troller.  If the DMA con`troller has not loaded the Floppy Data register within  96 microseconds (48 microseconds for double density), the Lost-Data bit  of the Floppy Status register is set, and the command is terminated.  The DMA con`troller is signalled each time another byte is required. If  an under-`run occurs, a zero byte is transferred and the Lost-Data bit of the  Status register is set. 6 6  .page29  .option(F-) !Data Pattern Single Density Double Density $(Hex) Function Function ! !00 thru F4 Write 00 thru F4 Write 00 thru F4 9with Clk = FF in MFM ! !F5  Not Allowed Write 0A * in MFM, Qpreset CRC ! !F6 Not Allowed Write C2 ** in MFM ! !F7 Generate 2 CRC bytes Generate 2 CRC Qbytes ! !F8 thru FB  Write F8 thru FB, Write F8 thru FB 9Clk=C7,Preset CRC in MFM ! !FC Write FC with Clk=D7 Write FC in MFM ! !FD Write FD with Clk=FF Write FD in MFM ! !FE Write FF with Clk=FF Write FE in MFM ! !FF Write FF with Clk=FF Write FF in MFM ! (* Missing clock transition between bits 4 and 5 (** Missing clock transition between bits 3 and 4 !  .option  .indent10  Table 4.11.2 Formatting Control Byte Functions     .inx Formatting Diskettes  .page3  _4.11.0.1.2.3 Formatting_   %A track is formatted by positioning the read/`write head over the desired  track, loading the DMA Address and Count Registers (see section 4.11.1) with  the appropriate address and byte count for the information described in  tables 4.11.3 and 4.11.4, and issuing a Write Track command.   %Table 4.11.3 describes one track of a disk in IBM single-`density format  with 128 bytes per sector. The left side of the table specifies the for`mat  com`mand values  to be written to the disk by the DMA Controller in order to format a track.  The right side of the table describes the data image read from a format`ted  track by a Read Track command (see section 4.11.0.1.2.1).   .page26  .option(F-) 'VALUE TO WRITE VALUE GENERATED # #NUMBER OF HEX NUMBER OF HEX %BYTES VALUE BYTES VALUE # &40 FF  40 Filler '6 00 6 Filler '1 FC - Index Mark & 26 FF 26 FF ' '6 00 6 00 '1 FE 1 ID Address Mark '1 Track Number 1 Track Number (00-4C) '1 Side Number 1 Side Number (00 or 01) '1 Sector Number 1 Sector Number (01-1A)  * 1 00 1 00 '1  F7 2 CRC bytes &11 FF 11 Filler '6 00 6 Filler '1 FB 1 Data Address Mark %128 E5 128 Data '1  F7 2 CRC bytes &27 FF 27 Filler & %222 FF 222 FF  .option  .indent12  Table 4.11.5 Track Format: Single Density   .margin(L+2)  .undent2  *~This section is written 26 times per track; the other sections are written  once per track.  .margin   %Table 4.11.4 describes one track of a disk in IBM double-`density format  with 256 bytes per sector. The left side of the table specifies the format  command values  to be written to the disk by the DMA Controller in order to format a track.  The right side of the table describes the data image read from a format`ted  track by a Read Track command (see section 4.11.0.1.2.1).   .page29  .option(F-) 'VALUE TO WRITE VALUE GENERATED # #NUMBER OF HEX NUMBER OF HEX %BYTES VALUE BYTES VALUE # &80 4E 80 Filler &12 00  12 Filler '3 F6 3 Filler '1 FC - Index Mark &50 4E 50 4E  &12 00  12 00 '3 F5 3 F5 '1 FE 1 ID Address Mark '1  Track Number 1 Track Number (00-4C) '1 Side Number 1 Side Number (00 or 01) '1 Sector Number 1 Sector Number (01-1A)  * 1 01 1 01 '1 F7 2 CRC bytes &22 4E 22 Filler &12 00 12 Filler '3  F5 3 Filler '1 FB 1 Data Address Mark %256 E5 256 Data '1 F7 2 CRC bytes &54 4E 54 Filler & %548  FF 548 FF  .option  .indent12  Table 4.11.4 Track Format: Double Density   .margin(L+2)  .undent2  *~This section is written 26 times per track; the other sections are written  once per track.  .margin   %NOTE: When the Floppy Controller encounters an index mark, it  issues an interrupt to the DMA Controller. If the current DMA transfer has  not completed, and the DMA Controller is in the process of requesting control  of the Q-Bus, the interrupt causes the DMA Controller, and thus the entire  PDQ-3, to halt. During Read Track and Write Track operations, the DMA C ount  Registers  must be programmed so that the DMA transfer termi`nates before the next index  pulse is sensed. Tables 4.11.3 and 4.11.4 give byte counts which have been  found to alleviate this problem.  If these values are used, and the problem still arises, the number of bytes  of filler at the end of each track (222 for single-`density; 548 for  double-`density), as well as the value loaded into the DMA Count Registers  must be decreased.    .page3  _4.11.0.1.3 Type IV Commands_   .inx Type IV Commands  .inx Interrupts  .inx Floppy Status Register  .inx Floppy Command Register  %Type IV commands are Force Interrupt commands, and are the only  commands which may be issued to the floppy con`troller when the Busy bit  of the Floppy Status register is set. A Type IV command is issued by loading  it into the Floppy Command register. This  command terminates upon the satis`faction of the condition spec`ified by the  Interrupt Condition bits (bits 0 - 3). Upon termination, the Busy  bit of the status register is reset.  If there was a floppy command in progress when the Type IV command was  initiated, the command is term`inated, and  the Status register is updated according to the type of the  inter`rupted command. If no floppy command was in progress, the Status  register is set as if a Type I command was executed.   %The termination conditions for the Type IV commands are described in  Table 4.11.3.   .page27  .inx Interrupts  .option(F-)  'BITS TERMINATION CONDITIONS !p q s t  !0 0 0 0 Immediate Termination: The Busy bit :of the status register is reset. Any :command terminates, but no inter`rupt :is generated. ! !0 0 0 1 Termination occurs when the selected :unit's status changes from Not-Ready :to Ready. The busy bit is immediately :reset and an inter`rupt is generated. ! !0 0 1 0 Termination occurs when the selected :unit's status changes from Ready to :Not-Ready. The busy bit is immediately :reset and an inter`rupt is generated. ! !0 1  0 0 Termination occurs when the floppy :con`troller encounters the next Index :Pulse. The busy bit is immediately :reset and an inter`rupt is generated.  !1 0 0 0 Immediate Interrupt: An inter`rupt :is generated, but the Busy bit of the :status register is not reset.  .option   .indent11  Table 4.11.3 Type IV Termination Conditions    .page3  _4.11.0.2 Status Register_   .inx Floppy Status Register  %The Floppy Status Register is either an 8-bit or a 16-bit read-only register  (depending on its address).  It resides in the least significant byte of both versions.  .inx Floppy Select Register  Since the Floppy Select register occupies the most significant byte of the  16-bit version, but is a write-only register, the most significant byte  of both versions of the Status register is undefined.   .inx Type IV Commands  %The Status register reflects the status of the last command executed on the  floppy drive that was last selected in the Drive Select register.  Upon receipt of any command except a Type IV command (see  section 4.11.0.1.3), the Busy status bit is set .   %The Status register is interpreted according to the type of command last  executed by the floppy con`troller.    .page3  .inx Type I Commands  _4.11.0.2.0 Type I Command Status_   %The bits of the Status register are interpreted after the termination of a  Type I command as follows:   .page5  .option(F-) ! BITS !----7------6-------5-------4-------3-------2-------1-------0----- !! NOT ! WRITE ! HEAD ! SEEK ! CRC ! TRACK ! INDEX ! BUSY ! !! READY ! PROT ! LOAD ! ERROR ! ERROR ! 00 ! PULSE ! ! !-----------------------------------------------------------------  .option   .margin(L+5)  .page2  .undent3  --~NOT READY:  %This bit is set to 1 when the selected  drive is not ready. It is set to 0  if the drive is ready.   .page2  .inx Write-protect  .inx Floppy Disk Drives  .undent3  --~WRITE PROT:  %This bit is set to 1 if the diskette  installed in the selected drive is  write protected. It is set to 0 if a  write operation is possible.   .page2  .undent3  --~HEAD LOAD:  %This bit is set to 1 if the read/write  head on the selected drive is loaded  and engaged. This occurs about 35ms  after a head load command is issued.  The bit is set to 0 when the head is  unloaded.   .page2  .inx Sector ID  .inx Track Number  .inx Track Register  .inx CRC  .undent3  --~SEEK ERROR:  %This bit is set to 1 following a  Verify operation where no sector ID  is found to have both a valid CRC  field, and a track number matching  the contents of the Track register  within 4 revolutions of the disk.   .page2  .undent3  .inx CRC  --~CRC ERROR:  %This bit is set to 1 if a CRC Error  is detected during a Verify operation  and a sector ID is encountered with  an invalid CRC field.   .page2  .undent3  --~TRACK 00:  %This bit is set to 1 when the read/write  head of the selected drive is positioned  over track 00.   .page2  .inx Index Mark  .undent3  --~INDEX:  %This bit is set to 1 when the floppy  index mark is detected by the selected  drive.   .page2  .undent3  --~BUSY:  %This bit is set to 1 for the duration of  the execution of a command. It is set to  0 upon the termination of the command.  .margin    .page3  _4.11.0.2.1 Type II and Type III Command Status_   .inx Type II Commands  .inx Type III Commands  %The bits of the Status register are interpreted after the termination of a  Type II or a Type III command as follows:   .page7  .option(F-) ! BITS !----7-------6-------5--------4--------3-------2------1------0---- !! NOT ! WRITE ! RECORD ! RECORD ! CRC ! LOST ! DATA ! BUSY ! !! READY ! PROT ! TYPE / ! NOT ! ERROR ! DATA !REQUEST! ! !! ! ! WRITE ! FOUND ! ! ! ! ! !! !  ! FAULT ! ! ! ! ! ! !-----------------------------------------------------------------  .option ,  .margin(L+5)  .page2  .undent3  --~NOT READY:  %This bit is set to 1 if the selected  drive is not ready. It is set to 0  if the drive is ready.   .page2  .inx Floppy Disk Drives  .inx Write-protect  .undent3  --~WRITE PROT:   %This bit is set to 1 if the diskette  in the selected drive is write-`protected. It is set to 0 if a write  operation is possible.   .page2  .inx Deleted Data Mark  .undent3  --~RECORD TYPE/WRITE FAULT:  %This bit is set to 1 following a Read  Sector if the selected sector contains  a Deleted Data Mark. It is set to 0 if  the mark is not present. This bit is  not used on a Read Track command.  Following either a Write Sector or a  Write Track command, this bit is set to  1 if the selected floppy drive signals  a Write Fault. It is set to 0 if the  write operation is successful.   .page2  .inx Record-Not-Found  .undent3  --~RECORD NOT FOUND:  .inx Sector ID  .inx CRC  %This bit is set to 1 if no sector ID  can be found that both has a valid CRC  field, and matches the sector contained  in the sector register. It is also set  to 1 if no Data Mark can be found  within 30 bytes of the preamble CRC  (43 bytes for double density). This  bit is set to 0 if the command is  successful.   .page2  .undent3  .inx Record-Not-Found  .inx CRC  --~CRC ERROR:  %This bit is set to 1 if a CRC Error has  been detected. If the error is found  in a sector ID field, the Record-Not-  Found bit is also set to 1. This bit is  set to 0 if the command is successful.   .page2  .undent3  --~LOST DATA:  .inx Lost-Data  %This bit is set to 1 if either a read  data over-`run or a write data under-`run  is detected. If the error is detected  during a read operation, the over-`run  byte is lost. If the error is detected  during a write operation, a zero byte  is written to the floppy. This bit is  set to 0 if the command is successful.   .page2  .undent3  --~DATA REQUEST:  .inx DMA Controller  .inx Floppy Disk Controller  .inx Floppy Data Register  %This bit is set to 1 when the floppy  con`troller signals the DMA con`troller  to service the Floppy Data register.  It is set to 0 when the DMA con`troller  satisfies the request.   .page2  .undent3  --~BUSY:  %This bit is set to 1 to indicate that  a command is in progress.  .margin    .page3  _4.11.0.2.2 Type IV Command Status_   .inx Type IV Commands  .inx Floppy Command Register  %If a Force Interrupt command is executed when  there is a current command under execution, and the 'p' bit of the Command  register is set to 0, the Busy status bit is set to 0, and the rest of  the status bits are unchanged. If a Force Interrupt command is issued and  the con`troller is not executing a command, the Busy status bit is set to  0, and the status for a Type 1 command is loaded into the Status register  (see section 4.11.0.2.0).    .page3  _4.11.0.3 Data Register_   .inx Floppy Data Register  %The Floppy Data register is either an 8-bit or a 16-bit read-write  register (depending on the address)  .inx Type II Commands  that buffers data for the DMA con`troller during data Type II  operations (see section 4.11.0.1.1). It also contains the destination  .inx Track Number  track number  during a Seek operation (see section 4.11.0.1.0.1).    .page3  _4.11.0.4 Track Register_   .inx Track Register  %The Floppy Track register is either an 8-bit or a 16-bit read-write  register (depending on the address) that cont ains the track number under  the read/write head of the most recently accessed floppy drive. This  .inx Type I Commands  .inx Type II Commands  register is updated by the Type I commands, and used in verifying the head  position during Type I and Type II commands.   .inx Floppy Disk Drives  %When it is possible that the floppy con`troller may be used with more than  one floppy drive, the current track for any unselected drives must be maintained  by the software floppy driver. When the previously unselected drive is  selected, the Track register must be loaded with the appropriate track number.   %Note: This register should not be loaded when the floppy con`troller is  busy.    .page3  _4.11.0.5 Sector Register_   .inx Sector Register  .inx Sector Number  %The Floppy Sector register is either an 8-bit or a 16-bit read-write  register (depending on the address) that contains the sector number  .inx Type II Commands  to be accessed by a Type II command (see section 4.11.0.1.1). It also contains  .inx Track Number  the current track  number after the execution of a Read Address command (see section 4.11.0.1.2.0).   %Note: This register should not be loaded when the floppy con`troller is  busy. $LAST A $EQUAL $TAG $CURSOR FFD G¬  VvVVªO.: ƒ¤( .title PDQ-3 Hardware User's Manual  .input (H` U_ B~)  .paragraph (F% I5)   .page3  .inx DMA Controller  .inx Floppy Disk Controller  _4.11.1 DMA Controller_   %The DMA Controller interfaces the Floppy Disk Controller and  the memory. It generates all bus  request signals, all bus protocol signals, and status inter`rupts necessary  .inx Memory  to effect DMA transfers between the floppy con`troller and memory without  processor inter`vention. Moreover, all floppy con`troller dat a transfers  .inx Floppy Disk Interface Registers  and interrrupt processing is performed by the DMA con`troller. Floppy  con`troller register addresses select the DMA con`troller, which in turn  .inx Interrupts  selects the appropriate register of the floppy con`troller. Floppy con`troller  inter`rupts are communicated to the DMA con`troller, which may be programmed  to allow or disallow the inter`rupt.   .inx DMA Interface Registers  .inx DMA Control Register  .inx DMA Status Register  .inx Byte Count Registers  .inx Memory Address Registers  %The DMA con`troller provides  4 groups of interface registers: the Control register, Status  register, Byte Count register, and the Memory Address register. They are  listed in Table 4.11.4 with their corresponding device address locations.   .page13  .option(F-) - (REGISTER WIDTH ADDRESS  ACCESS <(bits) (word) ( (CONTROL 8 FC38 Write Only (STATUS 8  FC39 Read/Write (BYTE COUNT (low) 8 FC3A Read/Write (BYTE COUNT (high) 8 FC3B Read/Write (ADDRESS (low) 8 FC3C Read/Write (ADDRESS (high) 8 FC3D Read/Write (ADDRESS (extension) 2 FC3E Read/Write -  .option  .indent15  Table 4.11.4 DMA Interface Registers   %Each DMA interface register is contained in the least signifi`cant  byte of a 16-bit word.  The most signifi`cant byte is undefined.  The high Byte Count and low Byte Count registers combine to form  the most and least signifi`cant bytes, respectively, of a 16-bit two's  complement byte count register.  The extension Address, high Address, and low Address  registers combine to form an 18-bit memory buffer address register.  This register is the address of a memory byte. Since addresses on the PDQ-3  are word addresses, a byte address is obtained from a word address by  adding the word address to itself.   %The DMA Controller may be programmed to transfer information between the  .inx Memory  floppy and memory in four steps:   .margin(L+5)  .undent3  1) Store the byte address of the memory buffer into  the Address register group.   .undent3  2) Load the Byte Count registers with the two's  complement of the buffer size.   .undent3  3) Program the Control register for the direction,  the inter`rupt characteristics, and the bus  handling characteristics of the transfer.   .inx Floppy Disk Controller  .undent3  4) Program the floppy con`troller to start the data  transfer.  .margin ,  %The transfer starts when the floppy con`troller signals the DMA con`troller  that DMA service is necessary. The DMA con`troller issues a DMA bus  .inx Bus Master  request and then waits until it is granted the bus mastership. As the bus  master, the DMA con`troller controls the bus handshaking protocol necessary  to transfer a byte of data between the memory and the floppy con`troller.  After the byte is trans`ferred, the memory buffer address is incremented to  point at the next byte to be transferred.    .page3  _4.11.1.0 DMA Control Register_   .inx DMA Control Register  .inx Interrupts  %The DMA Control register i s a write-only register used to initiate DMA  operations. The DMA con`troller may be programmed to inter`rupt on a number  of different conditions including floppy con`troller completion, bus timeout,  and DMA termination.   .page4  .option(F-) ( BITS (--7-----6------5-----4------3------2-----1-----0--- (! X ! AECE ! HBUS ! IOM ! TCIE ! TOIE ! DIE ! RUN ! (---------------------------------------------------   .option  .margin(L+5)  .page2  .undent3  --~X:  %This bit is not used.   .page2  .undent3  --~AECE:  %When the Address Extension Carry Enable  is set to 1, carry operations out  of the high Address register are  propa`gated into the extension address  register. This bit should be set to  1 when accessing more than 64K bytes  of memory.   .page2  .inx Bus Master  .undent3  --~HBUS:  %When the Hold Bus bit is set to 1, the  DMA con`troller acts as bus master for the  entire duration of the DMA operation. If  this bit is set to 0, the DMA con`troller  relinquishes the bus mastership after each  byte transfer. This bit should be set to  0.   .page2  .inx Memory  .undent3  --~IOM:  %The I/O Mode bit is set to 1 in order to  perform DMA transfers from the floppy con`troller  to memory. This bit is set to 0  in order to perform DMA transfers from  memory to the floppy con`troller.   .page2  .inx Interrupts  .undent3  --~TCIE:  %The Transfer Count Interrupt Enable bit is  set to 1 in order to allow the DMA con`troller  to inter`rupt the processor when both the low  and high Byte Count registers are zero. This bit  is set to 0 in order to disallow the inter`rupt.   .page2  .undent3  --~TOIE:  %The Time Out Interrupt Enable bit is set to  1 in order to allow the DMA con`troller  to inter`rupt the processor if the memory  does not respond within 5 microseconds of  a DMA Sync signal. This bit is set to 0 in  order to disallow the inter`rupt.   .page2  .undent3  --~DIE:  %The Device Interrupt Enable bit is set to 1  in order to allow a Floppy Controller task completion  inter`rupt to inter`rupt the processor. This bit  is set to 0 in order to disallow the  inter`rupt.   .page2  .undent3  --~RUN:  %The Run bit is set to 1 in order to start a DMA  operation, thereby causing the Busy bit in the  .inx DMA Status Register  Status register to be set. This bit is set to  0 to cancel any DMA operations.  .margin    .page3  _4.11.1.1 DMA Status Register_   .inx DMA Status Register  %The DMA Status register contains the status information for the DMA  con`troller. It may be read at any time, but may be written only when  the Busy status bit is set to 0.   .page4  .option(F-) & BITS &----7------6------5-----4------3-----2------1-----0--- &! BUSY ! AECE ! HBUS ! IOM ! TCZI ! TOI ! DINT ! BOW ! &------------------------------------------------------   .option  .margin(L+5)  .page2  .undent3  --~BUSY:  %The Busy bit is set to 1 when a DMA  operation is in progress.   .page2  .undent3  --~AECE:  %The Address Extension Carry Enable bit  is a copy of the AECE bit of the  command register.   .page2   .undent3  --~HBUS:  %The Hold Bus bit is a copy of the HBUS  bit of the command register.   .page2  .undent3  --~IOM:  %The I/O Mode bit is a copy of the IOM  bit of the command register.   .page2  .undent3  --~TCZI:  %The Transfer Count Zero Interrupt bit is  set to 1 to indicate that both the high  and the low Byte Count registers are zero. If  the TCZI bit of the Command register is set  to 1, an inter`rupt is generated. The  inter`rupt is cleared by making either the  high or the low Byte Count register non-zero, then  by setting the TCZI bit to 0.   .page2  .undent3  --~TOI:  %The Time Out Interrupt bit is set to 1 to  indicate that the memory did not respond  with a Reply signal within 5 microseconds  of the DMA Sync signal. If the TOIE bit of  the command register is set to 1, an  inter`rupt is generated. The inter`rupt is  cleared by setting the TOI bit to 0.   .page2  .inx Interrupts  .undent3  --~DINT:  %The Device Interrupt bit is set to 1 to  indicate that the Floppy Controller has  completed an operation. If the DIE bit  of the command register is set to 1,  a processor inter`rupt is generated. The  inter`rupt is cleared by reading the  Floppy Controller Status register, then  by setting the DINT bit to 0.   .page2  .undent3  --~BOW:  %The Byte Or Word bit is set to 1 if the  DMA con`troller transfers a byte in a  DMA cycle. It is set to 0 if a word is  trans`ferred. The DMA con`troller on  the PDQ-3 always transfers a byte.  .margin &   .page3  _4.11.1.2 Byte Count Registers_   .inx Byte Count Registers  %The high Byte Count and low Byte Count registers combine to form  the most and least signifi`cant bytes, respectively, of a 16-bit  byte count register. The 16-bit register is loaded with the two's complement  of the number of bytes in the DMA transfer, and is incremented each time  the DMA con`troller transfers a byte. When the 16-bit register reaches 0,  the DMA operation terminates, and the TCZI bit of the Status register is  set. If the TCIE bit of the Command register is set to 1, a processor  inter`rupt will also be generated.   %Each register is loaded independently, and can be loaded only when the  .inx DMA Status Register  Busy bit of the Status register is set to 0. Attempts to load these  registers while this bit is set to 1 are ignored by the DMA con`troller.    .page3  _4.11.1.3 Memory Address Registers_   .inx Memory Address Registers  .inx Memory  %The extension Address, high Address, and low Address  registers combine to form an 18-bit memory buffer address register.  This register is the address of a memory byte. Since addresses on the PDQ-3  are word addresses, a byte address is obtained from a word address by  adding the word address to itself. Note that the PDQ-3 uses only the low  order 17 bits of the 18-bit address.   %Each register is loaded independently, and can be loaded only when the  Busy bit of the status register is set to 0. Attempts to load these  registers while this bit is set to 1 are ignored by the DMA con`troller.    .page3  _4.11.2 Initialize d State_   %The DMA Floppy Disk Conroller is initialized by powering on, or by pressing  .inx Reset Button  the Reset button on the front console, or when  .inx System Status Register  .inx Floppy Data Register  .inx Floppy Status Register  .inx Floppy Command Register  .inx Floppy Select Register  .inx Track Register  .inx Sector Register  I/O Reset bit of the System Status register is set to 1. In the initialized  state, all drive select bits in the Drive Select register are set to 0, and  the Floppy Status register Not-Ready bit is set to 1. The Floppy Track, Sector,  and Data registers are undefined.   .inx Memory Address Registers  .inx Byte Count Registers  %The DMA controller Address registers are  set to 0, and the Byte Count registers are programmed for 65535 bytes.  The DMA controller status is inactive, with all interrupts disabled and the  Hold Bus and Write options enabled.    .page3  _4.11.3 DMA/Floppy Controller Interrupts_   .inx Interrupts  %Assuming the interrupt system is enabled,  the DMA controller may be programmed to generate processor interrupts under  any of the following conditions:   .margin(L+5)  .undent3  --~Termination of a floppy controller command.  This interrupt is enabled when the DIE bit  of the DMA Command register is set to 1. Note  that this bit must be set in order to generate  floppy interrupts whether or not a DMA transfer  is involved.   .undent3  --~Termination of a DMA transfer command. This  interrupt is enabled when the TCIE bit of the  .inx DMA Command Register  DMA Command register is set to 1. A  processor interrupt occurs whenever both the  .inx Byte Count Registers  high Byte Count and the low Byte Count registers  are 0.   .undent3  --~Time-out during a DMA transfer. This interrupt  is enabled when the TOIE bit of the DMA  Command register is set to 1. A processor  interrupt occurs whenever the memory does not  respond to the DMA controller within 5  microseconds.  .margin   .inx Interrupts  .inx Interrupt Vectors  %The DMA Floppy Controller interrupts through the interrupt vector at  location 0E hex.  When an interrupt occurs, the PDQ-3 interrupt system is disabled, and the  software interrupt handler is invoked.  All DMA interrupts must be specifically disabled by the software interrupt  handler before the PDQ-3 interrupt system is reenabled. A DMA interrupt  is disabled when a 0 is stored into the DMA status register bit  corresponding to the active interrupt. Moreover, if the interrupt is  .inx Byte Count Registers  caused because the Byte Count registers are 0, a nonzero quantity must  be loaded into one or both registers in order to preclude the interrupt's  re`occurrence. Note that if the DMA interrupt is not disabled in this  manner, a DMA interrupt will occur immediately upon reenabling the  interrupt system.    4.11.4 Floppy Disk Drive Interface   The PDQ-3 CPU provides a Shugart model 850/851 floppy disk drive interface  at the J-2 connector of the CPU module. This 50 pin card edge connector  is also pin for pin compatable with the shugart bus specification.  This interface is discribed in Table XXXXXX.  .option (F-)   Pin Number Sou rce description   2 - (alternate I/O connection) (not used)  4 - (alternate I/O connection) (not used)  6 - (alternate I/O connection) (not used)  8 - (alternate I/O connection) (not used)  10 - (alternate I/O connection) (not used)  12 drive Disk Change (not used)  14 - (alternate I/O connection)  16 CPU In Use (not used)  18 CPU Head Load (not used)  19 CPU VFOE *  20 drive Index  22 drive Ready  24 drive Sector (not used)  26 CPU Drive Select 1  28 CPU Drive Select 2  30 CPU Drive Select 3  32 CPU Drive Select 4  34 CPU Direction Select  36 CPU Step  38 CPU Write Data  40 CPU Write Gate  42  Drive Track Zero  44 Drive Write Protect  46 Drive Read Data  48 Drive Sep Data *  50 Drive Sep Clock *  .option  * These signals are used in the control of the Phase Locked Loop Module.  For more information on the PLL reference the PLL users guide.   4.11.4.1 Termination and Connection   Signal that are sourced by the CPU must be terminated at the drive. Signals  sourced by the drive and used by the CPU are already ter`min`ated.The output  signals are driven with an open collector wouput stage capable of sinking  a maximum of 40 ma. at a logic zero level or true state with a maximum  voltage of 0.4V measured at the driver.when the line driver is in a logical  one or false state, the driver is off and the collector current is a maximum  of 250 microamperes.As specified by Shugart these signals must be ter`min`ated  by a 150 ohm pull-up resistor. Connection can be provided by either flat  or twisted pair cable not in length excess of 10ft.    .page3  _4.12 CPU Module Serial Number_   %Each CPU Module has been assigned a unique serial number which can  be accessed via the HDT PROM. This serial number is located at word  address F5FF and may be read and used by applications software. ENDBUF ONE TWO BACK $EQUAL $TAG $CURSOR $CURSOR    ÿÿF$FJ­(0$@@@O.¹ ƒ¤6  .title PDQ-3 Hardware User's Manual  .subtitle Chapter Five: The Q-Bus  .odd  .inx Q-Bus  _5. THE Q-BUS_   .inx LSI-11 Bus  %The DEC LSI 11/23 Q-bus is an electrical signal convention utilized  by the DEC LSI family of computers to communicate with  memory and peripherals also  implementing the convention. The electrical signals presented to the  backplane by the PDQ-3 CPU module conform to the Q-bus conventions, thus  facilitating communi`cation between the PDQ-3 CPU Module and memory or  any other Q-bus  compatible peripheral in the backplane.   .inx Memory  %The Q-bus comprises an 18-bit multiplexed address and data bus, Q-bus  control signals, power, and ground. It enables  memory and controller modules, which operate at different speeds, to communicate  with each other by an interlocking handshaking pro`tocol. This pro`tocol  includes data input and output in either word or byte modes, proces`sor service  interrupt requests, and direct memory access (DMA) bus requests.   .inx Bus Master  .inx CPU Module  .inx I/O Devices  %The PDQ-3 CPU Module is the default Q-bus  master, but a Q-bus compatible I/O device  controller may request and be granted temporary control of the bus for  a DMA oper`ation. The PDQ-3 CPU module is compatible with all devices  designed to operate on the LSI 11/23 Q-bus. %  .inx Priority  .inx Daisy Chain  %Both interrupt requests and the DMA requests are prior`itized using a  daisy-chain method. The controller that is elec`trically closer to the  proces`sor has the higher priority  (see section 3.1.2). The bus is designed so that any  bus-`compatible module may be inserted into any bus location and still receive  interface signals. How`ever, the module's priority will change according to its  location relative to the CPU module.   .page15   .skip13  .inx Q-Bus  .indent24  Figure 5.0.0 Q-Bus     .page3  _5.0 Module Bus Connection Pin Identification_   .inx Dual-Size Modules  .inx Quad-Size Modules  .inx Backplanes  %The Q-Bus accepts both dual size and quad size modules (see Figures  5.0.1.A and 5.0.1.B). A dual  size module requires two slots on the backplane module (slots A & B or  C & D); a quad  size module requires four slots on the backplane module (slots A, B, C, and  D). Each slot contains 36 connection pins: 18 on the component side of a  module (side 1), and 18 on the solder side (side 2). Each pin in a slot is  identified by a letter of the alphabet from A to V (excluding G, I, O, and Q),  starting from the right on the component side. Hence, the rightmost pin of  slot A on the component side is AA1. The first A refers to Slot A; the  second A refers to Pin A; the number 1 refers to the component side.  Likewise, the third pin from the right, on slot D, on the solder side, is  DC2.   .page17   .skip14  .indent21  A) Slot A B) Slot B   .inx Dual-Size Modules  .indent11  Figure 5.0.1.A Dual Size Module Configuration   .page18   .skip14  .indent21   A) Slot A C) Slot C  .indent21  B) Slot B D) Slot D   .inx Quad-Size Modules  .indent11  Figure 5.0.1.B Quad Size Module Configuration   .inx BSYNC  .inx Pin Assignments  %The bus is designed so that corresponding pins of slots A and C, and slots  B and D, are as`signed identical signal names. For example, the bus  synchron`ization control signal (BSYNC~L) is as`signed both to pin AJ2 and  CJ2. Note that modules are polarized by a notch between two adjacent slots.  This notch acts as a key to mate with a protrusion on the connector block  for correct module positioning. Table 5.0 lists the backplane pin assignments  for slots A and B. The pin assignments for slots C and D are identical to  those for slots A and B. "  .inx Active State  %NOTE: The trailing L (low) or H (high) of a  signal mnemonic indicates the active state of  the signal.   .page10  .inx Backplanes  .inx Pin Assignments  =Table 5.0 5Backplane Pin Assignments    BUS PIN MNEMONIC DESCRIPTION   .margin(L+25)  .undent25  AA1 BIRQ5~L Interrupt Request Priority 5. Not used by the PDQ-3. !  .undent25  AB1 BIRQ6~L Interrupt Request Priority 6. Not used by the PDQ-3. !  .undent25  AC1 BDAL16~L  .undent25  AD1 BDAL17~L Extended address bits.   .undent25  AE1 SSPARE1   .undent25  AF1 SSPARE2  .undent25  AH1 SSPARE3 Unassigned, unbussed special spares. A`vail`able for  user interconnections.   .inx GND  .undent25  AJ1 GND System signal ground and DC return.    .undent25  AK1 MSPAREA  .undent25  AL1 MSPAREA Maintenance spares. Normally connected  on the back`plane at each option location.   .undent25  .inx GND  AM1 GND System signal ground and DC return.   .inx DMA Devices  .inx Bus Master  .inx BDMR  .undent25  AN1 BDMR~L Direct Memory Access (DMA) Request. A device asserts  this signal to request control of the bus. The CPU arbitrates  bus mastership between itself and all  the DMA devices on the bus. If the processor is to relinquish bus mastership  it grants bus mastership to the electrically closest requesting device by  asserting BDMGO~L. The device responds  by negating BDMR~L and asserting BSACK~L. *  .inx Interrupts  .inx BHALT  .undent25  AP1 BHALT~L Processor halt. When BHALT~L is  asserted, the proces`sor responds by halting  normal program execution. Interrupts are latch`ed, and DMA request/grant  sequences are enabled.   .undent25  AR1 BREF~L Memory refresh. Not used by the PDQ-3.   .undent25  AS1 +5B or +12B Battery Backup Power. !  .inx GND  .undent25  AT1 GND System signal ground and DC return. !  .undent25  AU1 PSPARE1 Unassigned spare. Usage not recommended. !  .inx Battery Power  .undent25  AV1 +5B +5V battery power. Secondary +5V power  connection. Battery power may be used with certain devices. @  .inx Power, DC  .inx BDCOK  .undent25  BA1 BDCOK~H DC power ok. Asserte d by the power  up/`down sequence logic of the primary back`plane when there is sufficient DC  voltage available to reliably sustain sys`tem  oper`ation. A  .inx Power Supplies  .inx BPOK  .inx Power Fail  .undent25  BB1 BPOK~H Power ok. Asserted by the power up/`down  sequence logic of the primary back`plane when power supply is normal. If negated  during proces`sor oper`ation, a power fail interrupt sequence is initiated. @  .undent25  BC1 SSPARE4  .undent25  BD1  SSPARE5  .undent25  BE1 SSPARE6  .undent25  BF1 SSPARE7  .undent25  BH1 SSPARE8 Unassigned, unbussed special spares.  A`vail`able for user interconnections.   .inx GND  .undent25  BJ1 GND System signal ground and DC return.   .undent25  BK1 MSPAREB  .undent25  BL1  MSPAREB Maintenance spare. Normally connected  on the back`plane at each option location.   .inx GND  .undent25  BM1 GND System signal ground and DC return.   .inx BSACK  .inx Bus Master  .inx DMA Devices  .undent25  BN1 BSACK~L Slave acknowledgement. Asserted by  a DMA device in response to the  proces`sor's BDMGO~L signal, indicating that the DMA device is the new  bus master. 7  .undent25  BP1 BIRQ7~L Bus interrupt request, priority 7.  Not used by the PDQ-3.   .undent25  BR1 BEVNT~L External event interrupt request. Not  used by the PDQ-3. 8  .undent25  BS1 PSPARE4 Unassigned spare. Usage not recommended. !  .inx GND  .undent25  BT1  GND System signal ground and DC return. !  .undent25  BU1 PSPARE2 Unassigned spare. Usage not recommended. !  .inx Power, DC  .undent25  BV1 +5  +5V DC sys`tem power. !  .inx Power, DC  .undent25  AA2 +5 +5V DC sys`tem power. !  .inx Power, DC  .undent25  AB2 -12 -12V DC power. @  .inx GND  .undent25  AC2 GND System signal ground and DC return. !  .inx Power, DC  .undent25  AD2 +12 +12V DC sys`tem power. !  .inx BDOUT  .inx Bus Master  .inx BDAL Lines  .inx Output Data  .undent25  AE2 BDOUT~L Data output. Asserted by the bus master  to imply that valid data is available  on BDAL0-15~L and that an output transfer is taking place. To complete the  transfer, the addressed device must acknowledge the receiving of data by  asserting BRPLY~L in response to BDOUT~L. 9  .inx BRPLY  .inx Interrupt Acknowledge  .inx Input Data  .inx Output Data  .undent25  AF2 BRPLY~L Reply. Asserted in response to BDIN~L  or BDOUT~L and during interrupt acknowledge. It is generated by an addressed  device to indicate that the device has input data available on the BDAL bus or  that it has accepted output data from the bus. A  .inx Input Data  .inx BDIN  .inx Bus Master  .inx Interrupts  .undent25  AH2 BDIN~L Data input. BDIN~L is used for two types  of bus oper`ations: 9  .margin(L+3)  .undent3  --~When asserted by the bus master  during BSYNC~L time, implies an input  trans`fer and requires a response. BDIN~L is  asserted when the master device is ready to accept data from a addressed  device.   .undent3  --~When asserted without BSYNC~L, it in`di`cates that an interrupt oper`ation  is in pro`gress.  .margin ;  .inx BSYNC  .inx BDAL Lines  .inx Bus Master  .undent25  AJ2 BSYNC~L  Synchronize. Asserted by the bus master  to indicate that it has placed an address on BDAL0-15~L and initiate an input or  output bus cycle. The cycle is in pro`gress until after the master receives  BRPLY~L from the addressed device. @  .inx Output Data  .inx BWTBT  .undent25  AK2 BWTBT~L Write/byte. Used in two ways  to control a bus cycle:   .margin(L+3)  .undent3  --~It is asserted during the leading edge of BSYNC~L to indicate that an  output sequence is to follow, rather than an input sequence.   .undent3  --~It is asserted during BDOUT~L, in a DATO bus cycle, for byte addressing.  .margin ;  .inx BIRQ  .inx Interrupts  .inx Input Data  .inx Output Data  .undent25  AL2 BIRQ~L Interrupt request. A device asserts this  signal when its in`ter`rupt enable and in`ter`rupt request flip-flops are set  to inform the pro`ces`sor that the device needs pro`ces`sor service. The  pro`ces`sor asserts BDIN~L and BIAKO~L to acknow`ledge the re`quest. @  .inx Interrupt Acknowledge  .inx Interrupts  .inx Priority  .inx BIAKI  .inx BIAKO  .undent25  AM2 BIAKI~L  .undent25  AN2 BIAKO~L Interrupt Acknowledge Input and Interrupt Acknowledge  Output. These signals are gen`er`ated by the pro`ces`sor in response  to an in`ter`rupt request (BIRQ~L). The pro`ces`sor asserts BIAKO~L, which is  routed to the BIAKI~L pin of the first device on the bus. If that device is not  assert`ing BIRQ~L, the device will pass BIAKI~L to the next lower priority  device via its BIAKO~L pin and the lower  priority de`vice's BIAKI~L pin. If it is requesting an in`ter`rupt, it will not  assert BIAKO~L. @  .inx BBS7  .inx Bus Master  .undent25  AP2 BBS7~L Bank 7 select. Asserted by the bus master  when an address is placed on the bus which is in the upper 4K words of memory  (ad`dres`ses F000 hex to FFFF hex; nor`mal`ly reserved for memory mapped  I/O). BSYNC~L is then asserted and BBS7~L re`mains active  during the addressing por`tion of the bus cycle. @  .inx DMA Devices  .inx BMGI  .inx BMGO  .undent25  AR2 BDMGI~L   .undent25  AS2 BDMGO~L DMA Grant Input and DMA Grant Output.  This signal is gen`er`ated by the pro`ces`sor to grant bus mastership to the  highest priority  DMA device on the bus. The pro`ces`sor routes the BDMGO~L signal to the  BDMGI~L pin of the first device on the bus. If this device is not requesting  bus control, it passes the signal to BDMGI~L pin of the next device on the  bus. How`ever, if the device is requesting bus control, it will inhibit the  passage of the BDMGO~L signal to the next device. @  .inx BINIT  .inx Reset Button  .inx Backplanes  .inx Powering Up  .undent25  AT2   BINIT~L Initialization. Asserted by one of the following:  .margin(L+5)  .undent3  --~the pro`ces`sor  .undent3  --~the RESET switch on the front  panel  .undent3  --~the primary back`plane during  the pow`er up/`down logic sequence  .margin  ...in order to clear or initialize all devices in the sys`tem. A  .inx Data/Address Lines  .inx BDAL Lines  .inx Bus Master  .inx Output Data  .inx Input Data  .undent25  AU2 BDAL0~L  .undent25  AV2 BDAL1~L Data/Address Lines. These two lines  are part of the 18-line data/address  bus over which data and address information is transmitted. Address  information is first placed on the bus by the bus master device. Then the  master device either receives data from, or  outputs data to the addressed device or memory over the same bus lines. @  .inx Power, DC  .undent25  BA2 +5 +5V DC system pow`er.   .inx Power, DC  .undent25  BB2 -12  -12V DC pow`er. A  .inx GND  .undent25  BC2 GND System signal ground and DC return.   .inx Power, DC  .undent25  BD2 +12 +12V DC system pow`er.   .inx Data/Address Lines  .inx BDAL Lines  .undent25  BE2 BDAL2~L  .undent25  BF2 BDAL3~L  .undent25  BH2 BDAL4~L  .undent25  BJ2 BDAL5~L  .undent25  BK2 BDAL6~L  .undent25  BL2 BDAL7~L  .undent25  BM2 BDAL8~L  .undent25  BN2 BDAL9~L  .undent25  BP2 BDAL10~L  .undent25  BR2 BDAL11~L  .undent25  BS2 BDAL12~L  .undent25  BT2 BDAL13~L  .undent25  BU2 BDAL14~L  .undent25  BV2 BDAL15~L Data/Address Lines. These 14 lines are  part of the 18-line data/address bus de`scribed for BDAL0 and BDAL1.  .margin A $EQUAL $CURSOR Ú(@@@O.¹ ƒ¤!!  .title PDQ-3 Hardware User's Manual  .page3  _5.1 Bus Cycles_   .inx Instruction Cycle  .inx CPU Module  .inx Interrupts  .inx I/O Devices  %Each processor instruction requires at least one I/O oper`ation. The first  is a data input, which fetches an instruction from the location addressed  by the program counter. This oper`ation is called a DATI bus cycle. If no  additional operands are referenced in memory or in an I/O device, no  additional bus cycles are required for instruction execution. However, if  additional memory or devices are referenced, additional data input/`output or  data transfer cycles are required. Between processor bus cycles, the bus is  available for DMA access. In addition, interrupt requests may be serviced  prior to instruction fetches. The following  sections describe the types of bus cycles. It should be noted that the bus  sequences for I/O operations between processor and memory or I/O devices are  ident`ical.    .page3  _5.1.0 DATI Operations_   .inx DATI Cycle  .inx Input Data  .inx Interrupts  .inx Memory  .inx BDAL Lines  .inx BSYNC  .inx BDIN  .inx BRPLY  %The DATI cycle (see Figure 5.1.0) is  asyn`chronous and requires a re`sponse from the addressed device or memory.  An address is put onto the BDAL lines, and the BSYNC L signal is asserted. The  addressed device or memory responds to an input request (BDIN~L) by putting  the data on the bus lines and then asserting BRPLY~L. Upon receiving BRPLY~L,  the processor terminates the cycle by negating BDIN~L and BSYNC~L.  If BRPLY~L is not asserted within 15 micro`seconds after BSYNC~L,  the processor terminates the DATI oper`ation,  .inx Bus Error  and executes a bus-error inter`rupt through  location 2.   .page4   .indent22  (Provided as addendum)   .indent20  Figure 5.1.0 DATI Sequence    .page3  _5.1.1 DATO Operations_   .inx DATO Cycle  .inx Output Data  .inx Memory  .inx BDAL Lines  .inx BSYNC  .inx BWTBT  .inx DATOB  .inx BDOUT  %The DATO cycle (see Figure 5.1.1) is asyn`chronous, and re`quires a  response from the addressed de`vice or memory. An address is put onto  the BDAL lines and the BSYNC L signal is asserted. BWTBT~L is asserted during  the addressing portion of the cycle to indicate that an output data  transfer is to follow. If a DATOB (DATO Byte) is to be executed,  BWTBT~L remains active  for the rest of the bus cycle. However, if a DATO is to be executed, BWTBT~L  is negated and remains so for the rest of the bus cycle.  The addressed device or memory responds to an output re`quest (BDOUT~L)  by accepting the data and then asserting BRPLY~L. Upon receiving BRPLY~L,  the processor terminates the cycle by negating BDOUT~L and BSYNC~L.  If BRPLY~L is not asserted within 15 micro`seconds after BSYNC~L,  the processor terminates the DATO oper`ation,  .inx Bus Error  and executes a bus-error inter`rupt through  location 2.   .page4   .indent22  (Provided as addendum)   .indent20  Figure 5.1.1 DATO Sequence    .page3  _5.2 DMA Operations_   .inx DMA Devices  .inx Memory  .inx I/O Devices  %DMA I/O operations involve both memory and peripheral devices. These devices  may transfer data to or from any address in the add" ress space, including the  I/O addresses. The sequence of operations involved in executing a DMA data  transfer is as described for input and output bus cycles (see section 3.1),  except that the DMA  .inx Bus Master  device, not the processor, is the bus master. Memory ad`dressing, timing, and  control signal gen`eration and response are provided by the logic contained on  the DMA device's interface module. The processor is not involved with address  or data transfers during such operations. Figure 5.2.0 illustrates in detail  how a DMA bus request sequence occurs.   .inx Backplanes  .inx BDMGI  .inx BDMGO  %Note that because of the daisy chain in`volving the BDMGI L and the BDMGO L  signals, all Q-Bus back`plane slots between the processor and the DMA module  must be filled. Other`wise, the daisy chain is broken and no DMA grant is  re`ceived.    .indent22  (Provided as Addendum)   .indent10  Figure 5.2.0 DMA Bus Request Sequence    .page3  _5.3 Interrupts_   .inx Interrupts  %Interrupts are requests made by peripheral devices which cause the processor  to temporarily suspend its program execution in order to service the  interrupting device. Each device has its own service routine which it enters  once its interrupt request has been acknowledged by the processor. After  completion of this routine, program control is returned to the interrupted  program. Such interrupts are useful when dealing with peripheral devices  that operate much more slowly than the processor itself.   %A device may generate an interrupt request at any time; however, it  can interrupt the processor only when interrupts are enabled and  the device is the elec`trically  closest interrupting device to the processor on the bus.  When the interrupt sysyem is disabled, interrupts are latched but not  serviced.   .inx DATI Cycle  .inx Interrupt Vectors  %Associated with each device is an interrupt vector that is hard-`wired into  the device's interface/`control logic. This vector is an address pointer that  allows automatic entry into a service routine without device polling. A  .inx BIRQ  .inx BIAKI  de`vice inter`rupts the processor by asserting BIRQ~L. The processor  acknow`ledges the inter`rupt by asserting BIAKO~L. The first device on the  bus receives this signal at its BIAKI~L input. If this de`vice is not  re`questing ser`vice, it passes the sig`nal via its BIAKO~L out`put to the  next de`vice on the bus. This daisy chain con`tinues until the sig`nal reaches  a de`vice re`questing ser`vice. This de`vice does not pass the BIAKO~L sig`nal,  and  re`sponds by as`serting BRPLY~L, and plac`ing its in`ter`rupt vec`tor ad`dress  .inx BDAL Lines  on the BDAL lines.   .inx Backplanes  .inx BIAKI  .inx BIAKO  %Note that because of the daisy chain in`volving the BIAKI L and the BIAKO L  signals, all Q-Bus back`plane slots between the processor and the  interrupting module  must be filled.  Other`wise, the daisy chain is broken and no  interrupt acknowledge is re`ceived.   .indent22  (Provided as Addendum)   .inx Interrupts  .indent14  Figure 5.3.0 Interrupt Timing Sequence    .page3  _5.4 Bus Initialization_   .inx Rese# t Button  .inx BINIT  %The Q-Bus control signal BINIT L is asserted whenever the RESET button  on the front panel is depressed. It will hold the system in the  initial`ized state until the button is re`leased. The ability to reset  the system without powering the system down is not avail`able in DEC`s  Q-Bus line of computers. This feature is in`corporated by ACD to facilitate  system reset without powering down, and hence preventing a loss of data.  .inx DMA Controller  However, some devices, such as an intelli`gent DMA con`troller, may lock  up the bus if a manual asyn`chronous reset is generated while DMA  oper`ations are being per`formed. In this case, a system power down is  necessary to rein`itialize the con`troller.   %The system may also be reset under soft`ware control. In this case,  every device on the bus, except the CPU chip set, is initial`ized. This  .inx System Status Register  is accomplished by setting the INIT bit of the System Status Register  (see section 6.7).    .page3  _5.5 Power-up/Power-down Sequence_   .inx Powering Up  .inx Powering Down  .inx BPOK  .inx BDCOK  %The power status signals BPOK H and BDCOK H are used to control a power  up or power down sequence as power is applied or removed, so that the  system may carry out an orderly start up or shut down.   .inx BINIT  .inx Backplanes  .inx Power Supplies  .inx Power, DC  %During a power up  sequence, BPOK H, BDCOK H, and BINIT L are low. Approximately 3  milli`seconds after the DC power supply (supplies) outputs rise to their  proper voltage levels and are stable, the power supply (supplies) asserts  the signal PF. Upon receiving PF, the primary backplane power up/down  logic sequence drives both BDCOK H and BINIT L high. After a delay of  another 70 milli`seconds, the logic drives BPOK H high. At this point,  the PDQ-3 CPU processor begins to execute its power up routine.   %A power down sequence occurs when the power supply (supplies) detects the  AC power dropping below its operating limit. The power supply (supplies)  begins the sequence by negating PF. This causes BPOK H to be negated and  causes the processor to execute a power fail interrupt through word location  6. Approximately 3 milli`seconds later, the primary backplane logic drives  both the BDCOK H and BINIT L low.    .page3  _5.6 Halt Mode_   .inx Run/Halt Button  .inx BHALT  .inx Interrupts  %The processor is placed in Halt mode by asserting BHALT~L. This occurs  the Run/Halt button on the front panel is pressed.  While the processor waits for ne`gation of BHALT~L,  DMA requests and refresh operations  still occur, and interrupts are latched, but not ex`ecuted.   .page3  _5.7 Memory Refresh_   .inx Memory  .inx Memory Refresh  %The PDQ-3 CPU Module does not pro`vide memory re`fresh control  signals (BREF~L is perman`ently negated). Thus, any dynamic  semi`conductor memory module used  with the PDQ-3 must provide its own memory refresh logic.    .page3  _5.8 Bus Configuration   .inx Configuration  %The following sections describe  methods of Q-Bus termination recommended for the PDQ-3 systems.  Each Q-Bus signal $ (excluding the SPARE signals)  is terminated by a 250 Ohm termination resistor on the CPU board (see  Figure 5.8.0).   .page14  .option(F-) &With Primary With Primary And %Backplane Only Secondary Backplanes ( *+5V +5V 1 %390 390 3250 Ohm Bus 120 Ohm Bus 3terminations terminations %680 680    .option    .indent18  Figure 5.8.0 Bus Terminations   $LAST A $EQUAL $CURSOR $TAG LOOK LOOK1 LOOK2 @@@O.«¡ƒ¤+ .title PDQ-3 Hardware User's Manual  .input (H` U_ B~)  .paragraph (F% I5)  .margin (L5 R72)    .page3  _4.9.1.2 Interval Timer_   .inx Interval Timer  %This counter is loaded by the system or application as required.  The input clock to this counter is the System clock pulse.  Assuming the System clock pulses at 10 ms intervals, the  Interval Timer may be programmed to  produce time-out intervals from 10ms to 10 minutes. To generate an  arbitrary interval pulse, the Interval Timer counter register is loaded  with the Interval Factor (IF), computed as follows: :  .indent27  IF = 100 x I   % 'I' is the time-out  interval in seconds. Thus, to generate a pulse of 1 second (IF = 100 x 1 = 100),  the Interval Timer counter register is loaded with 100.  The Interval Timer is programmed either to restart itself when it counts  down to zero (using  mode 010) or to terminate on the first pulse (using mode 000).  %  %When the Interval Timer counter register counts down to zero, the  .inx System Status Register  Interval Timer bit in the System Status register (see section 4.7) is set. If  interrupts are enabled, an interrupt will be generated through location  1E hex.   _4.10 Console Controller_   %The PDQ-3 RS-232c Console Controller is a WD1931 USART located onboard the  PDQ-3 CPU Module. It supports ful duplex com`mun`i`cation with the console  at speeds ranging from 50 to 19,000 bits per second. Recommendations for  cabling between the PDQ-3 CPU Module and the operator's console are found  in Appendix D>   .page3  _4.10.0 USART Registers_   .inx USART  .inx USART Interface Registers  %The USART provides five 8-bit interface  registers. Com`muni`cation with the USART registers may be carried  on in either  the word or byte mode. Significant data always occupies the low order byte,  and the value of the high order byte is undefined.   %Table 4.10 lists the USART registers accessible by the proces`sor.   .page12  .inx USART Control Register #1  .inx USART Control Register #2  .inx USART Status Register  .inx Transmitter Holding Register  .inx Receiver Holding Register  .option(F-)  *REGISTER ADDRESS ACCESS I(Word)  'Control Register #1 FC10 Read/write  'Control Register #2 FC11 Read/Write 'Status Register FC12 Read only 'Transmitter Holding Register FC13 Write only 'Receiver Holding Register FC13 Read only    .option  .indent20  Table 4.10 USART Registers   .page3  _4.10.0.0 Control Registers_   %The two 8-bit Control registers hold device programming information such  as mode selection, interface signal control, and data format.    .page3  _4.10.0.0.0 Control Register #1_   .inx USART Control Register #1  %The USART Control register #1 is used to define line proto`col and data  con`trol func`tions. It is de`fined as fol`lows:   .page4  .option(F-) @BITS !----7-------6-------5-------4-------3------2------1-------0---- !! LOOP ! BRK ! MISC ! ECHO ! PE ! RE ! RTS ! DTR ! !---------------------------------------------------------------  .option G  .margin(L+5)  .page2  .undent3  --~LOOP:  %The Loop/Normal bit allows all data sent to the trans`mitter to  appear at the receiver, thus forming an internal diagnostic  data loop. When this bit is set to 1, the loop is  .inx Interrupts  activated and ring interrupts are dis`abled. When this bit  is set to 0, the ring interrupt is enabled and the  USART is configured to operate in normal full duplex mode.   .page2  .undent3  --~BRK:  %The Break bit allows the trans`mitter output line to be held in  a continuous space state start`ing at the next char`acter.  When this bit is set to 0 and  the trans`mitter is enabled, the trans`mitter acts  normally except that the trans`mitter output line is held in  the spacing state.   .page2  .inx Character Length  .inx Stop Bit  .undent3  --~MISC:  %This bit determines the number of stop bits to be  transmitted with each character. When this&  bit is set to  0, a single stop bit is transmitted.  When this bit is set to 1, two stop bits are transmitted  with each character 6, 7, or 8 bits long, and 1.5 stop bits  for characters 5 bits long. )  .page2  .undent3  --~ECHO:  %The Echo Mode bit allows data on the receiver input line to be  duplicated on the trans`mitter ouput line.  When this bit is set to 0 and the receiver is  enabled, the clocked regenerated data is presented to  the Transmitted Data output.   .page2  .inx Parity  .undent3  --~PE:  %The Parity Enable bit enables checking of the parity on received  char`acters and generation of parity on transmitted  char`acters. When this bit is set to 0, parity  checking/`generation is enabled. When this bit is set to 1,  parity checking/`generation is disabled.   .page2  .undent3  --~RE:  %The Receiver Enable bit controls the receiver logic.  When this bit is set to 0, characters may be  .inx Receiver Holding Register  .inx USART Status Register  placed in the Receiver Holding register and Status  register bits 1 through 4 may be updated. When this  bit is set to 1, status bits 1-4 are cleared and the  receiver is disabled.   .page2  .undent3  --~RTS:  %The Request To Send bit controls the data set CA circuit.  This bit must be set to 0 and the Clear To Send input  must be asserted for the trans`mitter to be enabled.  When this bit is set to 1, the trans`mitter is disabled  and the RTS output is turned off at the completion of  any current character trans`missions.   .page2  .undent3  .inx DTR  --~DTR:  %The Data Terminal Ready bit controls the data set CD circuit.  When set to 0, Carrier, Data Set Ready, and Ring  interrupts are enabled. When set to 1, the  Ring interrupt is enabled.  .margin    .page3  _4.10.0.0.1 Control Register #2_   .inx USART Control Register #2  %The USART Control register #2 controls the data format and  transmission/`receive rates. It is defined as follows:   .page4  .option(F-) ABITS !----7-------6-------5--------4--------3--------2-----1-----0----- !! CHAR LENGTH ! MODE ! ODD/EVN ! RX CLK ! CLOCK SELECT ! !-----------------------------------------------------------------  .option !  .margin(L+5)  .page2  .inx Character Length  .undent3  --~CHAR LENGTH:  %The Character Length bits select the number of bits per  character as follows:   .page4  .option(F-) 400 - five bits 401 - six bits 410 - seven bits 411 - eight bits  .option   .page2  .undent3  --~MODE:  %The Character Mode bit configures the USART for  asyn`chronous character mode. This bit is set to 1  on the PDQ-3. (Synchronous character mode is not used.)   .page2  .inx Parity  .undent3  --~ODD/EVN:  %The Odd/Even bit determines the transmit/`receive  parity. When this bit is set to 0, odd parity is  generated/`expected. When this bit is set to 1,  even parity is selected.   .page2  .inx Clocks  .undent3  --~RX CLK:  %The alternate RX clock bit determines the separate receive  data clock rate. This feature is not used on the  PDQ-3 and this bit must always be set to 1.   .page2  .inx Baud Rate  .inx Baud Rate Generator  .inx Clock' s  .undent3  --~CLOCK SELECT:  %These bits select the transmit and receive clocks, and must  always be set to 110 on the PDQ-3. This allows the  Baud Rate generator (see section 4.9.1.0) to determine  both clock rates.  .margin    .page3  _4.10.0.1 Status Register_   .inx USART Status Register  %The USART Status register contains information relating to the status of the  USART. It is defined as follows: !  .page4  .option(F-) >BITS  ----7-------6-------5-------4-------3-------2-------1-------0----  ! DSC ! DSR ! CD ! FE ! PE ! OE ! DR  ! THRE !  -----------------------------------------------------------------  .option   .margin(L+5)  .page2  .undent3  --~DSC:  %The Data Set Change bit is set to 0 after a change in  the state of either the DSR or CD control inputs (assuming  .inx USART Control Register #1  .inx DTR  the DTR bit in Control register #1 is programmed 0)  or Ring control input (assuming the DTR bit in Control  register #1 is programmed 1). This bit is set to 1 after  the Status register is read.   .page2  .undent3  --~DSR:  %The Data Set Ready bit is the Data Set Ready control input from  the Data Set.   .page2  .inx DTR  .inx Console CRT  .undent3  --~CD:  %The Carrier Detect bit is the Carrier Detect control input from  the Data Set.    .page2  .inx Stop Bit  .undent3  --~FE:  %The Framing Error bit is set to 0 if the receiver is enabled and  the last character received is found not to have a stop  bit. A framing error condition is cleared (this bit is set  to 1) when the receiver is disabled then reenabled.   .page2  .undent3  .inx Parity  --~PE:  %The Parity Error bit is set to 0 when the receiver and Receive  Parity are enabled and the last received character has  a parity error. A parity error condition is cleared (this  bit is set to 1) when the receiver is disabled and then  reenabled.   .page2  .undent3  --~OE:  %The Overrun Error bit is set to 0 when a character has been  .inx Receiver Holding Register  received and is ready to be trans`ferred to the Receiver  Holding register, but DR is set to 0 (indicating that the  proces`sor has not responded to the last character). In  this case, the newest character is lost. An overrun error  con`dition is cleared (this bit is set to 1) when the  receiver is disabled and then reenabled.   .page2  .undent3  --~DR:  %The Data Received bit is set to 0 when the receiver is enabled  .inx Receiver Holding Register  and the Receiver Holding register is loaded from the  Receiver. It is set to 1 when the Receiver Holding  register is read by the proces`sor or when the receiver  is disabled.   .page2  .undent3  --~THRE:  .inx Transmitter Holding Register  %The Trans`mitter Holding Reg`ister Emp`ty bit is set to 0  when the con`tents of the Trans`mitter Hold`ing Reg`ister  is trans`ferred to the trans`mitter reg`ister and  Trans`mitter is en`abled. It is set to 1 when the  Trans`mitter Hold`ing Reg`ister is loaded by the proces`sor  or when trans`mitter is dis`abled.  .margin !   .page3  _4.10.0.2 Trans`mitter Holding Register_   .inx Transmitter H( olding Register  %The Trans`mitter Holding register buffers data for trans`mission.  When the trans`mitter is not busy and the trans`mitter is  enabled, the contents of the Trans`mitter Holding register is trans`ferred to  the trans`mitter and a THRE condition is generated. Note that the Trans`mitter  Holding register is loaded with the 1's complement of the character to  be transmitted.    .page3  _4.10.0.3 Receiver Holding Register_   .inx Receiver Holding Register  %The Receiver Holding register buffers data received from the operator's  console. A DR status condition is generated when the Receiver  Holding register  is full. Note that the data contained in the Receiver Holding register is  the 1's complement of the data received.    .page3  _4.10.2 USART Interrupts_   .inx Interrupts  %Assuming interrupts are enabled (see section 4.3), the USART may generate  proces`sor interrupts under one of three conditions:   .margin(L+5)  .undent3  .inx Transmitter Holding Register  1) The Trans`mitter Holding register is empty. An inter`rupt  is generated through location 12 hex. Note that this inter`rupt  is continuously generated until either the Trans`mitter  .inx USART Control Register #1  Holding register is full, the trans`mitter is disabled (see  the RTS bit of Control register #1), or interrupts are  disabled.   .undent3  .inx Receiver Holding Register  2) The Receiver Holding register is full. An interrupt is  generated through location OE hex.   .undent3  .inx DTR  3) The Carrier Detect Signal or the Data Set Ready  signal has changed. An inter`rupt is gen`erated through loca`tion 16 hex.  This inter`rupt is con`tinuously gen`erated until either inter`rupts are  dis`abled, the USART status register is read, or location FC1A is read.  .margin $LAST $EQUAL $CURSOR jjO.«¡¥B)  .form ([// #30 /// l56 // E #30 ///]  + [// #20 /// l56 // #30 #63 E ///])  .option(F-)  .input (H`)             _CPU HARDWARE USER'S MANUAL_   VERSION 1.1   March, 1982   Advanced Computer Design  .option  .skip8  PDQ-3 is a registered trademark of Advanced Computer Design.   Information furnished by ACD is believed to be accurate and  reliable. However, no responsibility is assumed by ACD for  its use; nor for any infringements of patents or other  rights of third parties which may result from its use. No  license is granted by implication or otherwise under any  patent or patent rights of ACD. ACD reserves the right to  change product specifications at any time without notice.   DEC, LSI-11, LSI-11/23, LSI-11 Bus, and Q-Bus are registered  trade`marks of Digital Equipment Corporation, Maynard, Mass.   UCSD Pascal is a registered trade`mark of the Regents of the  University of California.    .option(F-)  Authors : (Alphabetically)  Jim Condit +Barry Demchak +Patricia Farwell +Charles P. Fort +Yu Hao Lin  Kevin Reilly   Part #: 01-09-0002   (c) Copyright 1981, Advanced Computer Design. All rights reserved.  "Duplication of this work by any means is forbidden without the (prior written consent of Advanced Computer Design. >  .form ([// #30 t /// l56 // E #30 pR ///]  + [// #20 s /// l56 // #30 pR #63 E ///])  .count 0  .page  .option(f- p-)  .subtitle PDQ-3 Hardware User's Manual  .subtitle Table of Contents `_page_   I. INTRODUCTION ...................................................1  .margin (L+5)   1.0 General...................................................1  .margin   II. SYSTEM OVERVIEW................................................3  .margin (L+5)   2.0 The PDQ-3T CPU Module Version.............................3   2.1 General Specifications ...................................3  .margin (L+5)   2.1.0 The CPU Module.....................................3   2.1.1 CPU Module Jumper and Switch Options...............4  .margin   2.2 The Memory Modules........................................7  .margin   III. Bootstrapping UCSD Pascal.....................................9  .margin (L+5)   3.0 BOOT PROMS- Bootstrapping UCSD Pascal.....................9  .margin   IV. THE PDQ-3 CPU MODULE...........................................13  .margin (L+5)   4.0 CPU Module Organization...................................13   4.1 Internal WD-Bus...........................................13  .margin (L+5)   4.1.0 WD-Bus Data/Address Signals........................14   4.1.1 SYNC...............................................14   4.1.2 DIN................................................14   4.1.3 DOUT...............................................14   4.1.4 REPLY..............................................15   4.1.5 W/R................................................15   4.1.6 BUSY...............................................15   4.1.7 RESET..............................................15   4.1.8 COMPUTE..........................................* ..16   4.1.9 INTERRUPT SENCE LINES..............................16   4.1.10 IACK..............................................16  .margin   4.2 Processor Chip Set........................................16  .margin (L+5)   4.2.0 Control Chip.......................................16   4.2.1 Data Chip..........................................17   4.2.2 Control Memory Chip................................17  .margin   4.3 Interrupt System..........................................17   4.4 Power Fail and Power Restart..............................18   4.5 Bus Error.................................................18   4.6 Interfacing the WD-Bus to the Q-Bus.......................19  .margin (L+5)   4.6.0 Address and Data Lines.............................19   4.6.1 Control Lines......................................19   4.6.2 Interrupt Lines....................................20   4.6.3 DMA Lines..........................................20  .margin   4.7 System Status Register....................................20   4.8 Environment Switch........................................22   4.9 Real Time Clocks..........................................23  .margin (L+5)   4.9.0  Mode Register......................................24   4.9.1 Using the Clocks...................................24  .margin (L+5)   4.9.1.0 Baud Rate Clock.............................25   4.9.1.1 System Clock................................25   4.9.1.2 Interval Timer..............................25  .margin (L-10)   4.10 Console Controller.......................................26  .margin (L+5)   4.10.0 USART Registers...................................26  .margin (L+5)   4.10.0.0 Control Registers..........................26  .margin (L+5)   4.10.0.0.0 Control Registers #1................26   4.10.0.0.1 Control Registers #2................28  .margin   4.10.0.1 Status Register............................28   4.10.0.2 Transmitting Holding Register..............30   4.10.0.3 Receiver Holding Register..................30  .margin   4.10.2 USART Interrupts..................................30  .margin   4.11 DMA Floppy Disk Controller...............................30  .margin (L+5)   4.11.0 Floppy Controller.................................30  .margin (L+5)   4.11.0.0 Drive Select Register......................31   4.11.0.1 Command Register...........................32  .margin (L+5)   4.11.0.1.0 Type I Commands.....................34  .margin (L+5)   4.11.0.1.0.0 Restore......................34   4.11.0.1.0.1 Seek.........................35   4.11.0.1.0.2 Step.........................35   4.11.0.1.0.3 Step In......................35   4.11.0.1.0.4 Step Out.....................35  .margin   4.11.0.1.1 Type II Commands....................35  .margin (L+5)   4.11.0.1.1.0 Read Sector Command..........36   4.11.0.1.1.1 Write Sector Command.........36  .margin   4.11.0.1.2 Type III Commands...................37  .margin (L+5)   4.11.0.1.2.0 Read Address.................37   4.11.0.1.2.1 Read Track...................38   4.11.0.1.2.2 Write Track...............+ ...38   4.11.0.1.2.3 Formatting...................39  .margin   4.11.0.1.3 Type IV Commands....................41  .margin   4.11.0.2 Status Register............................42  .margin (L+5)   4.11.0.2.0 Type I Command Status...............43   4.11.0.2.1 Type II and Type III Command Status.44   4.11.0.2.2 Type IV Command Status..............45  .margin   4.11.0.3 Data Register..............................45   4.11.0.4 Track Register.............................45   4.11.0.5 Sector Register............................45  .margin   4.11.1 DMA Controller....................................46  .margin (L+5)   4.11.1.0 DMA Control Register.......................47   4.11.1.1 DMA Status Register........................48   4.11.1.2 Byte Count Registers.......................49   4.11.1.3 Memory Address Registers...................49  .margin   4.11.2 Initialized State.................................49   4.11.3 DMA/Floppy Controller Interrupts..................50   4.11.4 Floppy Disk Drive Interface.......................50  .margin (L+5)   4.11.4.1 Termination and Connection.................51  .margin (L-10)   4.12 CPU Module Serial Number.................................51  .margin(L-5)   V. The Q-Bus.......................................................53  .margin   5.0 Module Bus Connection Pin Identification..................53   5.1 Bus Cycles................................................59  .margin (L+5)   5.1.0 DATI Operations....................................59   5.1.1 DATO Operations....................................60  .margin   5.2 DMA Operations............................................60   5.3 Interrupts................................................61   5.4 Bus Initialization........................................61   5.5 Power-Up/Power-Down Sequence..............................62   5.6 Halt Mode.................................................62   5.7 Memory Refresh............................................62   5.8 Bus Configuration.........................................62  .margin (L-10)   Appendix A Hexadecimal Debugging Tool (HDT)........................65   Appendix B Reserved Memory Locations...............................67   Appendix C Recommended CRTs........................................69   Appendix D Cabling Recommendations.................................71   Appendix E References..............................................73   Appendix F The Memory Modules......................................75         , $LAST $EQUAL $CURSOR ONE TWO   Ob«¡¥( .option (S1 F+)  .title PDQ-3 Hardware User's Manual  .input (H` U_ B~)  .paragraph (F% I5)  .margin (L5 R72).subtitle Chapter One: Introduction  .odd  .form ([// #30 t /// l56 // E #30 'Page ' p ///]  + [// #20 s /// l56 // #30 'Page ' p #63 E ///])  .count 1  _1. INTRODUCTION_   .inx UCSD Pascal  .inx LSI-11 Bus  .inx Q-Bus  %This manual is designed to be used as an aid in the instal`lation,  configur`ation, and oper`ation of the PDQ-3 CPU Module. Knowledge of the  Q-Bus or LSI-11 Bus, UCSD Pascal language, or UCSD operating system  is not required for  the use of this manual. For more information on these subjects, please  .inx Reference Materials  refer to the reference mater`ials listed in Appendix E.     .page3  _1.0 General_   .inx UCSD Pascal  .inx CPU Module  The CPU is a 16-bit  MOS microprocessor, microcoded to execute the UCSD Pascal Version III.0  P-code. In addition, the CPU includes hardware floating point (IEEE draft  standard), integer arithmetic, and mul`tiply and div`ide instructions.  The CPU Module board contains the microprocessor, a DMA floppy controller,  .inx RS-232C  .inx Serial Number  an RS-232C terminal interface, a real time clock, an interval timer, and  an optional low level debugger. Each CPU Module is assigned a unique  serial num`ber acces`sible to the software.   Figure 1.0 Block Diagram of the PDQ-3 Computer System   - BACK $EQUAL $CURSOR ÿÿÿÿJtt@@@O.«¡¥5 .option (S1 F+)  .title PDQ-3 Hardware User's Manual  .input (H` U_ B~)  .paragraph (F% I5)  .margin (L5 R72)  .subtitle Chapter Two: System Overview  .odd  _2. SYSTEM OVERVIEW_   .page3  _2.0 The PDQ-3 CPU Module Version_   .inx CPU Module  .inx Bootstrapping  %Under this version the buyer purchases  only the CPU Module. This version is avail`able in five models.  Each in`cludes the CPU, the Real Time Clock, the Interval Timer, the RS-232C  con`troller, and the double density DMA floppy disk con`trol`ler.  The models differ only in their boot`strap`ping ROMs.   .margin(L+5)  .inx Floppy Disk Controller  .undent3  --~The~PDQ-3/1.~~The  boot`strap`ping ROM provided with this model boots from the on-board  floppy disk con`trol`ler.  .undent3  --~The~PDQ-3/2.~~The  boot`strap`ping ROM provided with this model  boots from an RXV-01 floppy disk sub`system.   .undent3  --~The~PDQ-3/3.~~The  boot`strap`ping ROM provided with this model boots  from an RXV-02 floppy disk sub`system.   .inx Mass Storage  .undent3  --~The~PDQ-3/4.~~The  boot`strap`ping ROM provided with this model boots  from an RP-01 mass storage disk sub`system.   .undent3  --~The~PDQ-3/5.~~The  boot`strap`ping ROM provided with this model boots  from an RP-02 mass storage disk sub`system.  .margin   %The factory may be con`tacted for other boot`strap`ping re`quire`ments.      .page4  _2.1 General Specifications_    .page3  _2.1.0 The CPU Module_   .option ( F- )  .page10  .inx CPU Module  (A) CPU  .margin(L+5)   .inx Word Size  Word Size : 16 bits Instruction  .inx Instruction Length  Instruction Length : One to four bytes  .inx Instruction Cycle  Typical Instruction Cycle : 12 microseconds (based Con memory access time of C400 nsec)  .inx Addressing Range  Addressing Range : 64K words (with 4K words Cmemory mapped I/O)  .inx Interrupts  Interrupt Level  : BR4 only   .margin   .page11  .inx Serial Port Controller  (B) Serial Port Controller  .margin(L+. 5)   Interface : EIA RS-232C  .inx Baud Rate  Baud Rate : 50 to 19,200  Order  : Least significant bit first.  Distance : Depends on baud rate. >(see Appendix D)  .inx Character Length  .inx Parity  .inx Stop Bit  Character Format : 7 or 8 bits, no parity, two >stop bits.  .inx Console CRT  Console Signals : TD, RD, RTS, CTS, DTR, DSR, CD   .margin   .inx Floppy Disk Controller  .inx DMA Controller  .page12  (C) DMA Floppy Disk Controller  .margin(L+5)   .inx Floppy Disk Drives  Interface  : Shugart SA800/SA850, single/ >double density, single/double >sided, 8" soft sectored drives >with automatic Track 43 current >switching.  .inx Diskettes  Format : Software controlled IBM >formats : 1 (FM), 2 (MFM) H1D (FM), 2D (MFM)  Number of Drives : up to 4 single/double density, >single/double sided drives   .margin   .page7  .inx Power, DC  .inx Power Requirements  (D) DC Power Requirements  .margin(L+5)   +5V +/- 5% @ 2.80 Amp. Max.   +12V +/- 5% @ 0.15 Amp. Max.   -12V +/- 5% @ 0.04 Amp. Max.   .margin !  .page10  .inx Environmental Requirements  (E) Environmental Requirements  .margin(L+5)   .inx Temperature  Operating Temperature range  : Celsius : 0C to 50C DFahrenheit : 32F to 122F  Non-Operating Temperature Range : Celsius : -40C to 80C DFahrenheit : -40F to 176F  .inx Humidity  Humidity : 10% to 90% without Dcondensation  .inx Air Flow  Air Flow : 30 cubic feet/minute Dminimum is recommended   .margin   .inx Size Specifications  (F) Physical Size : One Quad-size card, D8.5" x 10.5" C   .page3  .inx CPU Module !2.1.1 CPU Module Jumper and Switch Options_   %The CPU Module is pictured in Figure ??????   .margin(L+5)  .undent3  .page3  .inx Jumpers  --~Jumpers:  .option  .inx HDT  .inx Powering Up  .inx Jumpers  .inx Bootstrapping  %The state of the PDQ-3 after power-up or reset is de`termined by the  con`nection of option jumpers E12 or E14 to jumper E13. If jumpers E14  and E13 are con`nected, the PDQ-3 comes up in the Hexadecimal Debugging  Tool (HDT) state (see Appendix A). If jumpers E12 and E13 are con`nected,  the PDQ-3 comes up in the auto`matic boot`strap`ping routine and boot`straps  from the approp`riate de`vice, de`pending on the version of the CPU module.  The CPU module is strapped with jumper E14 by the factory.   .inx Switches  .inx Baud Rate  .inx Console CRT  .undent3  .page3  --~System Environment Switches:   %Switches one(1) through three(3) select the baud rate for the con`sole  CRT, and should be set as shown in Figure 3.1.1. They are configured at the  factory for 9600 baud.   .inx Printer  Switches four(4), five(5), six(6) and seven(7) are unused and avail`able  for user appli`cations.  Switch eight(8) is used for maintenance, and should always  be on (open).  .margin   .page   .skip46  .inx CPU Module  .inx USART  .inx Floppy Disk Controller  .inx DMA Controller  .inx Floppy Disk / Drives  .inx Q-Bus  .inx Clocks  .inx Console CRT  .inx Jumpers  .inx Switches  .inx Micro-Engine  .option( F- ) )A) USART J) Floppy finger connectors )B) 1793 Floppy Controller K) Q-Bus finger connectors )C) 1883 DMA Controller L) System Environment Switches )D) 8253 Counter Timer M) Jumpers E12, E13, E14 )E-I) Micro-Engine Chip set N) Console plug /O) Bootstrapping Proms (IC-D7,D9)   .indent19  Figure ?????? The CPU Module  .page 0_BAUD_ _S1_ _S2_ _S3_ 1110 open open open 1300 closed open open 1600  open closed open 01200 closed closed open 02400 open open closed 04800 closed open closed 09600 open closed closed /19200 closed closed closed  4note: open = on, closed = off   .indent12  Figure ?????? Table of Switch Options: 1-3    .margin  2.2 THE MEMORY MODULES  .margin (l+5)   (A) Memory Capacity : 32K and 64K word  .Inx Memory Capacity C.configurations available.  (B) Read Access Time : 300 nsec. max. $Cycle Time : 500 nsec. max.  (C) Physical Size : One dual-size card.  (D) Electrical $Specifications : Refer to the Memory EModule technical manual.   C ONE TWO $EQUAL $CURSOR $CURSOR ‰¡ ÿÿMMGM#'O.Ø¡¥, .title PDQ-3 Hardware User's Manual  .margin (L5 R72)  .option (F+)  .input (H` U_ B~)  .paragraph (F% I5)  .subtitle Chapter Four: The PDQ-3 CPU Module  .odd  _4. THE PDQ-3 CPU MODULE_ @  .inx CPU Module  .inx WD-Bus  %This section describes the PDQ-3 CPU module. It contains descriptions of  the CPU module internal WD-Bus, major CPU module components, and  various internal architectural features.   .inx Q-Bus  .inx LSI-11 Bus  .inx UCSD Pascal  %The PDQ-3 computer module is electrically and mechan`ically  compatible with the Digital Equipment Corporation LSI 11/23 Q-bus (described  in chapter five; a  superset of the LSI-11/03 Q-bus) and executes the UCSD version III.0  P-code. The module implements the following 0 fea`tures:   .margin(L+5)  .option(F-)  --~Q-bus interface  --~Direct execution of UCSD version III.0 P-code  .inx System Clock Counter  .inx Interval Timer  --~Real-time clock with programmable interval timer  .inx Write Precompensation  .inx Floppy Disk Controller  .inx DMA Controller  --~Multiple unit floppy disk controller with DMA control`ler, #data separator, and write pre-compensation on double #density (The CPU can read double-density information with an #optional Phase Locked Loop)  .inx Memory  --~Non-existing device or memory detection  .inx Power Fail  .inx Interrupts  --~Power fail and recovery detection and interrupt  .inx HDT  --~1024 byte ROM with hardware debugger (HDT)  --~Vectored interrupts  .inx DMA Devices  --~DMA arbitration between multiple DMA devices  .inx Serial Port Controller  --~Programmable asynchronous serial I/O port  --~Programmed CLEAR function  --~Hardware NIL detection and interrupt  .option  .margin &   .page3  _4.0 CPU Module Organization_   .inx Micro-Engine  .inx WD-Bus  .inx USART  .inx Floppy Disk Controller  .inx DMA Controller  .inx Clocks  .inx Q-Bus  %The PDQ-3 CPU Module contains the WD 9000 MicroEngine proces`sor chip set, a  DMA Floppy controller, a USART, real time clocks, and a Q-bus interface.  The processor uses the internal WD-Bus to communicate with each on-board  device, and uses the Q-bus interface to communicate with any Q-Bus  devices. Each on-board device is assigned an address location in a  manner similar to devices on the Q-bus. Thus, communication between  .inx Memory  the processor and memory or I/O devices is routed first on the WD-Bus then,  if necessary, through the Q-bus interface onto the Q-bus.   .inx Clocks  %A 10 Megahertz crystal oscillator provides clocking for the processor and all  on-board devices. A 2.5 Megahertz four phase clock is derived from it for  the processor chip set.    .page3  _4.1 Internal WD-Bus_   .inx WD-Bus  .inx Data/Address Lines  .inx Bus Master  .inx DMA Controller  .inx Floppy Disk Controller  %The internal WD-Bus comprises 13 control signals and 16 multiplexed  data/address signals (see Table 4.1). The proces`sor is the default bus  master and, using the  WD-Bus, can control I/O between itself and any on-board or off-board  device. The on-board DMA controller can also gain temporary control of the  WD-Bus to transfer memory data to or from the Floppy disk controller.   .page23  .inx WDAL Lines  .option(F-)  %Signal Description  %WDAL0:15 data/address lines %SYNC bus syncronization %DIN data in control %DOUT data out control %REPLY address acknowledge %W/R write-not-read and byte control %BUSY processor wait control %RESET  processor reset %COMP processor active control %I0 interrupt request level 0 %I1  interrupt request level 1 (not used) %I2 interrupt request level 2 (not used) %I3 interrupt request level 3 (not used) %IACK interrupt acknowledge   .option   .inx SYNC  .inx DIN  .inx DOUT 1  .inx REPLY  .inx W/R  .inx BUSY  .inx RESET  .inx COMPARE  .inx IACK  .inx Interrupts  .inx Interrupt Acknowledge  .indent19  Table 4.1 WD-Bus Signals    .page3  _4.1.0 WD-Bus Data/Address Signals_   .inx WDAL Lines  .inx Data/Address Lines  .inx SYNC  .inx DIN  .inx DOUT  .inx REPLY  .inx W/R  %The WDAL0 through WDAL15 lines carry either a 16 bit address, an 8 bit  byte, or a 16 bit word of data depending on the state of the SYNC, W/R, DIN,  DOUT, and REPLY control signals.     .page3  _4.1.1 SYNC_   .inx SYNC  .inx Bus Error  %The SYNC control signal is used to initiate a data access  operation and  to control its duration. SYNC is asserted high by the processor  as soon as an address  becomes valid on the WDAL lines. This occurs at clock phase 2  during execution of an input or output operation. It remains high until  the termin`ation of the operation.   %If SYNC remains asserted longer than 15 micro`seconds, the bus error  re`covery logic is acti`vated (see section 4.5).    .page3  _4.1.2 DIN_   .inx DIN  .inx Input Data  .inx WDAL Lines  .inx I/O Devices  %The DIN (Data IN) signal is used by the proces`sor to signal  memory or an I/O device to put a byte or word on the bus.  During a read operation,  the proces`sor asserts DIN high either at the time the address is  secured from the WDAL lines or on the clock phase 2, fol`lowing the  .inx SYNC  asser`tion of SYNC (whichever is first). DIN  is negated low at the end of the data input operation or  when SYNC is negated low (whichever is first).    .page3  _4.1.3 DOUT_   .inx DOUT  .inx Output Data  .inx WDAL Lines  %The DOUT (Data OUT) signal is used by the proces`sor to signal the  addressed device that data is stable on the bus. During a write operation,  the proces`sor asserts DOUT  high during clock phase 1 when the write data is placed  on the  WDAL lines. It remains  asserted for the duration of the write operation and is negated one clock  phase prior to the removal of the data from the WDAL lines. The addressed  device uses this signal to clock data appearing on the WDAL  .inx Memory  lines into its selected memory or register location.    .page3  _4.1.4 REPLY_   .inx REPLY  .inx Bus Master  %The REPLY signal synchronizes the proces`sor to I/O oper`ations, thus  permitting  devices to  complete any required internal oper`ations related to the I/O operation prior  to the bus master's resumption of execution.  .inx I/O Devices  Assertion of REPLY by a memory or I/O device signals the proces`sor that the  I/O device has gated data  onto the bus in response to the assertion of DIN, or that the device has  accepted the data in response to DOUT.  The bus master interrogates the REPLY signal following  execution of an input or output operation and enters the Wait state on  each clock phase 3 until the REPLY signal is asserted by the addressed device.  The WD 9000 processor also interrogates the REPLY signal prior to the  execution of  input or write oper`ations at clock phase 3. If the CPU has not received  the REPL2 Y signal 15 microseconds after the SYNC signal is asserted, then the  bus recovery circuitry in activity is enabled and a Bus ERROR status is set.  (See section 4.5)    .page3  _4.1.5 W/R_   .inx W/R  .inx Floppy Disk Drives  %The W/R (Write-not-Read) signal is asserted high by the proces`sor  during the  device selection sequence to  signal the addressed device that a DOUT signal will follow immediately.  The  slave device may use the assertion or negation of W/R to initiate oper`ations  preparatory to an output or input oper`ation, re`spectively.   %The assertion of W/R during DOUT signals that a byte  .inx WDAL Lines  oper`ation is being performed, and the WDAL8:15 lines are auto`matically  .inx Micro-Engine  forced to zero (required by the MicroEngine chip set).    .page3  _4.1.6 BUSY_   .inx BUSY  %The BUSY signal is examined by the processor at clock phase 3 prior to an  input or output operation. If BUSY is found asserted high, the processor  enters the Wait state and does not attempt to use the WDAL bus lines or assert  any control signals until BUSY is negated.   .inx I/O Devices  .inx DMA Devices  %A DMA request from an I/O device causes BUSY to  be asserted. It will remain  asserted until the DMA operation completes and the DMA device relinquishes  control of the bus.    .page3  _4.1.7 RESET_    .inx RESET  .inx SYNC  .inx DIN  .inx HDT  %Assertion of the RESET signal causes the pro`ces`sor to enter a  reset state and tri-state both SYNC and DIN.  Sub`sequent negation of the  RESET signal causes the processor to enter into the HDT bootstrap  PROM. The CPU enters the RESET state when the BUS signal BINTL is  asserted.    .page3  _4.1.8 COMPUTE_   .inx COMPUTE  .inx Microinstructions  %Assertion of the COMPUTE signal causes the processor to execute  micro`instructions. It  is examined by the processor at each clock phase 1. If COMPUTE is found  negated low, the processor enters the Wait state thereby ceasing  execu`tion of the  micro`program. While in this state the processor continues to monitor  the COMPUTE signal at  each clock phase 1. When COMPUTE is found asserted high, the processor  resumes execu`tion of  the micro`program. COMPUTE is low when the processor is put into the Halt  .inx Run/Halt Button  mode by asserting BHALTL (Bus Halt).     .page3  _4.1.9 Interrupt Sense Lines_   .inx Interrupts  .inx Interrupt Acknowledge  .inx Interrupt Vectors  %There are four interrupt sense lines, I0 through I3.   .inx I/O Devices  %An I/O device makes an interrupt request by asserting BIRQL.  .inx System Status Register  If the Interrupt Enable bit of the System Status Register (see sec`tion  4.7) is set (enabling  interrupt requests), the processor micro`program enters an  .inx Interrupt Acknowledge  interrupt acknowledge sequence. This sequence first  .inx IACK  .inx SYNC  .inx DIN  asserts SYNC and IACK, and then DIN, to which  the inter`rupting device of the highest priority responds with its unique  interrupt vector on the data lines.   %The interrupt request lines I1, I2, and I3 are not used.    .page3  _4.1.10 IACK_   .inx IACK  .inx Interrupt Acknowledge  .inx I3 nterrupts  .inx SYNC  .inx REPLY  %The IACK (Interrupt ACKnowledge) and SYNC signals are asserted high by the  processor during clock phase 2 in response to an interrupt request appearing  on I0. It re`mains asserted until the inter`rupting device re`sponds  with REPLY and the interrupt vector address on the data lines.   $CURSOR $EQUAL çàO.ƒ¤¥ .title PDQ-3 Hardware User's Manual  .input (H` U_ B~)  .paragraph (F% I5)  .page3  _4.2 Processor Chip Set_   .inx Processor Control Chip  .inx Processor Data Chip  .inx Processor Control Memory Chips  .inx CPU Module  %The PDQ-3 CPU Module processor is a WESTERN DIGITAL CORP`ORATION  WD9000 processor chip set. This set comprises the  Control Chip, Data Chip and three Read Only Memory Chips (ROMs). The Control  chip and  .inx Microinstructions  Data chip execute microcode found in the three Control Memory chips.    .page3  _4.2.0 Control Chip_   .inx Processor Control Chip  %The control chip provides the  thirteen control signals used to control the internal  .inx WD-Bus  WD-bus (see section 4.1).    .page3  _4.2.1 Data Chip_   .inx Processor Data Chip  .inx Microinstructions  %The Data Chip contains the arithmetic logic unit, the micro`instruc`tion  decode logic, and the internal processor register files. It controls the  .inx WDAL Lines  16 WDAL signal lines de`scribed in section 4.1.    .page3  _4.2.2 Control Memory Chips_   .inx Processor Control Memory Chips  .inx Microinstructions  .inx UCSD Pascal  .inx Memory  %The three Read Only Memory (ROMs) Chips contain the  micro`instruc`tions necessary to emulate the UCSD Pascal version III.0  P-machine. Each memory chip provides 512 words of 22 bits apiece.   .page3  .inx Interrupts  _4.3 Interrupt System_   %An interrupt request on the I0 control line,  occurring with interrupts enabled, causes the processor  .inx DIN  .inx IACK  to begin an interrupt sequence. Both the DIN and the IACK signals  are asserted high at the beginning of  this sequence. The assertion of DIN signals the highest priority  device wit4 h an inter`rupt pend`ing  to gate its interrupt vector address onto the data lines  .inx REPLY  and then assert REPLY. The processor then vectors an interrupt through  this location.   .inx Interrupt Acknowledge  .inx System Status Register  %The assertion of IACK causes the the Interrupt Enable bit of the System  Status register (see section 4.7) to be reset. This permits any  interrupt service routine invoked by the interrupt condition to be  executed without being interrupted. The service routine must  re-enable interrupts at the appro`priate time by setting the  Interrupt Enable bit of the System Status register (see section 4.7).   %Before disabling any device which may require processor intervention, the  interrupt system must be disabled by setting the INTEN bit of the  System Status Register to 0 (see section 4.7). If the interrupt system is  not disabled before the device is disabled, and an interrupt from the device  and the disabling of the device occur in the same instruction cycle,  the device cannot supply the required interrupt vector, and the PDQ-3 will  wait for the vector indefinitely.   %The PDQ-3 CPU Module on-board devices are assigned an inter`rupt  priority above that of the  devices on the Q-Bus. The rel`ative  .inx Priority  priorities of the on-board devices are shown in Table 4.3.   .inx UCSD Pascal  %For details on how to write an interrupt routine in UCSD Pascal,  refer to the PDQ-3 Pro`gram`mer's Manual.   .page14  .inx Priority  .inx Bus Error  .inx Power Fail  .inx Clocks  .inx DMA Controller  .inx Floppy Disk Controller  .inx Console CRT  .inx Printer  .option(F-)  %DEVICE VECTOR PRIORITY  %Bus Error  0002 0 (highest) %Power Fail 0006 1 %DMA (and Floppy disk) 000A  2 %Console Receive Data 000E 3 %Console Transmitter Ready 0012 4 %Carrier Detect  0016 5 %System Clock 001A 6 %Interval Timer 001E 7 (lowest)    .option  .indent11  Table 4.3 PDQ-3 Device Priority Assignment   .inx Interrupts  .inx Interrupt Vectors  .inx Q-Bus  %The interrupt  vector assignments of the standard Q-Bus de`vices, are listed in Appendix  B.    .page3  _4.4 Power Fail and Power Recovery_   .inx Power Fail  .inx BDCOK  .inx BPOK  %Power failure and power recovery are detected on the PDQ-3 by monitoring  the Q-Bus signals BDCOK~H and BPOK~H. Assuming  .inx Memory  .inx Battery Power  the system memory is non-volatile (either because of the type of memory used  or because of battery backup), it is possible to recover from a power failure.  .inx System Status Register  .inx Interrupts  When a power failure occurs, the Power Fail bit in the System Status register  (see section 4.7) is set. If interrupts are enabled, an interrupt is  vectored through location 6. Under these conditions, the system has  approximately 3 ms to prepare for power failure.   .inx HDT  .inx RESET  %When power is restored, the PDQ-3 enters a RESET state and the HDT PROM  is invoked (see Appendix A).  .inx Memory  .inx Clocks 5  .inx Interval Timer  .inx USART  .inx Baud Rate  If the memory can be determined to be intact, processing is  resumed at the point of power failure. Note that the USART baud rate, the  System clock rate, and the Interval Timer rate are reset to their  initial values. If memory cannot be determined to  .inx Bootstrapping  be intact, the PDQ-3 is bootstrapped either into HDT or into the operating  .inx Jumpers  system according to the E12 jumper (see section 3.2.1).    .page3  _4.5 Bus Error_   .inx Bus Error  %A Bus Error on the PDQ-3 is triggered by an access to a non-existent  .inx I/O Devices  .inx Memory  memory or  I/O device address.  A device failing to respond to the assertion of SYNC causes the  bus master to continue to assert SYNC. The duration of the SYNC signal  is monitored by bus timeout logic. If SYNC persists beyond  15 micro`seconds,  the Bus Error recovery logic is initiated. This logic sets the Bus  .inx System Status Register  .inx REPLY  Error bit in the System Status register (see section 4.7) and asserts  REPLY to complete the cycle. If  .inx Interrupts  interrupts are enabled, an interrupt is vectored through location 2.    .page3  _4.6 Interfacing the WD-Bus to the Q-Bus_ -  .inx WD-Bus  .inx Q-Bus  %The Data/Address lines and signals referred to in this section are  described in detail in the sections on the Q-Bus (see chapter 5) and WD-Bus  (see section 4.1).   .inx CPU Module  %The WD-Bus connects all modules internal to the CPU module. This bus  interfaces to the Q-Bus through the Q-Bus interface.  The on-board WD-Bus provides connections between the fol`low`ing de`vices:   .page14  .option(F-) %-- Processor Control chip (see section 4.2.0) %-- Processor Data chip (see section 4.2.1) %-- Real-Time Clock chip (see section 4.9) %-- DMA Controller (see section 4.11.1) %-- Floppy Disk Controller (see section 4.11.0) %-- USART (see section 4.10) %-- HDT PROMs %-- System Environment Switches (see section 4.8) %-- System Status Register (see section 4.7) %-- on-board Address Registers %-- on-board Address Decoder %-- WD-Bus Control Signal Buffer Drivers %-- Q-Bus Buffer Drivers %-- Processor Address Buffer Drivers  .option !  %The WD-Bus Control Signal Buffer Drivers, the WDAL Buffer Drivers, and  the Processor Address Buffer Drivers are  necessary for electrical driving capacities. In addition, the Processor  .inx BDAL Lines  Address Buffer Drivers interface the CPU address with the Q-Bus BDAL  address lines.    .page3  _4.6.0 Address and Data Lines_   .inx WDAL Lines  .inx Bus Master  %When the CPU is the bus master, the WDAL lines carry word addresses.  .inx BDAL Lines  The Q-Bus BDAL lines always carry byte addresses.  In order to interface a CPU word address to a Q-Bus byte address,  the CPU address is shifted left one bit (doubled) by the Processor Address  Buffer Driver. Hence, WDAL0 becomes BDAL1, and BDAL0 is always driven to 0.   .inx DMA Controller  %When the DMA Controller is the bus master, the WDAL lines carry byte  addresses. All addresses are buffered by the WDAL Buffer Drivers, and  no s6 hifting is necessary.   %The WDAL lines are interfaced to the Q-Bus BDAL lines by standard DEC  drivers, receivers and transceivers. Their Q-Bus timing sequence is  .inx Clocks  derived from the 10 MHz master clock.    .page3  _4.6.1 Control Lines_   .inx SYNC  .inx DIN  .inx DOUT  .inx W/R  .inx BSYNC  .inx BDIN  .inx BDOUT  .inx BWTBT  %The WD-Bus control signals SYNC, DIN, DOUT, and W/R are mapped onto the  Q-Bus as BSYNC, BDIN, BDOUT, and BWTBT by standard DEC drivers. The Q-Bus  BRPLY signal is received by a standard DEC receiver, and controls the WD-Bus  REPLY signal. COMPUTE is con`trolled by the Q-Bus BHALT~L signal. It is  ne`gated when BHALT~L is asserted. RESET is con`trolled by the Q-Bus signal  BINIT~L. It is asserted when`ever BINIT~L is asserted. The Q-Bus signal  BBS7 is asserted during address time when address bits 13, 14, 15, and 16  are asserted. All Q-Bus timing is con`trolled by a timing se`quence de`rived  .inx Clocks  from the 10 MHz master clock.    .page3  _6.6.2 Interrupt Lines_   .inx Interrupts  .inx BIRQ  %The Q-Bus interrupt signal BIRQ~L is "OR"ed with other on-board device  inter`rupt re`quest lines to gen`erate the WD-Bus I0 signal.  .inx IACK  .inx BIACK  The Q-Bus signal BIAKO~L is con`trolled by the WD-Bus IACK signal, which  propa`gates through all on-`board devices. If no on-`board de`vice is  re`questing inter`rupt service, BIAKO~L will be asserted when IACK is  asserted. Other`wise, the on-`board de`vice blocks the prop`agation  of IACK and BIAKO~L remains ne`gated.    .page3  _6.6.3 DMA Lines_   .inx DMA Controller  %The Q-Bus DMA request line BDMR~L is "OR"ed with the request of the  on-`board DMA Con`troller to gen`erate a DMA re`quest to the processor.  .inx DMGO  .inx BDMGO  The DMA grant logic generates a bus grant signal, DMGO. This signal  prop`agates through the on-`board DMA Con`troller. If the DMA Controller  is not re`questing the bus, the Q-Bus signal BDMGO~L is asserted when  DMGO is asserted. Other`wise, the on-`board con`troller blocks the  prop`agation of DMGO and BDMGO~L re`mains ne`gated.    .page3  _6.7 System Status Register_ !  .inx System Status Register  %The System Status register is an 8-bit read/write register that  provides the means to effect the status of PDQ-3 CPU Module on-board devices,  and provides information concerning the status of those devices. Its word  address is FC24 (hex). It occupies the  least significant byte of a 16-bit word;  the most significant byte is undefined. The register is defined as follows:   .option(F-)  .page4 @BITS  $----7------6------5-------4------3------2-------1------0--- $! INIT ! INTEN ! 0 ! PWRF ! BANK ! INTVL ! TICK ! BERR ! $-----------------------------------------------------------  .option   .margin(L+5)  .undent3  WARNING: Storing a value into one particular bit o7 f this register stores  a value into ALL bits. The impli`cations of such a storage  must be considered carefully.   .page2  .undent3  --~INIT:  .inx Jumpers  .inx HDT  .inx Bootstrapping  %When read, the INIT bit reflects the jumper status of the E12, E13,  and the E14 jumpers.  If E12 is is jumped to E13, the INIT bit is set to 0. If E14 is jumped to  E13, the INIT bit is set to 1. The HDT PROM program (see Appendix A) uses  this value to determine the bootstrapping sequence.   %When written to, the INIT bit is used as a bus reset control. Writing  a 1 into this  .inx BINIT  bit causes the assertion of the BINIT bus signal for 96 microseconds.  During this period, the processor is placed in the BUSY state and all system  devices are re-initialized. (The 8253 counter  described in section 4.9 is an exception.)   .page2  .undent3  --~INTEN:  .inx Interrupts  %The INTEN bit reflects the state of the PDQ-3 interrupt system. If the INTEN  bit is set to 1, the interrupt system is enabled (see section 4.3). If  the INTEN bit is set to 0, the interrupt system is disabled and all interrupts  are latched. The state of the interrupt system can be changed by loading a  different value into INTEN.   %To disable the interrupt system, it is safest  to cycle, setting INTEN to 0 and reading the System Status Register, until  INTEN is read as a 0. This guarantees that the interrupt routine of a device  may not re-`enable the interrupt system if the device interrupt and the  interrupt disable occur in the same instruction cycle.   .page2  .undent3  --~0:  %This bit of the System Status Register is reserved. This bit  should be set to 0 (zero) whenever this register is modified.   .page2  .undent3  --~PWRF:  .inx Power Fail  .inx BPOK  %The PWRF bit is set to 1 when a Power Failure is imminent (the BPOK bus  signal is negated).  If the interrupt system is enabled, a  Power Failure causes a processor interrupt through the  interrupt vector at location 6. The PWRF condition must be cleared in  order to satisfy the interrupt. The PWRF bit is set to 0 by writing a  1 into PWRF.   %If, after clearing the PRWF condition, the PWRF bit is  still set to 1, a complete power failure will occur within 3 milliseconds.  .inx Interrupts  In this case, the interrupt system should remain off, and the power failure  interrupt handler should prepare for the power failure. Its last action  should be to loop until the PWRF bit is set to 0. Assuming a recovery  is possible (see section 4.4), the loop will be exited upon recovery.   .page2  .inx BANK  .undent3  --~BANK:  %The BANK bit selects which 128KB memory bank is being used. If it is set to  0, the main bank is selected; if it is set to 1, the alternate bank is  selected. This bit should always be set to 0 for systems with a single  memory bank.   .page2  .undent3  --~INTVL:  .inx Interval Timer  %The INTVL bit indicates the Interval Timer counter (#2-  see section 4.9)  has counted down to 0. If the interrupt system is enabled, an  Interval Timer 'tick' causes a processor interrupt throug8 h the  interrupt vector at location 1E hex. The INTVL condition must be cleared in  order to satisfy the interrupt. The INTVL bit is set to 0 by storing a  1 into INTVL.   .page2  .undent3  --~TICK:  .inx Clocks  %The TICK bit indicates the System Clock counter (#1-  see section 4.9)  has counted down to 0. If the interrupt system is enabled, a  System clock 'tick' causes a processor interrupt through the  interrupt vector at location 1A hex. The TICK condition must be cleared in  order to satisfy the interrupt. The TICK bit is set to 0 by writing a  1 into TICK. "  .page2  .undent3  --~BERR:  .inx Bus Error  %The BERR bit indicates a Bus Error condition. It is set to 1 after  .inx REPLY  .inx SYNC  either memory or an I/O device fails to assert the bus signal REPLY  within 15 microseconds of the assertion of the SYNC signal. A  BERR condition also occurs as a result of setting the INIT bit of the  .inx Interrupts  System Status register to 1. If the interrupt system is enabled, a  Bus Error condition causes a processor interrupt through the interrupt  vector at location 2. The Bus Error condition must be cleared in  order to satisfy the interrupt. The BERR bit is set to 0 by writing a  1 into BERR.  .margin    .page3  _4.8 Environment Switch_   .inx Switches  %The Environment Switch is an 8 bit DIP switch (see Figure 3.1.0)  used to commun`icate cer`tain  informa`tion about the hardware environment to the operating system. The value  of the register may be read as the low order byte of the word at device  address FC18 hex. The contents of the high order byte are un`defined.  %The DIP switches are defined as in Table 4.8.   .margin(L+5)  .undent5  NOTE: Bit 0 of the byte value corresponds to the dip switch marked '1'.  A bit value of 0 corresponds to a dip switch in the closed (off) position.  .margin   .page27  .inx Baud Rate  .inx HDT  .inx Printer  .inx Console CRT  .inx Switches  .option(F-)  +Bits Value Meaning  +7 1  Boot into HDT * +6 - Reserved for user applications * +5 - Reserved for user applications * +4 - Reserved for user applications + +3  - Reserved for user applications  +2:0 000 Console Speed is 19200 baud 5001 Console Speed is 9600 baud 5010 Console Speed is 4800 baud 5011 Console Speed is 2400 baud 5100 Console Speed is 1200 baud 5101 Console Speed is 600 baud 5110 Console Speed is 300 baud 5111 Console Speed is 110 baud    .option  .indent15  Table 4.8 DIP Switch Configuration    .page3  _4.9 Real Time Clocks_    .inx Clocks  .inx USART  .inx Baud Rate  %Real time clock functions are provided by an Intel 8253 programmable  counter`/timer chip. This device provides three coun`ter`/timers:  one for the USART Baud Rate clock,  one for a 100 Hz System clock,  .inx Interval Timer  and one for a programmable Interval Timer with a range from 9  10ms to 10 minutes in 10ms increments.   %The 8253 is driven by a 1.25MHz clock derived from the system 10MHz  oscil`lator. This clock is used to strobe successive  dec`rements of the System clock and Baud Rate clock counter registers.  A clock "ticks" when its counter register reaches zero. The Interval Timer is  decremented on successive "ticks" of the System clock.    %The 8253 comprises four registers as shown in Table 6.9 and de`scribed  below.   .page11  .inx Clocks  .inx Counter Mode Register  .inx Baud Rate Clock Counter  .inx Interval Timer  .inx System Clock Counter  .option(F-)  %REGISTER  BITS ADDRESS ACCESS H(word)  %Baud Rate clock counter 8 FC20 Read/Write %System clock counter 8 FC21 Read/Write %Interval Timer counter 8 FC22 Read/Write %Mode Register 8  FC23 Write Only  +  .option (F+)  .indent14  Table 4.8 Real Time Clock Registers    .page3  _4.9.0 Mode Register_   .inx Counter Mode Register  %The Mode Register controls the operation of each of the counters.  The Mode Register format is shown below.   .page4  .option(F-) ?BITS  ----7-------6-------5-------4-------3-------2-------1-------0----  ! COUNT REG SEL ! LOAD METHOD ! MODE ! 0 !  -----------------------------------------------------------------  .option +   .page2  .margin(L+5)  .undent3  --~COUNT REG SEL:  %These two bits specify the counter to  which the remaining mode control  information is to apply:   .page4  .inx Baud Rate Clock Counter  .inx Interval Timer  .inx System Clock Counter  .option(F-) %00 = Baud Rate Clock counter %01 = System Clock counter %10 = Interval Timer counter %11 = Illegal  .option <  .page2  .undent3  --~LOAD METHOD:  %These two bits specify the  method to be used in latching the initial  contents of the specified counter register:   .page8  .option(F-)  00 = Not used by the PDQ-3. %01 = Load the least significant byte % of counter only. %10 = Load the most significant byte of *counter only. %11 = Load the least significant byte *first, followed by the most *significant byte.  .option   .page2  .undent3  --~MODE:  %These three bits specify the operating mode of  the spec`ified counter:   .page6  .inx Baud Rate Clock Counter  .inx Interval Timer  .inx System Clock Counter  .option(F-) 2Counter Recommended JMode 2 2Baud Rate clock 010 2System clock 010 2Interval Timer 000 or 010  .option  .margin    .page3  _4.9.1 Using the Clocks_   .inx Clocks  %To program a clock counter, the mode for the counter is specified by  load`ing the mode register, then  the counter register is loaded.  The mode char`acterizes the conditions under which the specified counter  dec`rements and whether or not the counter restarts after reaching  zero. On the PDQ-3, all counters start decrementing on the  clock transition  immediately fol`low`ing the last load necessary to initialize the counter.  It is necessary to load the counter register either once or twice depending  on whether one or:  two bytes  of the counter are being initialized.    .page3  _4.9.1.0 Baud Rate Clock_   .inx Baud Rate Clock Counter  .inx USART  .inx Baud Rate  %This counter creates the baud rate timing for the on-board USART. USART  operation from 50 baud to 19,200 baud is possible. The base frequency of this  counting register is 1.25MHz. The USART baud rate is set by loading the  Baud Rate clock counter register with the baud factor (BF) where: :  .indent22  BF = 39066/B   %'B' is in bits per second, and BF is rounded to the nearest  integer. The Baud Rate clock is programmed (using mode 010)  to restart itself when it counts down to zero, thus providing a  steady pulse rate of the desired frequency.   .inx HDT  .inx Switches  %The Baud Rate clock is normally initialized by the HDT ROM at system reset  time according to the state of the Environment Switch Register  (see section 3.1.1).    .page3  _4.9.1.1 System Clock_   .inx System Clock Counter  %This counter produces the 10ms pulses used by the PDQ-3 to  provide a real-time clock.  The input clock rate to this counter is 1.25MHz.  To generate the an arbitrary pulse rate, the System clock counter register  is loaded with the Clock Factor (CF):   .indent25  CF = 1250000 x T   %'T' is the pulse period in seconds. For example, to set the System  clock to  generate 10ms pulses, CF = 1250000 x .01 = 12500. Thus 12500 is loaded into  the System clock counter register. The System clock is programmed (using  mode 010) to restart itself when it counts down to zero, thus providing a  steady pulse rate of the desired frequency.   %When the System clock counter register counts down to zero, the  .inx System Status Register  System clock bit in the System Status register (see section 4.7) is set. If  .inx Interrupts  interrupts are enabled, an interrupt will be generated through location  1A hex.   $CURSOR $EQUAL „O.#¥#¥;    TABLE OF FIGURES AND CHARTS   Figure 1.0   Block Diagram of the PDQ-3 Computer System..........................?   Figure 3.1.0   The CPU Module.......................................................?   Figure 3.1.1   Table of Switch Options 1-3...........................................?   Figure 3.2.0   Picture of a Floppy Diskette..........................................?   Figure 4.1   WD-Bus Signals.........................................................?   Figure 4.3   PDQ-3 Device Priority Assignments......................................?   Figure 4.8   DIP Switch Configuration...............................................?   Figure 4.9   Real Time Clock Registers..............................................?   Figure 4.10   USART Registers.........................................................?   Figure 4.11.1 A   Command Summary.........................................................?   Figure 4.11.1 D   Flag Summary (Type 1)...................................................?   Figure 4.11.1.D   Flag Summary (Type II)..................................................?   Figure 4.11.1.D   Flag Summary (Type IV)...................................................?   Figure 4.11.1.E   Stepping Rates...........................................................?   Figure 4.11.2   Formatting Control Byte Functions.........................................?   Figure 4.11.5   Track Format: Single Density..............................................?   Figure 4.11.4   Track Format: Double Density..............................................?   Figure 4.11.3   Type IV Termination Conditions............................................?   Figure 4.11.4   DMA Interface Registers....................................................?   Figure 5.0.0   The Q-Bus..................................................................?   Figure 5.0.1   Dual Size Module Configuration...............................................?   Figure 5.0.1.B   Quad Slize Module Configuration..............................................?   Figure 5.0   Backplane Pin Assignments...................................................?   Figure 5.8.0   Bus Terminations.............................................................?  < üÿ$LAST A $EQUAL $CURSOR $TAG 6ÿÿ66ÿÿÀ®lÀƒ @@@O.«¡ƒ¤& %This bit of the System Status Register is reserved. This bit  should be set to 0  (zero) whenever this register is modified.   .page2  .undent3  --~PWRF:  .inx Power Fail  .inx BPOK  %The PWRF bit is set to 1 when a Power Failure is imminent (the BPOK bus  signal is negated).  If the interrupt system is enabled, a  Power Failure causes a processor interrupt through the  interrupt vector at location 6. The PWRF condition must be cleared in  order to satisfy the interrupt. The PWRF bit is set to 0 by writing a  1 into PWRF.   %If, after clearing the PRWF condition, the PWRF bit is  still set to 1, a complete power failure will occur within 3 milliseconds.  .inx Interrupts  In this case, the interrupt system should remain off, and the power failure  interrupt handler should prepare for the power failure. Its last action  should be to loop until the PWRF bit is set to 0. Assuming a recovery  is possible (see section 6.4), the loop will be exited upon recovery.   .page2  .inx BANK  .undent3  --~BANK:  %The BANK bit selects which 128KB memory bank is being used. If it is set to  0, the main bank is selected; if it is set to 1, the alternate bank is  selected. This bit should always be set to 0 for systems with a single  memory bank.   .page2  .undent3  --~INTVL:  .inx Interval Timer  %The INTVL bit indicates the Interval Timer counter (#2-  see section 6.9)  has counted down to 0. If the interrupt system is enabled, an  Interval Timer 'tick' causes a processor interrupt through the  interrupt vector at location 1E hex. The INTVL condition must be cleared in  order to satisfy the interrupt. The INTVL bit is set to 0 by storing a  1 into INTVL.   .page2  .undent3  --~TICK:  .inx Clocks  %The TICK bit indicates the System Clock counter (#1-  see section 6.9)  has counted down to 0. If the interrupt system is enabled, a  System clock 'tick' causes a processor interrupt through the =  interrupt vector at location 1A hex. The TICK condition must be cleared in  order to satisfy the interrupt. The TICK bit is set to 0 by writing a  1 into TICK. "  .page2  .undent3  --~BERR:  .inx Bus Error  %The BERR bit indicates a Bus Error condition. It is set to 1 after  .inx REPLY  .inx SYNC  either memory or an I/O device fails to assert the bus signal REPLY  within 15 microseconds of the assertion of the SYNC signal. A  BERR condition also occurs as a result of setting the INIT bit of the  .inx Interrupts  System Status register to 1. If the interrupt system is enabled, a  Bus Error condition causes a processor interrupt through the interrupt  vector at location 2. The Bus Error condition must be cleared in  order to satisfy the interrupt. The BERR bit is set to 0 by writing a  1 into BERR.  .margin    .page3  _6.8 Environment Switch_   .inx Switches  %The Environment Switch is an 8 bit DIP switch (see Figure 3.1.0)  used to commun`icate cer`tain  informa`tion about the hardware environment to the operating system. The value  of the register may be read as the low order byte of the word at device  address FC18 hex. The contents of the high order byte are un`defined.  %The DIP switches are defined as in Table 6.8.   .margin(L+5)  .undent5  NOTE: Bit 0 of the byte value corresponds to the dip switch marked '1'.  A bit value of 0 corresponds to a dip switch in the closed (off) position.  .margin   .page27  .inx Baud Rate  .inx HDT  .inx Printer  .inx Console CRT  .inx Switches  .option(F-)  +Bits Value Meaning  +7 1  Boot into HDT * +6 - Reserved for user applications * +5 - Reserved for user applications * +4:3 - Reserved for user applications  +2:0 000 Console Speed is 19200 baud 5001 Console Speed is 9600 baud 5010 Console Speed is 4800 baud 5011 Console Speed is 2400 baud 5100 Console Speed is 1200 baud 5101 Console Speed is 600 baud 5110 Console Speed is 300 baud 5111 Console Speed is 110 baud    .option  .indent15  Table 6.8 DIP Switch Configuration    .page3  _6.9 Real Time Clocks_   .inx Clocks  .inx USART  .inx Baud Rate  %Real time clock functions are provided by an Intel 8253 programmable  counter`/timer chip. This device provides three coun`ter`/timers:  one for the USART Baud Rate clock,  one for a 100 Hz System clock,  .inx Interval Timer  and one for a programmable Interval Timer with a range from  10ms to 10 minutes in 10ms increments.   %The 8253 is driven by a 1.25MHz clock derived from the system 10MHz  oscil`lator. This clock is used to strobe successive  dec`rements of the System clock and Baud Rate clock counter registers.  A clock "ticks" when its counter register reaches zero. The Interval Timer is  decremented on successive "ticks" of the System clock.   %The 8253 comprises four registers as shown in Table 6.9 and de`scribed  below.   .page11  .inx Clocks  .inx Counter Mode Register  .inx Baud Rate Clock Counter  .inx Interval Timer  .inx System Clock Counter  .option(F-)  %REGISTER >  BITS ADDRESS ACCESS H(word)  %Baud Rate clock counter 8 FC20 Read/Write %System clock counter 8 FC21 Read/Write %Interval Timer counter 8 FC22 Read/Write %Mode Register 8  FC23 Write Only  +  .option  .indent14  Table 6.8 Real Time Clock Registers    .page3  _6.9.0 Mode Register_   .inx Counter Mode Register  %The Mode Register controls the operation of each of the counters.  The Mode Register format is shown below.   .page4  .option(F-) ?BITS  ----7-------6-------5-------4-------3-------2-------1-------0----  ! COUNT REG SEL ! LOAD METHOD ! MODE ! 0 !  -----------------------------------------------------------------  .option +   .page2  .margin(L+5)  .undent3  --~COUNT REG SEL:  %These two bits specify the counter to  which the remaining mode control  information is to apply:   .page4  .inx Baud Rate Clock Counter  .inx Interval Timer  .inx System Clock Counter  .option(F-) %00 = Baud Rate Clock counter %01 = System Clock counter %10 = Interval Timer counter %11 = Illegal  .option <  .page2  .undent3  --~LOAD METHOD:  %These two bits specify the  method to be used in latching the initial  contents of the specified counter register:   .page8  .option(F-)  00 = Not used by the PDQ-3. %01 = Load the least significant byte % of counter only. %10 = Load the most significant byte of *counter only. %11 = Load the least significant byte *first, followed by the most *significant byte.  .option   .page2  .undent3  --~MODE:  %These three bits specify the operating mode of  the spec`ified counter:   .page6  .inx Baud Rate Clock Counter  .inx Interval Timer  .inx System Clock Counter  .option(F-) 2Counter  Recommended JMode 2 2Baud Rate clock 010 2System clock 010 2Interval Timer 000 or 010  .option  .margin    .page3  _6.9.1 Using the Clocks_   .inx Clocks  %To program a clock counter, the mode for the counter is specified by  load`ing the mode register, then  the counter register is loaded.  The mode char`acterizes the conditions under which the specified counter  dec`rements and whether or not the counter restarts after reaching  zero. On the PDQ-3, all counters start decrementing on the  clock transition  immediately fol`low`ing the last load necessary to initialize the counter.  It is necessary to load the counter register either once or twice depending  on whether one or two bytes  of the counter are being initialized.    .page3  _6.9.1.0 Baud Rate Clock_   .inx Baud Rate Clock Counter  .inx USART  .inx Baud Rate  %This counter creates the baud rate timing for the on-board USART. USART  operation from 50 baud to 19,200 baud is possible. The base frequency of this  counting register is 1.25MHz. The USART baud rate is set by loading the  Baud Rate clock counter register with the baud factor (BF) where: :  .indent22  BF = 39066/B   %'B' is in bits per second, and BF is rounded to the nearest  integer. The Baud Rate clock is programmed (using mode 010)  to restart itself when it counts?  down to zero, thus providing a  steady pulse rate of the desired frequency.   .inx HDT  .inx Switches  %The Baud Rate clock is normally initialized by the HDT ROM at system reset  time according to the state of the Environment Switch Register  (see section 3.1.1).    .page3  _6.9.1.1 System Clock_   .inx System Clock Counter  %This counter produces the 10ms pulses used by the PDQ-3 to  provide a real-time clock.  The input clock rate to this counter is 1.25MHz.  To generate the an arbitrary pulse rate, the System clock counter register  is loaded with the Clock Factor (CF):   .indent25  CF = 1250000 x T   %'T' is the pulse period in seconds. For example, to set the System  clock to  generate 10ms pulses, CF = 1250000 x .01 = 12500. Thus 12500 is loaded into  the System clock counter register. The System clock is programmed (using  mode 010) to restart itself when it counts down to zero, thus providing a  steady pulse rate of the desired frequency.   %When the System clock counter register counts down to zero, the  .inx System Status Register  System clock bit in the System Status register (see section 6.7) is set. If  .inx Interrupts  interrupts are enabled, an interrupt will be generated through location  1A hex.    .page3  _6.9.1.2 Interval Timer_   .inx Interval Timer  %This counter is loaded by the system or application as required.  The input clock to this counter is the System clock pulse.  Assuming the System clock pulses at 10 ms intervals, the  Interval Timer may be programmed to  produce time-out intervals from 10ms to 10 minutes. To generate an  arbitrary interval pulse, the Interval Timer counter register is loaded  with the Interval Factor (IF), computed as follows: :  .indent27  IF = 100 x I   % 'I' is the time-out  interval in seconds. Thus, to generate a pulse of 1 second (IF = 100 x 1 = 100),  the Interval Timer counter register is loaded with 100.  The Interval Timer is programmed either to restart itself when it counts  down to zero (using  mode 010) or to terminate on the first pulse (using mode 000).   %When the Interval Timer counter register counts down to zero, the  .inx System Status Register  Interval Timer bit in the System Status register (see section 6.7) is set. If  interrupts are enabled, an interrupt will be generated through location  1E hex. $LAST $EQUAL $CURSOR O.¹ ƒ¤ @  .output (ASC E+)  .option (S1 F+)  .title PDQ-3 Hardware User's Manual  .input (H` U_ B~)  .paragraph (F% I5)  .margin (L5 R72) üÿ$LAST $EQUAL $CURSOR ÿÿÿÿÿÿO.¹ 2¤ --~The PDQ-3 comes up in the HDT state, prompt`ing the user with  a '#' (see Appendix A for de`tails on HDT). Once a boot`able  disk`ette has been in`serted into the left floppy disk drive, the user can  press `R` to boot the UCSD Pascal System.   .inx Floppy Control Cable  .inx CPU Module  .inx Run/Halt Button  .undent3  --~The machine comes up in an auto`matic boot`strap rou`tine.  As`suming a boot`able diskette has been in`serted in the left drive,  the floppy disk drives should start run`ning. If they do not,  check to make sure the disk`ette has been  in`serted correct`ly, and that the Run/`Halt button (front panel)  is in the Run (out) position. Also check that the floppy control  cable is securely connected to the CPU Module (refer to section 3.0 for  details).  .margin   .inx Configuration  .inx Console CRT  .inx Work Disk  .undent3  4) The "BOOT" disk boots a con`figur`ation pro`gram. Un`de`ci`pher`able  char`acters ap`pear on certain types of con`sole CRTs. This A  prob`lem is cleared up once the screen is con`figured (later in the  initial bootstrapping process).  Read the text on the screen. The user is in`structed  to insert a scratch disk into  the right-hand drive and press the car`riage re`turn key on the key`board.  The program pro`ceeds to make a bootable work disk from the  scratch disk. Hence`forth, this work disk should be used  for boot`ing, and the "BOOT" disk should be saved as a backup.   .inx Console CRT  .undent3  5) After the work disk is made, the program prompts the user for  the type of console CRT to be used with the PDQ-3.   .inx Reset Button  .undent3  6) The pro`gram has finished when "Done." ap`pears on the  screen. Re`move the disk`ettes  from the drives as follows:   .inx Floppy Disk Drives  .inx Diskettes  .margin(L+5)  .undent3  a) Press down on the lever below the drive. The door should pop  open, and the edge of the disk`ette should be vis`ible.   .undent3  b) Gently pull the diskette forward, out of the drive.  .margin   .inx Bootstrapping  .undent3  7) In`sert the new`ly cre`ated work disk  into the left-`hand  disk drive, and bootstrap it (starting at step 1 above). IT IS RECOMMENDED  THAT THE BOOT DISK BE SAVED AS A BACKUP AND THAT THE WORK DISK BE USED  HENCEFORTH.  .margin    .page3  .inx Powering Down  .inx Diskettes  .inx Floppy Disk Drives  _3.2.2 Turning Power Off_   %To power down the PDQ-3:   .margin(L+5)  .undent3  1) REMEMBER TO REMOVE ALL DISK`ETTES FROM ALL FLOPPY DRIVES BEFORE  POWER`ING UP OR DOWN.   .inx DC Power Button  .inx DC Power Light Indicator  .inx Power, DC  .undent3  2) Turn off the DC power (front panel) by pressing the DC ON button.  When the DC power is off, the DC ON button will be unlit.   .inx AC Power Switch  .inx AC Power Light Indicator  .inx Power, AC  .undent3  3) Turn off the AC power (rear panel) by flipping the AC power switch down.  .margin !  A $EQUAL $CURSOR $CURSOR  ÿÿd&O.«¡2¤    .page3  .inx Console Controller  .inx Console CRT  .inx Baud Rate  .inx RS-232C  _6.10 Console Controller_   %The PDQ-3 RS-232C Console Controller is a WD1931 USART located onboard the PDQ-3  CPU Module.  It supportsB  full duplex com`mun`i`cation with the console at  speeds ranging from 50 to 19,200 bits per second. Recom`mendations for  .inx CPU Module  .inx Cabling  cabling between the PDQ-3 CPU Module and the operator's console are found  is Appendix D.    .page3  _6.10.0 USART Registers_   .inx USART  .inx USART Interface Registers  %The USART provides five 8-bit interface  registers. Com`muni`cation with the USART registers may be carried  on in either  the word or byte mode. Significant data always occupies the low order byte,  and the value of the high order byte is undefined.   %Table 6.10 lists the USART registers accessible by the proces`sor.   .page12  .inx USART Control Register #1  .inx USART Control Register #2  .inx USART Status Register  .inx Transmitter Holding Register  .inx Receiver Holding Register  .option(F-)  *REGISTER  ADDRESS ACCESS I(Word)  'Control Register #1 FC10 Read/write 'Control Register #2 FC11 Read/Write 'Status Register FC12 Read only 'Transmitter Holding Register  FC13 Write only 'Receiver Holding Register FC13 Read only    .option  .indent20  Table 6.10 USART Registers   .page3  _6.10.0.0 Control Registers_   %The two 8-bit Control registers hold device programming information such  as mode selection, interface signal control, and data format.    .page3  _6.10.0.0.0 Control Register #1_   .inx USART Control Register #1  %The USART Control register #1 is used to define line proto`col and data  con`trol func`tions. It is de`fined as fol`lows:   .page4  .option(F-) @BITS !----7-------6-------5-------4-------3------2------1-------0---- !! LOOP ! BRK ! MISC ! ECHO ! PE ! RE ! RTS ! DTR ! !---------------------------------------------------------------  .option G  .margin(L+5)  .page2  .undent3  --~LOOP:  %The Loop/Normal bit allows all data sent to the trans`mitter to  appear at the receiver, thus forming an internal diagnostic  data loop. When this bit is set to 1, the loop is  .inx Interrupts  activated and ring interrupts are dis`abled. When this bit  is set to 0, the ring interrupt is enabled and the  USART is configured to operate in normal full duplex mode.    .page2  .undent3  --~BRK:  %The Break bit allows the trans`mitter output line to be held in  a continuous space state start`ing at the next char`acter.  When this bit is set to 0 and  the trans`mitter is enabled, the trans`mitter acts  normally except that the trans`mitter output line is held in  the spacing state.   .page2  .inx Character Length  .inx Stop Bit  .undent3  --~MISC:  %This bit determines the number of stop bits to be  transmitted with each character. When this bit is set to  0, a single stop bit is transmitted.  When this bit is set to 1, two stop bits are transmitted  with each character 6, 7, or 8 bits long, and 1.5 stop bits  for characters 5 bits long. )  .page2  .undent3  --~ECHO:  %The Echo Mode bit allows data on the receiver input line to be  duplicated on the trans`mitter ouput line.  When this bit is set to 0 and the recC eiver is  enabled, the clocked regenerated data is presented to  the Transmitted Data output.   .page2  .inx Parity  .undent3  --~PE:  %The Parity Enable bit enables checking of the parity on received  char`acters and generation of parity on transmitted  char`acters. When this bit is set to 0, parity  checking/`generation is enabled. When this bit is set to 1,  parity checking/`generation is disabled.   .page2  .undent3  --~RE:  %The Receiver Enable bit controls the receiver logic.  When this bit is set to 0, characters may be  .inx Receiver Holding Register  .inx USART Status Register  placed in the Receiver Holding register and Status  register bits 1 through 4 may be updated. When this  bit is set to 1, status bits 1-4 are cleared and the  receiver is disabled.   .page2  .undent3  --~RTS:  %The Request To Send bit controls the data set CA circuit.  This bit must be set to 0 and the Clear To Send input  must be asserted for the trans`mitter to be enabled.  When this bit is set to 1, the trans`mitter is disabled  and the RTS output is turned off at the completion of  any current character trans`missions.   .page2  .undent3  .inx DTR  --~DTR:  %The Data Terminal Ready bit controls the data set CD circuit.  When set to 0, Carrier, Data Set Ready, and Ring  interrupts are enabled. When set to 1, the  Ring interrupt is enabled.  .margin    .page3  _6.10.0.0.1 Control Register #2_   .inx USART Control Register #2  %The USART Control register #2 controls the data format and  transmission/`receive rates. It is defined as follows:   .page4  .option(F-) ABITS !----7-------6-------5--------4--------3--------2-----1-----0----- !! CHAR LENGTH ! MODE ! ODD/EVN ! RX CLK ! CLOCK SELECT ! !-----------------------------------------------------------------  .option !  .margin(L+5)  .page2  .inx Character Length  .undent3  --~CHAR LENGTH:  %The Character Length bits select the number of bits per  character as follows:   .page4  .option(F-) 400 - five bits 401 - six bits 410 - seven bits 411 - eight bits  .option   .page2  .undent3  --~MODE:  %The Character Mode bit configures the USART for  asyn`chronous character mode. This bit is set to 1  on the PDQ-3. (Synchronous character mode is not used.)   .page2  .inx Parity  .undent3  --~ODD/EVN:  %The Odd/Even bit determines the transmit/`receive  parity. When this bit is set to 0, odd parity is  generated/`expected. When this bit is set to 1,  even parity is selected.   .page2  .inx Clocks  .undent3  --~RX CLK:  %The alternate RX clock bit determines the separate receive  data clock rate. This feature is not used on the  PDQ-3 and this bit must always be set to 1.   .page2  .inx Baud Rate  .inx Baud Rate Generator  .inx Clocks  .undent3  --~CLOCK SELECT:  %These bits select the transmit and receive clocks, and must  always be set to 110 on the PDQ-3. This allows the  Baud Rate generator (see section 6.9.1.0) to determine  both clock rates.  .margin    .page3  _6.10.0.1 Status Register_   .inx USART Status Register  %The USART Status register contains information relating to the status of the  USART. It is defD ined as follows: !  .page4  .option(F-) >BITS  ----7-------6-------5-------4-------3-------2-------1-------0----  ! DSC ! DSR ! CD ! FE ! PE ! OE ! DR ! THRE !  -----------------------------------------------------------------  .option   .margin(L+5)  .page2  .undent3  --~DSC:  %The Data Set Change bit is set to 0 after a change in  the state of either the DSR or CD control inputs (assuming  .inx USART Control Register #1  .inx DTR  the DTR bit in Control register #1 is programmed 0)  or Ring control input (assuming the DTR bit in Control  register #1 is programmed 1). This bit is set to 1 after  the Status register is read.   .page2  .undent3  --~DSR:  %The Data Set Ready bit is the Data Set Ready control input from  the Data Set.   .page2  .inx DTR  .inx Printer  .inx Console CRT  .undent3  --~CD:  %The Carrier Detect bit is the Carrier Detect control input from  the Data Set. On the PDQ-3, it is used to monitor the DTR signal of  a printer when the serial port is multi`plexed between a CRT and a  serial printer.   .page2  .inx Stop Bit  .undent3  --~FE:  %The Framing Error bit is set to 0 if the receiver is enabled and  the last character received is found not to have a stop  bit. A framing error condition is cleared (this bit is set  to 1) when the receiver is disabled then reenabled.   .page2  .undent3  .inx Parity  --~PE:  %The Parity Error bit is set to 0 when the receiver and Receive  Parity are enabled and the last received character has  a parity error. A parity error condition is cleared (this  bit is set to 1) when the receiver is disabled and then  reenabled.   .page2  .undent3  --~OE:  %The Overrun Error bit is set to 0 when a character has been   .inx Receiver Holding Register  received and is ready to be trans`ferred to the Receiver  Holding register, but DR is set to 0 (indicating that the  proces`sor has not responded to the last character). In  this case, the newest character is lost. An overrun error  con`dition is cleared (this bit is set to 1) when the  receiver is disabled and then reenabled.   .page2  .undent3  --~DR:  %The Data Received bit is set to 0 when the receiver is enabled  .inx Receiver Holding Register  and the Receiver Holding register is loaded from the  Receiver. It is set to 1 when the Receiver Holding  register is read by the proces`sor or when the receiver  is disabled.   .page2  .undent3  --~THRE:  .inx Transmitter Holding Register  %The Trans`mitter Holding Reg`ister Emp`ty bit is set to 0  when the con`tents of the Trans`mitter Hold`ing Reg`ister  is trans`ferred to the trans`mitter reg`ister and  Trans`mitter is en`abled. It is set to 1 when the  Trans`mitter Hold`ing Reg`ister is loaded by the proces`sor  or when trans`mitter is dis`abled.  .margin !   .page3  _6.10.0.2 Trans`mitter Holding Register_   .inx Transmitter Holding Register  %The Trans`mitter Holding register buffers data for trans`mission.  When the trans`mitter is not busy and the trans`mitter is E  enabled, the contents of the Trans`mitter Holding register is trans`ferred to  the trans`mitter and a THRE condition is generated. Note that the Trans`mitter  Holding register is loaded with the 1's complement of the character to  be transmitted.    .page3  _6.10.0.3 Receiver Holding Register_   .inx Receiver Holding Register  %The Receiver Holding register buffers data received from the operator's  console. A DR status condition is generated when the Receiver  Holding register   is full. Note that the data contained in the Receiver Holding register is  the 1's complement of the data received.    .page3  _6.10.1 Printer Multiplexing_   .inx Console CRT  %The Printer Multiplexing feature permits a serial printer to share the  USART with the operator's console. The printer is selected by the  .inx System Status Register  assertion of the PRNT bit of the System Status register (see  section 6.7). When the printer is selected, char`acter transmission  .inx RS-232C  proceeds over the Secondary Trans`mit line of the RS-232C con`nector.  Hand`shaking between the proces`sor and the printer is ac`complished by  .inx Printer  .inx DTR  .inx Cabling  connecting the printer Data Terminal Ready signal to the Carrier Detect  line of the RS-232C connector. For cabling details, refer to Appendix D.   .inx Baud Rate  .inx Console CRT  %Note that the receiver lines of the USART are not connected to the printer.  Therefore, no character transmission from the printer to the USART is possible.  Note, also, that if the printer baud rate differs from the operator's console  .inx Baud Rate Generator  baud rate, the Baud Rate generator (see section 6.9) must be re`programmed  each time the USART is redirected. During this time, the USART receiver  should be disabled since any data received from  the operator's console is invalid. USART oper`ation should not be switched  be`tween the con`sole and the printer any sooner than one char`acter time  after the last char`acter out`put. This allows time for the USART to finish  trans`mitting that char`acter.    .page3  _6.10.2 USART Interrupts_   .inx Interrupts  %Assuming interrupts are enabled (see section 6.3), the USART may generate  proces`sor interrupts under one of three conditions:   .margin(L+5)  .undent3  .inx Transmitter Holding Register  1) The Trans`mitter Holding register is empty. An inter`rupt  is generated through location 12 hex. Note that this inter`rupt  is continuously generated until either the Trans`mitter  .inx USART Control Register #1  Holding register is full, the trans`mitter is disabled (see  the RTS bit of Control register #1), or interrupts are  disabled.   .undent3  .inx Receiver Holding Register  2) The Receiver Holding register is full. An interrupt is  generated through location OE hex.   .undent3  .inx DTR  3) The Carrier Detect Signal (DTR from the printer) or the Data Set Ready  signal has changed. An inter`rupt is gen`erated through loca`tion 16 hex.  This inter`rupt is con`tinuously gen`erated until either inter`rupts are  dis`abled, the USART status register is read, or location FC1A is read.  .margin F  priorities of the on-board devices are shown in Table 6.3.   .inx UCSD Pascal  %For details on how to write an interrupt routine in UCSD Pascal,  refer to the PDQ-3 Pro`gram`mer's Manual.   .page14  .inx Priority  .inx Bus Error  .inx Power Fail  .inx Clocks  .inx DMA Controller  .inx Floppy Disk Controller  .inx Console CRT  .inx Printer  .option(F-)  %DEVICE VECTOR PRIORITY  %Bus Error 0002 0 (highest) %Power Fail  0006 1 %DMA (and Floppy disk) 000A 2 %Console Receive Data 000E 3 %Console Transmitter Ready 0012 4 %Printer Protocol 0016 5 %System Clock  001A 6 %Interval Timer 001E 7 (lowest)    .option  .indent11  Table 6.3 PDQ-3 Device Priority Assignment   .inx Interrupts  .inx Interrupt Vectors  .inx Q-Bus  %The interrupt  vector assignments of the standard Q-Bus de`vices, are listed in Appendix  B.    .page3  _6.4 Power Fail and Power Recovery_   .inx Power Fail  .inx BDCOK  .inx BPOK  %Power failure and power recovery are detected on the PDQ-3 by monitoring  the Q-Bus signals BDCOK~H and BPOK~H. Assuming  .inx Memory  .inx Battery Power  the system memory is non-volatile (either because of the type of memory used  or because of battery backup), it is possible to recover from a power failure.  .inx System Status Register  .inx Interrupts  When a power failure occurs, the Power Fail bit in the System Status register  (see section 6.7) is set. If interrupts are enabled, an interrupt is  vectored through location 6. Under these conditions, the system has  approximately 3 ms to prepare for power failure.   .inx HDT  .inx RESET  %When power is restored, the PDQ-3 enters a RESET state and the HDT PROM  is invoked (see Appendix A).  .inx Memory  .inx Clocks  .inx Interval Timer  .inx USART  .inx Baud Rate  If the memory can be determined to be intact, processing is  resumed at the point of power failure. Note that the USART baud rate, the  System clock rate, and the Interval Timer rate are reset to their  initial values. If memory cannot be determined to  .inx Bootstrapping  be intact, the PDQ-3 is bootstrapped either into HDT or into the operating  .inx Jumpers  system according to the E12 jumper (see section 3.2.1).    .page3  _6.5 Bus Error_   .inx Bus Error  %A Bus ErG ror on the PDQ-3 is triggered by an access to a non-existent  .inx I/O Devices  .inx Memory  memory or  I/O device address.  A device failing to respond to the assertion of SYNC causes the  bus master to continue to assert SYNC. The duration of the SYNC signal  is monitored by bus timeout logic. If SYNC persists beyond  15 micro`seconds,  the Bus Error recovery logic is initiated. This logic sets the Bus  .inx System Status Register  .inx REPLY  Error bit in the System Status register (see section 6.7) and asserts  REPLY to complete the cycle. If  .inx Interrupts  interrupts are enabled, an interrupt is vectored through location 2.    .page3  _6.6 Interfacing the WD-Bus to the Q-Bus_ -  .inx WD-Bus  .inx Q-Bus  %The Data/Address lines and signals referred to in this section are  described in detail in the sections on the Q-Bus (see chapter 5) and WD-Bus (see  section 6.1).   .inx CPU Module  %The WD-Bus connects all modules internal to the CPU module. This bus  interfaces to the Q-Bus through the Q-Bus interface.  The on-board WD-Bus provides connections between the fol`low`ing de`vices:   .page14  .option(F-) %-- Processor Control chip (see section 6.2.0) %-- Processor Data chip (see section 6.2.1) %-- Real-Time Clock chip (see section 6.9) %-- DMA Controller (see section 6.11.1) %-- Floppy Disk Controller (see section 6.11.0) %-- USART (see section 6.10) %-- HDT PROMs %-- System Environment Switches (see section 6.8) %-- System Status Register (see section 6.7) %-- on-board Address Registers %-- on-board Address Decoder %-- WD-Bus Control Signal Buffer Drivers %-- Q-Bus Buffer Drivers %-- Processor Address Buffer Drivers  .option !  %The WD-Bus Control Signal Buffer Drivers, the WDAL Buffer Drivers, and  the Processor Address Buffer Drivers are  necessary for electrical driving capacities. In addition, the Processor  .inx BDAL Lines  Address Buffer Drivers interface the CPU address with the Q-Bus BDAL  address lines.    .page3  _6.6.0 Address and Data Lines_   .inx WDAL Lines  .inx Bus Master  %When the CPU is the bus master, the WDAL lines carry word addresses.  .inx BDAL Lines  The Q-Bus BDAL lines always carry byte addresses.  In order to interface a CPU word address to a Q-Bus byte address,  the CPU address is shifted left one bit (doubled) by the Processor Address  Buffer Driver. Hence, WDAL0 becomes BDAL1, and BDAL0 is always driven to 0.   .inx DMA Controller  %When the DMA Controller is the bus master, the WDAL lines carry byte  addresses. All addresses are buffered by the WDAL Buffer Drivers, and  no shifting is necessary.   %The WDAL lines are interfaced to the Q-Bus BDAL lines by standard DEC  drivers, receivers and transceivers. Their Q-Bus timing sequence is  .inx Clocks  derived from the 10 MHz master clock.    .page3  _6.6.1 Control Lines_   .inx SYNC  .inx DIN  .inx DOUT  .inx W/R  .inx BSYNC  .inx BDIN  .inx BDOUT  .inx BWTBT  %The WD-Bus control signals SYNC, DIN, DOUT, and W/R are mapped onto the  Q-Bus as BSYNC, BDIN, BDOUT, and BWTBT by standard DEC drivers. The Q-BH us  BRPLY signal is received by a standard DEC receiver, and controls the WD-Bus  REPLY signal. COMPUTE is con`trolled by the Q-Bus BHALT~L signal. It is  ne`gated when BHALT~L is asserted. RESET is con`trolled by the Q-Bus signal  BINIT~L. It is asserted when`ever BINIT~L is asserted. The Q-Bus signal  BBS7 is asserted during address time when address bits 13, 14, 15, and 16  are asserted. All Q-Bus timing is con`trolled by a timing se`quence de`rived  .inx Clocks  from the 10 MHz master clock.    .page3  _6.6.2 Interrupt Lines_   .inx Interrupts  .inx BIRQ  %The Q-Bus interrupt signal BIRQ~L is "OR"ed with other on-board device  inter`rupt re`quest lines to gen`erate the WD-Bus I0 signal.  .inx IACK  .inx BIACK  The Q-Bus signal BIAKO~L is con`trolled by the WD-Bus IACK signal, which  propa`gates through all on-`board devices. If no on-`board de`vice is  re`questing inter`rupt service, BIAKO~L will be asserted when IACK is  asserted. Other`wise, the on-`board de`vice blocks the prop`agation  of IACK and BIAKO~L remains ne`gated.    .page3  _6.6.3 DMA Lines_   .inx DMA Controller  %The Q-Bus DMA request line BDMR~L is "OR"ed with the request of the  on-`board DMA Con`troller to gen`erate a DMA re`quest to the processor.  .inx DMGO  .inx BDMGO  The DMA grant logic generates a bus grant signal, DMGO. This signal  prop`agates through the on-`board DMA Con`troller. If the DMA Controller  is not re`questing the bus, the Q-Bus signal BDMGO~L is asserted when  DMGO is asserted. Other`wise, the on-`board con`troller blocks the  prop`agation of DMGO and BDMGO~L re`mains ne`gated.    .page3  _6.7 System Status Register_ !  .inx System Status Register  %The System Status register is an 8-bit read/write register that  provides the means to effect the status of PDQ-3 CPU Module on-board devices,  and provides information concerning the status of those devices. Its word  address is FC24 (hex). It occupies the  least significant byte of a 16-bit word;  the most significant byte is undefined. The register is defined as follows:   .option(F-)  .page4 @BITS  .title PDQ-3 Hardware User's Manual  .subtitle Appendix A: Hexadecimal Debugging Tool (HDT)  .odd  .inx HDT  _A. HEXADECIMAL DEBUGGING TOOL (HDT)_   .inx I/O Devices  .inx Debugging  .inx Memory  .inx Bootstrapping  .inx UCSD Pascal  %The Hexadecimal Debugging Tool (HDT) is a powerful, low level  debugger capable of examining memory, examining I/O device reg`i`sters,  bootstrapping the UCSD Pascal system,  and recovering from power failures. It is implemented as a UCSD Pascal  .inx CPU Module  program resident in PROMS located on the PDQ-3 CPU Module. The PROMS  occupy memory locations F400 hex through F7FF hex. HDT uses memory  between 22 and 25 hex and 100 and 130 hex for temporaries.    _A.1 Invoking HDT_   %HDT is activated under one of the following con`ditions:  .margin(L+5)   .undent3  .inx Jumpers  --~ Initiation of the BDCOK L signal on the Q-Bus. HDT is automatically  executed when the BDCOK L signal is negated. (This will cause a full  system reset). I  If the E14 jumper is installed on the PDQ-3 CPU Module (see section 3.2.1),  HDT immediatly attempts to boot`strap the UCSD Pascal system from the  boot`strap device.  If the E12 jumper is installed, HDT prints a '#' on  the console and waits for an HDT command. Activating the 'R' command causes  HDT to boot the UCSD Pascal system from the bootstrap device.   .inx Powering Up  .inx Power Fail  .undent3  --~Initial power up. HDT checks for a power fail restart in progress.  If a restart is in progress, HDT restarts the UCSD Pascal system at  the point where  a power failure interrupted it. If a restart is not in progress, HDT  behaves as if it were an initial power up sequence.   .inx Priority  .inx Console CRT  .undent3  --~Invocation of the control-p key. HDT is invoked as a high priority  process (priority 255) and the UCSD Pascal system is suspended.  It prints a '#' on the console and waits for an  .inx Interrupts  .inx UCSD Pascal  HDT command. During the execution of HDT, all interrupts are latcheä and  any outstanding DMA operations continue. Re`sump`tion of the UCSD Pascal  system occurs on receipt of the 'P' command from the console.   .undent3  --~Invocation of the HALT procedure from a Pascal program. This invokes  HDT in the same manner as the invocation of the conrtol-p key.  .margin     _A.2 HDT Commands_   %HDT can be commanded to examine and modify a 'current location' in memory,  boot the UCSD Pascal system from the bootstrap device, or proceed with a  UCSD Pascal program currently executing. All numbers are input and output  by HDT in hexadecimal format (eg. 1 hex = 1 decimal, A hex = 10 decimal,  and 10 hex = 16 decimal). All addresses point to 16-bit word quantities.  The commands are as follows:   .margin(L+5)  .inx Bootstrapping  .undent4  'R'~HDT reboots the UCSD Pascal system from the bootstrap device  specified by for standard systems as follows (custom systems may  differ):   .margin(L+5)  .undent3  --~If is empty, the PDQ-3 boots as if were 0.   .undent3  --~If is 0, the PDQ-3 boots from the left single-sided floppy disk drive.   .undent3  --~If is 1, the PDQ-3 boots from the right single-sided floppy disk drive.   .undent3  --~If is 4, the PDQ-3 boots from the left double-sided floppy disk drive.   .undent3  --~If is 5, the PDQ-3 boots from the right double-sided floppy disk drive.  .margin   .inx UCSD Pascal  .undent4  'P'~The currently executing UCSD Pascal program is resumed.   .undent4  .inx Memory  '/'~If a number has been entered, that number becomes the new current  location. HDT then displays the contents of the new current location.   .inx Memory  .undent5  ~If a number has been entered, that number is stored into the current  location. HDT then displays the HDT prompt '#'.   .inx Memory  .undent5  ~If a number has been entered, that number is stored into the current  location. HDT then increments the current location, and displays  the contents of the new current location.   .inx Memory  .undent4  '^'~If a number has been entered, that number is stored into the current  location. HDT then decrements the currJ ent location, and displays  the contents of the new current location.   .inx Memory  .undent4  '@'~If a number has been entered, that number is stored into the current  location. The contents of the current location then becomes  the new current location, and HDT  displays the contents of the new current location.  .margin  .subtitle Appendix B: Reserved Memory Locations  .page  .inx Memory  _B. RESERVED MEMORY LOCATIONS_   _B.0 Bus Address Assignments_   .inx I/O Devices  %Since I/O device registers are mapped into the mem`ory space,  loca`tions F000 through FFFF are  .inx CPU Module  re`served for these registers. The PDQ-3 CPU Module on`board 'devices'  are as`signed ad`dresses  F400 through F7FF and FC00 through FC7F.   _B.0.1 PDQ-3 Onboard Device Addresses_   .inx Interrupt Vectors  %The following word addresses and inter`rupt vec`tors  are as`signed to de`vices lo`cated on the PDQ-3 CPU Module:   .option( F- )  DEVICE ADDRESS  INTERRUPT VECTOR   .inx HDT  HDT ROM F400 (lowest)  F5FF (CPU Module Serial #) FF7FF (highest)  .inx USART Control Register #1  .inx USART Control Register #2  Console terminal control register 1 FC10  Console terminal control register 2 FC11  .inx USART Status Register  Console terminal status register FC12  .inx Receiver Holding Register  Console terminal input register FC13 000E  .inx Transmitter Holding Register  Console terminal output register FC14 0012 (data) R0016 (protocol)  .inx Switches  System environment switch FC18 0002 (bus error) R0006 (pwr fail)  .inx Clocks  .inx Baud Rate Clock Counter  Console baud rate generator FC20  .inx System Clock Counter  System clock counter FC21 001A  .inx Interval Timer  Interval timer FC22 001E  .inx Counter Mode Register  Timer mode control byte FC23   .inx System Status Register  System status register FC24   .inx Floppy Disk Interface Registers  .inx Floppy Status Register  .inx Floppy Command Register  Floppy disk status/command register FC34  000A  .inx Track Register  Floppy disk track register FC35  .inx Sector Register  Floppy disk sector register FC36  .inx Floppy Data Register  Floppy disk data register FC37   .inx DMA Interface Registers  .inx DMA Command Register  DMA controller command register FC38 000A  .inx DMA Status Register  DMA controller status register FC39  .inx Byte Count Registers  DMA controller byte transfer count FC3A (low) FFC3B (high)  .inx Memory Address Registers  DMA controller memory start address FC3C (low) E FC3D (high)  DMA controller memory extension FC3E   Reserved FC4x  Reserved FC5x  .inx HDT  Pointer to HDT ROM FC68  Reserved FC6x  Reserved FC7x   NOTE: x = don't care  .option  .page  _B.0.2 Q-Bus Device Addresses_   .inx Q-Bus  .inx Interrupt Vectors  %AddresK ses are reserved for certain devices on the Q-Bus. Their word  addresses and interrupt vectors are as follows:   .option ( F- )  DEVICE FIRST LAST VECTOR   Reserved F000 F003  IEEE std.~488 IBV11-A F033 F036 008A  bus interface  Parallel line DRV11 #3  0000-007F "unit  Parallel line DRV11 #2 0000-007F "unit  Parallel line DRV11 #1 0000-007F "unit  Analog-to-digital ADV11-A F880 F882  0084 "converter  Programmable RTC KWV11-A F889 F897 0090  Digital-to Analog AAV11-A F890 F893 "converter  Parallel line DRV11-B #1 FA84 FA87 002A "unit  Parallel line DRV11-B #2 FA88 FA8B 0000-00FF "unit  Parallel line DRV11-B #3 FA8C FA8F 0000-00FF "unit  Magnetic Tape  TM-11 FAA8 FAAE 004A  256 word ROM BDV11 FB00 FB5F  .inx Floppy Disk Drives  RX01 Floppy disk RXV11 FE3C FE7E 005A  .inx Mass Storage  Hard Disk RP-02 FEE0 FEEE  0056  RKO5 Mass storage RKV11 FF80 FF87 0048  .inx Printer  Printer LAV11,LPV11 FFA6 FFA7 0040  Terminals: "partial modem DLV-11 FEB8 FFBB 0030 $control "full modem DLV-11 E FEB8 FEBB 0030 $control "no modem DLV-11 F FEB8 FEBB 0030 $control "4 channel with DLV-11 J FEB8 FEBB 0030 $partial modem FFA0 FFAE 006x  control   .option  .subtitle Appendix C: Recommended CRTs  .page   .inx Console CRT  _C. RECOMMENDED CRTs_  .option( F- )    MODEL COMPANY   Elite 1521A DataMedia (manufacturer)  .undent1  *Elite 3052A 7300 North Crescent Blvd.  DT80-1 Pennsauden, NJ 08110 :(609) 665-2382 :  .undent1  *Zephyr Zentec Corporation (manufacturer) :2400 Walsh Ave. :Santa Clara, CA 95050 :(408) 246-7662 8  IQ120 Soroc Corporation (manufacturer)  .undent1  *IQ140 165 Freedom Ave. :Anaheim, CA 92801 :(714) 992-2860 :  .undent1  *Z-19 Advanced Digital Products (distributor) :7584 Trade St. :San Diego, CA 92121 :(714) 578-9595   .undent1  * Highly recommended  .option  .subtitle Appendix D: Cabling Recommendations  .page  .inx Cabling  _D. CABLING RECOMMENDATIONS_   _D.0 Cable Length vs Baud Rate_   .inx Baud Rate  .inx CPU Module  %The recommended maximum cable lengths  for the baud rates supported by the PDQ-3 CPU Module are:   .option(F-) 0Baud Rate Cable Length @(ft) (m) 2 3110 400 122 3300 400 122 3600 400 122 21200 400 122 22400 400 122 24800 200 61 29600 100 30.5 119200  50 15.25  .option   %Bellden 2464 cable or the equivalent is recommended.    _D.1 PDQ-3 Cable Requirements_ L   .inx RS-232C  .inx Printer  %The use of the RS-232C console connector on the PDQ-3 CPU module is  multiplexed between terminal data and printer data. All terminal data  is transmitted on the primary transmission lines, and all printer data  is transmitted on the secondary lines. Thus, an RS-232C cable that services  both a terminal and a printer must start with a common connector to the  PDQ-3 CPU Module console connector, then split into a terminal cable and  a printer cable. Such a cable is avail`able with the PDQ-3 System and is  wired as follows:   .page13  .inx CPU Module  .option(F-) 7 ACONNECTED PINS 3 3PDQ-3 CPU Module Terminal Connector 3 31 (Signal Ground)* 1 (Frame Ground) 32 (Recv Data) 2 (Xmit Data) 33 (Xmit Data) 3 (Recv Data) 37 (Signal Ground) 7 (Signal Ground) 216 (Car Det) 4 (Clear To Send) 220 (Data Set Rdy) 20 (Data Term Rdy)  .option   %Note: On the PDQ-3 CPU Module cable end, pins 4 (CTS) and 5  (RTS) must be shorted. On the Terminal Connector, pins 4 (RTS),  5 (CTS), and 8 (CARD) must be shorted.  .inx RS-232C  %Using this cable it is possible to communicate with any RS-232C terminal  in full duplex. If handshaking is necessary, it must be carried out using  a data sequence such as X-ON, X-OFF.    .subtitle Appendix E: Reference Materials  .page  _E. Reference Materials_  .inx Reference Materials  .margin(L+5)  .option ( F- )   .undent4  ***~PDQ-3 System User's Manual Advanced Computer Design   PDQ-3 Programmer's Manual Advanced Computer Design   Programming in Pascal Peter Grogono DAddison-Wesley FPublishing Co., Inc. DReading, Mass., 1978   Beginner's Guide For the Kenneth Bowles, UCSD  UCSD Pascal System Byte Publications, Inc. @  Pascal User's Manual & Report Jensen & Wirth DSpringer-Verlag DNew York, 1974 !  Microcomputer Handbook Digital Equipment Corp. DDigital Publishing Corp. DMaynard, Mass., 1979 @ C  .undent4  ***~ADDENDA Advanced Computer Design  .option  .margin %  .margin(L+5)  .undent4  ***~Provided by Advanced Computer Design as refer`ence mater`ial with  this manual.  .margin  .page  .subtitle Appendix F: Memory Modules   _F. Memory Modules_  .inx Memory Modules   %A wide variety of Q-Bus memory devices may be used with the PDQ-3T  system because of the systems ability to interface with the Q-Bus. There  are several factors to consider when obtaining a memory device for the  PDQ-3T system. The CPU needs the top 4K words of memory to address  peripheral devices and system con`trol-`status registers. The minimum  memory needed to run the operating system is 32K words. The maximum  amount of memory that the system can address is 64K words. A nominal  cycle time for the memory would be 500 nsec. with a 300 nsec. access  time. ACD will provide a list of authorized memory vendors upon request.