IMD 1.18: 6/12/2012 18:57:18 sys 29/10a microprogram support #2 version 2.0 pn 4120026-006    AM29CPU DEF AM29CPU DEFEDISKCTLRDEF !"#$%&'()*DISKCTLRDEF'+,-./uct ; without notice in order to improve design and performance characteristics. ; The company assumes no responsibility for t AM29CPU.DEF FILE ; ****************************************** ; ; This file was created to serve as a master cpu file. The CONTROLRDEF0123456789:;<=>?CONTROLRDEFU@ABCDEFGHIJDISKCTLRSRCKLMNOPQRSTUVWXYZDISKCTLRSRC}[\]^_`abcdefghijhe use of any circuits or programs ; described herein. EJECT ; ; ; WORD 64 ; ; 13 DECEMBER 1976 JRM ; UPDATED SEPT 28,user must ; edit it as required for his/her particular application. ; ; ; ; Anyone finding errors in this file is requestedAM29203 SRCKklmnopqrstCONTROLRSRC#uvwxyDISK DOC|z{|}~CHKSUM DAT 1977 ; UPDATED APRIL 16, 1981 DEW ; UPDATED MAY 15, 1981 DEW ; UPDATED JAN 12, 1982 DEW ; ; INDEX: ; Am2901 [1], [ to send a marked listing ; or portion thereof to: AMD CUSTOMER EDUCATION CENTER ; 490-A LAKESIDE DRIVE ; PO ; ***************************************************** TITLE Am2900 FAMILY C P U MNEMONICS JAN 12, 1982 DEW ; ******2], [3] ; Am2914 [5] ; Am2930 [6] ; Am2932 [7] ; Am2940 [8] ; Am2903 [9], [10], [11], [12] ; Am29203 [9], [11], [13], [14]BOX 453 MS#71 ; SUNNYVALE, CA 94086 ; ; ; Advanced Micro Devices reserves the right to make changes in its prod*********************************************** ; ; ; ****************************************** ; Am2900 FAMILY MNEMONICS -  ; THREE-ADDRESS EXPANDED MEMORY SAMPLE [15], [16], [17], [18] ; MISCELLANEOUS FIELDS ; REGISTERS [R] ; CARRY BIT (NOT Am2n with DEF statements which include the ; very same fields, SUB statements are included here for a reference ; example. The u [3] ; QREG.01: EQU Q#0 NOP.01: EQU Q#1 RAMA.01: EQU Q#2 RAMF.01: EQU Q#3 RAMQD.01: EQU Q#4 RAMD.01: EQU Q#5 RAMQU.01: EQU H#4 ; CLEAR INTERRUPT FROM LAST VECTOR READ RDVC: EQU H#5 ; READ VECTOR RDSTA: EQU H#6 ; READ STATUS REGISTER RDM: EQU H# * * * * * * * * * * * * * * * * * * * * * * ; ; Am2901 SOURCE OPERANDS (R S) [1] ; AQ: EQU Q#0 AB: EQU Q#1 ZQ: E reference. Whichever method is chosen, DOCUMENT THE STATEMENTS. ; ; NOTE THAT, if the sequencer fields had been defined, the904) [19] ; Am2910 [20] ; Am29811 ADDED INSTRUCTION ; Am2925 MICROPROGRAMMABLE CLOCK CYCLE SELECT + CONTROL LINES [21] ; Am2se of SUB statements to partially define a microword ; allows a SUB to be defined immediatly after the mnemonics of the ; indiEQU Q#6 RAMU.01: EQU Q#7 ; EJECT ; ; ; EXAMPLE SUB STATEMENTS ; ALU: SUB 3VQ#0, 3VQ#0, 3VQ#1, 2VB#00 ; Am2901 FIEL7 ; READ MASK REGISTER SETM: EQU H#8 ; SET MASK REGISTER LDSTA: EQU H#9 ; LOAD STATUS REGISTER BCLRM: EQU H#A ; BIT CLEAR MASQU Q#2 ZB: EQU Q#3 ZA: EQU Q#4 DA: EQU Q#5 DQ: EQU Q#6 DZ: EQU Q#7 ; ; Am2901 ALU FUNCTIONS (R FUNCTION S) [2] ; *** T 19X above could ; have been replaced by the sequencer SUB statement name. EJECT ; ; * * * * * * * * * * * * * * * * ; ; 904 SHIFT EXAMPLES ; Am2904 STATUS REGISTER EXAMPLES ; Am2904 CONDITION CODE OUTPUT EXAMPLES ; MORE MISCELLANEOUS FIELDS ; vidual fields. The DEF statement may be defined after all of the ; SUB statements to which it refers are defined. The DEF staDS ONLY ; SOURCE FUNCT DEST CARRY ; REGS: SUB 4VH#0, 4VH#0 ; ALU REGISTER ADDRESSES ; RA RB ; SAK REGISTER BSETM: EQU H#B ; BIT SET MASK REGISTER CLRM: EQU H#C ; CLEAR MASK REGISTER DISIN: EQU H#D ; DISABLE INTERRUPT REQUO USE: DELETE THE .01 AND DELETE THE Am2903/29203 INSTRUCTION SETS *** ; ADD.01: EQU Q#0 SUBR.01: EQU Q#1 SUBS.01: EQU Q#2 Am2914 INSTRUCTION SET [5] ; ; * * * * * * * * * * * * * * * * ; MCLR: EQU H#0 ; MASTER CLEAR CLRIN: EQU H#1 ; COUTPUT ENABLE ; INSTRUCTION ENABLE ; CONDITION CODE MUX - DATA MONITOR PROBLEM ADDITION ; EXAMPLES OF DEF STATEMENTS - TWO tements are then ; more readable. The comments which would appear with a DEF statement would ; then appear with the SUB statemMPLE: DEF 19X, ALU, REGS, 2VB#00, 24X ; USAGE OF SUB STATEMENTS ; SEQ MUX etc. ; ; Although the file is writteEST LDM: EQU H#E ; LOAD MASK REGISTER ENIN: EQU H#F ; ENABLE INTERRUPT REQUEST ; EJECT ; * * * * * * * * * * * * * * * * *  OR.01: EQU Q#3 AND.01: EQU Q#4 NOTRS.01: EQU Q#5 EXOR.01: EQU Q#6 EXNOR.01: EQU Q#7 ; ; Am2901 DESTINATION CONTROL LEAR ALL INTERRUPTS CLRMB: EQU H#2 ; CLEAR INTERRUPTS FROM M-BUS CLRMR: EQU H#3 ; CLEAR INTERRUPTS FROM MASK REGISTER CLRVC: ADDRESS - NONEXPANDED MEMORY EJECT ; ; * * * * * * * * * * * * * * * * * * * * * * * * ; ; Am2901 INSTRUCTION SET ; ; * *ent (what the field is, what the default ; represents, etc.). This file has been written with both versions to ; provide a * ; ; Am2930 PROGRAM CONTROL UNIT [6] ; ; * * * * * * * * * * * * * * * * * * ; ; NON-CONDITIONAL INSTRUCTIONS ; PR H#6 ; PUSH PC RTS.32: EQU H#7 ; RETURN STACK FR.32: EQU H#8 ; FETCH R FPR.32: EQU H#9 ; FETCH PC PLUS R FPLRH#1D: ; RETURN S PLUS D CHLD: EQU 5H#1E: ; HOLD PSUS: EQU 5H#1F: ; SUSPEND ; EJECT ; * * * * * * * * * * * * * * * * * * ;EQUALS ONE, DECREMENT ADDRESS COUNTER WCCD: EQU 8Q#5% ; WORD COUNT COMPARE, DECREMENT ADDRESS COUNTER ADCD: EQU 8Q#6% ; ADDRES - FAIL TEST, EXECUTE FPC ; JMPR: EQU 5H#10: ; JUMP R JMPD: EQU 5H#11: ; JUMP D JMPZ: EQU 5H#12: ; JUMP ZERO JPRD: EQU 5H#DRESS COUNTER REIN: EQU Q#4 ; REINITIALIZE COUNTERS LDAD: EQU Q#5 ; LOAD ADDRESS LDWC: EQU Q#6 ; LOAD WORD COUNT ENCT: EQU QST: EQU 5H#00: ; RESET FPC: EQU 5H#01: ; FETCH PC FR: EQU 5H#02: ; FETCH R FD: EQU 5H#03: ; FETCH D FRD: EQU 5H#04: ; FETCH .32: EQU H#A ; FETCH PC, LOAD R JMPR.32: EQU H#B ; JUMP R JPPR.32: EQU H#C ; JUMP PC PLUS R JSBR.32: EQU H#D ; JU ; Am2932 PROGRAM CONTROL UNIT [7] ; ; * * * * * * * * * * * * * * * * * * ; ; TO USE: DELETE THE .32 FROM Am2932 MNEMONS COMPARE, DECREMENT ADDRESS COUNTER WCOD: EQU 8Q#7% ; WORD COUNTER CARRY OUT, DECREMENT ADDRESS COUNTER ; EJECT ; * * * * *13: ; JUMP R PLUS D JPPD: EQU 5H#14: ; JUMP PC PLUS D JPPR: EQU 5H#15: ; JUMP PC PLUS R JSBR: EQU 5H#16: ; JUMP SUBROUTINE R #7 ; ENABLE COUNTERS ; ; CONTROL MODE BYTE ; NOTE - BITS 3 THROUGH 7 ARE DON'T CARE ; WC1I: EQU 8Q#0% ; WORD COUNT EQUALS OR PLUS D FPD: EQU 5H#05: ; FETCH PC PLUS D FPR: EQU 5H#06: ; FETCH PC PLUS R FSD: EQU 5H#07: ; FETCH S PLUS D FPLR: EQU 5H#0MP SUBROUTINE R JSPR.32: EQU H#E ; JUMP SUBROUTINE PC PLUS R PLDR.32: EQU H#F ; LOAD R EJECT ; * * * * * * * * * * * *ICS IF NEEDED ; AND DELETE THE Am2930 INSTRUCTION SET ; PRST.32: EQU H#0 ; RESET PSUS.32: EQU H#1 ; SUSPEND PSHD.32:  * * * * * * * * * * * * * * * * * * * * * * * * * ; ; Am2903 INSTRUCTION SET ; ; * * * * * * * * * * * * * * * * * JSBD: EQU 5H#17: ; JUMP SUBROUTINE D JSBZ: EQU 5H#18: ; JUMP SUBROUTINE ZERO JSRD: EQU 5H#19: ; JUMP SUBROUTINE R PLUS D JSPNE, INCREMENT ADDRESS COUNTER WCCI: EQU 8Q#1% ; WORD COUNT COMPARE, INCREMENT ADDRESS COUNTER ADCI: EQU 8Q#2% ; ADDRESS COMPAR8: ; FETBH PC, LOAD R FRDR: EQU 5H#09: ; FETCH R PLUS D, LOAD R PLDR: EQU 5H#0A: ; LOAD R PSHP: EQU 5H#0B: ; PUSH PC PSHD: E * * * * * * * ; ; Am2940 DMA CONTROL UNIT [8] ; ; * * * * * * * * * * * * * * * * * * * ; INSTRUCTIONS ; WRCR: EQUEQU H#2 ; PUSH D POPS.32: EQU H#3 ; POP STACK FPC.32: EQU H#4 ; FETCH PC JMPD.32: EQU H#5 ; JUMP D PSHP.32: EQU * * * * * * * * * * * * * ; ; ALU SOURCE OPERANDS (EA, I0, OEB) [9] ; 16 REGISTER - TWO ADDRESS VERSION ; ; NOTE: USE FD: EQU 5H#1A: ; JUMP SUBROUTINE PC PLUS D JSPR: EQU 5H#1B: ; JUMP SUBROUTINE PC PLUS R RTS: EQU 5H#1C: ; RETURN S RTSD: EQU 5E, INCREMENT ADDRESS COUNTER WCOI: EQU 8Q#3% ; WORD COUNTER CARRY OUT, INCREMENT ADDRESS COUNTER WC1D: EQU 8Q#4% ; WORD COUNT QU 5H#0C: ; PUSH D POPS: EQU 5H#0D: ; POP S POPP: EQU 5H#0E: ; POP PC PHLD: EQU 5H#0F: ; HOLD ; ; CONDITIONAL INSTRUCTIONS Q#0 ; WRITE CONTROL REGISTER RDCR: EQU Q#1 ; READ CONTROL REGISTER RDWC: EQU Q#2 ; READ WORD COUNTER RDAC: EQU Q#3 ; READ AD OR BOTH THE Am2903 AND THE Am29203 * * * ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; RAMAB: EQU F TO RAM, LOGICAL DOWN SHIFT RAMQDA: EQU H#2 ; DOUBLE PRECISION ARITHMETIC DOWN SHIFT RAMQDL: EQU H#3 ; DOUBLE PRECISQU H#A ; F = R EXNOR S EXOR.03: EQU H#B ; F = R EXOR S AND.03: EQU H#C ; F = R AND S NOR.03: EQU H#D ; F = R NOR S NANERSION SLN.03: EQU H#8 ; SINGLE LENGTH NORMALIZE DLN.03: EQU H#A ; DOUBLE LENGTH NORMALIZE DIVFRST.03: EQU H#A ; TWO'] ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; SPECL.03: EQU H#0 ; I0 MUST BE LOW HIGH.03: EQU H#0 ; I0#F ; F TO Y, SIGN EXTEND LEAST SIG. BYTE EJECT ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; SPECIAL FUNC Q#0 ; RAM A PORT, RAM B PORT RAMADB: EQU Q#1 ; RAM A PORT, DATA BUS B RAMAQ: EQU Q#2 ; OR Q#3 - RAM A PORT, Q REGISTION LOGICAL DOWN SHIFT RAM: EQU H#4 ; F TO RAM WITH PARITY QD: EQU H#5 ; F TO Y, DOWN SHIFT Q LOADQ: EQU H#6 ; F TO Q WD.03: EQU H#E ; F = R NAND S OR.03: EQU H#F ; F = R OR S EJECT ; * * * * * * * * * * * * * * * * * * * * * * * ; ; ALU DS COMPLEMENT DIVIDE FIRST STEP DIVIDE.03: EQU H#C ; TWO'S COMPLEMENT DIVIDE MIDDLE STEPS DIVLAST.03: EQU H#E ; TWO'S COMP MUST BE HIGH (Q REGISTER SELECT) SUBR.03: EQU H#1 ; F = S - R - 1 + Cin SUBS.03: EQU H#2 ; F = R - S - 1 + Cin ADD.03: EQTIONS (I8-I7-I6-I5) [12] ; ; ; Am2903 FUNCTIONS ONLY ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *ER DARAMB: EQU Q#4 ; DATA BUS A, RAM B PORT DADB: EQU Q#5 ; DATA BUS A, DATA BUS B DAQ: EQU Q#6 ; OR Q#7 - DATA ITH PARITY RAMQ: EQU H#7 ; F TO RAM AND Q WITH PARITY RAMUPA: EQU H#8 ; F TO RAM, ARITHMETIC UP SHIFT RAMUPL: EQU H#9 ;ESTINATION CONTROL ( I8 - I7 - I6 - I5) [11] ; NORMAL FUNCTIONS ; ; NOTE: USE FOR BOTH THE Am2903 AND THE Am29203 * * * LEMENT DIVIDE LAST STEP ; EJECT ; ********************************************************************** ; NEW! NEW! NEWU H#3 ; F = R + S + Cin INCRS.03: EQU H#4 ; F = S + Cin INCSNON.03: EQU H#5 ; F = NOT S + Cin INCRR.03: EQU H#6 ; F = ; MULT.03: EQU H#0 ; UNSIGNED MULTIPLY TWOMULT.03: EQU H#2 ; TWO'S COMPLEMENT MULTIPLY TWOLAST.03: EQU H#6 ; TWO'S COMBUS A, Q REGISTER ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; ALU FUNCTIONS - NORMAL MODE (I4, I3, I2, F TO RAM, LOGICAL UP SHIFT RAMQUPA: EQU H#A ; DOUBLE PRECISION ARITHMETIC UP SHIFT RAMQUPL: EQU H#B ; DOUBLE PRECISION LOGI* ; ; * * * * * * * * * * * * * * * * * * * * * * * ; RAMDA: EQU H#0 ; F TO RAM, ARITHMETIC DOWN SHIFT RAMDL: EQU H#1 ;! NEW! NEW! NEW! NEW! NEW! NEW! NEW! ; ; Am29203 INSTRUCTION SET - 5/15/81 - DEW ; ; * * * * * * * * * * * * * R + Cin INCRNON.03: EQU H#7 ; F = NOT R + Cin LOW.03: EQU H#8 ; F = LOW NOTRS.03: EQU H#9 ; F = NOT R AND S EXNOR.03: EPLEMENT MULTIPLY LAST STEP INCRMNT.03: EQU H#4 ; INCREMENT BY 1 + Cin SGNTWO.03: EQU H#5 ; SIGN MAGNITUDE-TWO'S COMPL CONV I1, I0 ALL NOT 0) ; Am2903 ONLY ! * * * TO USE, DELETE THE .03 AND TAG OR ; DELETE THE Am29203 FUNCTIONS * * * ; [10CAL UP SHIFT YBUS: EQU H#C ; F TO Y ONLY QUP: EQU H#D ; F TO Y, UP SHIFT Q SIGNEXT: EQU H#E ; SIO0 TO Yi RAMEXT: EQU H  * * * * * * * * * * * * * * * * * * * * * * * ; ; Am29203 SOURCE SELECT - SEE Am2903 SOURCE SELECTION (SAME) ; TWO - ADDRESS USE SPECIL.2: EQU H#8 ; SPECIAL FUNCTIONS (MULTI-BCD) EJECT ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; Fi = Ri NOR Si NAND: EQU H#E ; Fi = Ri NAND Si OR: EQU H#F ; Fi = Ri OR Si ; ; * * THE FOLLOWING REQ BCD.ADD: EQU H#B ; BCD ADD BCD.SUBS: EQU H#D ; BCD SUBTRACT Fi = Ri - Si - 1 + Cin [BCD] BCD.SUBR: EQU H#F ; BCD SUBTRACT Fi S ARE GROUPED ACCORDING TO THE RESTRICTION ; ; ; * * THE FOLLOWING DO NOT HAVE RESTRICTIONS ON THE SOURCE SELECTION * * ; SH#3 ; DECREMENT BY 1 OR 2 INCRMNT: EQU H#4 ; INCREMENT BY 1 OR 2 SGNTWO: EQU H#5 ; SIGN MAGNITUDE-TWO'S COMPLEMENT CONVERSION OPERATION ONLY ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; * * * * * * * * * * * * * *  * * * * * ; ; DESTINATION CONTROL - SEE Am2903 DESTINATION (SAME) ; ; ; * * * * * * * * * * * * * * * * * * * * * * * * *UIRE THAT RAMAQ OR DAQ BE THE SELECTED SOURCE * * ; HIGH: EQU H#0 ; Fi = HIGH INCRR: EQU H#6 ; Fi = Ri + Cin INCRNON: EQ= Si - Ri - 1 + Cin [BCD] ; ; THE FOLLOWING ARE USED WITH SPECIL.2: ; MULTIBCD: EQU H#1 ; MULTIPRECISION BCD TO BINARY CONVEUBR: EQU H#1 ; Fi = Si - Ri - 1 + Cin SUBS: EQU H#2 ; Fi = Ri - Si - 1 + Cin ADD: EQU H#3 ; Fi = Ri + Si + C SLN: EQU H#8 ; SINGLE LENGTH NORMALIZE DLN: EQU H#A ; DOUBLE LENGTH NORMALIZE DIVFRST: EQU H#A ; TWO'S COMPLEMENT DIVIDE -* * * * * * * * * * * * * * * * * * * * * * ; ; Am29203 ALU FUNCTIONS - NORMAL MODE ( I4, I3, I2, I1, I0 ALL NOT 0 ) ;  * * * * * * * * * * * ; ; Am29203 SPECIAL FUNCTIONS [14] ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * U H#7 ; Fi = ~Ri + Cin LOW: EQU H#8 ; Fi = LOW ; ; * * THE FOLLOWING REQUIRE THAT Q IS ** NOT ** IN THE SELECTED SOURCE * RSION MULTIBIN: EQU H#9 ; MULTIPRECISION BINARY TO BCD CONVERSION ; EJECT ; ; * * * * * * * * * * * * * * * * * * * * * * *in INCRS: EQU H#4 ; Fi = Si + Cin INCRSNON: EQU H#5 ; Fi = ~Si + Cin NOTRS: EQU H#9 ; Fi = NOT Ri AND Si EX FIRST STEP DIVIDE: EQU H#C ; TWO'S COMPLEMENT DIVIDE - MIDDLE STEPS DIVLAST: EQU H#E ; TWO'S COMPLEMENT DIVIDE - LAST STEP [13] ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; NOTE DIFFERENCE FROM Am2903 - ** FIVE* * * * * * * * * ; ; INSTRUCTION LINES I8, I7, I6, I5 ; ; THE FOLLOWING ARE USED WITH SPECL: ; MULT: EQU H#0 ; UNSIGNED* ; SPECL: EQU H#0 ; SPECIAL FUNCTIONS RESRVD.1: EQU H#6 ; RESERVED FOR LATER USE RESRVD.2: EQU H#7 ; RESERVED FOR LATER * * * * * * * ; ; ; DEFINITION FILE FOR FIGURE 29, PAGE 2-57, 1980 DATA BOOK ; ; EXPANDED MEMORY FOR THE Am2903 USING THNOR: EQU H#A ; Fi = Ri EXNOR Si EXOR: EQU H#B ; Fi = Ri EXOR Si AND: EQU H#C ; Fi = Ri AND Si NOR: EQU H#DBCD.BIN: EQU H#1 ; BCD TO BINARY CONVERSION BCD.DIV2: EQU H#7 ; BCD DIVIDE BY TWO BIN.BCD: EQU H#9 ; BINARY TO BCD CONVERSION  ** INSTRUCTION FIELDS USED ; IN THE DATA SHEET TABLE - THEREFORE RESTRICTIONS ON THE SOURCE SELECTION ; APPLY. THE FUNCTION MULTIPLY TWOMULT: EQU H#2 ; TWO'S COMPLEMENT MULTIPLY TWOLAST: EQU H#6 ; TWO'S COMPLEMENT MULTIPLY - LAST STEP DECRMNT: EQU  E Am29705 ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; ONLY THE SOURCE FIELDS CHANGE - EXPANDED ; A; MISCELLANEOUS FIELDS ; ; REGISTERS [R] ; * * * * * * * * * * * * * * * * * * * * * ; R0: EQU H#0 R1: EQU H#1 R2: ES 2903 REGISTERS CIS7051:EQU B#01 ; C ADDRESSES FIRST 29705 ADDITION CIS7052:EQU B#10 ; C ADDRESSES SECOND 29705 ADDITION TO REG (F) OR PIPE (T) RFCT: EQU H#8 ; DO LOOP REPEAT UNTIL CTR=0 - STACK RPCT: EQU H#9 ; DO LOOP UNTIL CTR=0 - PIPE CRTNBITS (B5-B4) [16] ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; BINALU: EQU B#00 ; B ADDRESSES 2903 RE * * * * * * * * * * * * ; ; Am2910 MICROPROGRAM CONTROLLER INSTRUCTION SET [20] ; ; * * * * * * * * * * * * * * * * * * *  THIRD ADDRESS FIELD WAS ALSO ADDED (ADDRESS C) ; ; ; ; SOURCE OPERANDS [15] ; ADDED A ADDRESS BITS (A6-A5-A4) ; ; * * EQU H#2 R3: EQU H#3 R4: EQU H#4 R5: EQU H#5 R6: EQU H#6 R7: EQU H#7 R8: EQU H#8 R9: EQU H#9 R10: EQU H#A R11: CBUS: EQU B#11 ; C TO B BUS OUT ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; I0 SOURCE SELECT FIELD RE: EQU H#A ; COND RETURN, POP STACK (T) CJPP: EQU H#B ; COND JUMP PIPELINE, POP STACK LDCT: EQU H#C ; LOAD REGISTER, CONTGISTERS BIS7051:EQU B#01 ; B ADDRESSES FIRST 29705 ADDTION BIS7052:EQU B#10 ; B ADDRESSES SECOND 29705 ADDITION BBUS: EQU B* * * * * * * * * ; JZ: EQU H#0 ; RESET STACK, MICROPC, ADDRESS CJS: EQU H#1 ; COND JUMP SUBROUTINE, PUSH STACK JMAP: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; AINALU: EQU Q#0 ; A ADDRESSES 2903 REGISTERS AIS7051:EEQU H#B R12: EQU H#C R13: EQU H#D R14: EQU H#E R15: EQU H#F ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * PLACES EA-I0-OEB THREE-BIT FIELD ; [18] ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; QREGSEL:EQU B#1 INUE LOOP: EQU H#D ; DO LOOP UNTIL TEST=T - STACK CONT: EQU H#E ; CONTINUE TWB: EQU H#F ; THREE WAY (DEAD MAN TIMER!) #11 ; B FROM BUS ; EJECT ; * * * * * * * * * * * * * * * * * * * * * * * * ; ; THREE ADDRESS OPERATION - THIRD ADDRESS FIEEQU H#2 ; UNCOND JUMP TO MEMORY MAP (Di) CJP: EQU H#3 ; COND JUMP PIPELINE PUSH: EQU H#4 ; PUSH STACK, LOAD REG MAYBE, CQU Q#1 ; A ADDRESSES FIRST 29705 ADDITION AIS7052:EQU Q#2 ; A ADDRESSES SECOND 29705 ADDITION ACONST: EQU Q#3 ; A ADDRESSES; ; CARRY BIT (2 BITS FOR NOW) [19] ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; CARRY: EQU B#01 NOCAR ; SOURCE IS Q REGISTER NONQREG:EQU B#0 ; SOURCE IS RAMB OR B.BUS ; EJECT ; * * * * * * * * * * * * * * * * * * * * * ; ; ; * * * * * * * * * * * * * * * * * ; ; Am29811 INSTRUCTION SET ; ; * * * * * * * * * * * * * * * * * ; ; NOTE: THE SALD ; ADDED C ADDRESS BITS (C5-C4) [17] ; * * * * * * * * * * * * * * * * * * * * * * * * ; ; CIN2903:EQU B#00 ; C ADDRESSONT JSRP: EQU H#5 ; JUMP SUB FROM REG (F) OR PIPE(T) CJV: EQU H#6 ; COND JUMP TO VECTOR INTER (Di) JRP: EQU H#7 ; JUMP  CONSTANT PROM ABUS: EQU Q#4 ; A FROM BUS ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; ADDED B ADDRESS RY: EQU B#00 ;IMAGINATIVE! IC: EQU B#10 ; Cin is Cout Z: EQU B#11 ; Z is Cin ; EJECT ; * * * * * * * * * * * * * * * * ME AS THE Am2910 EXCEPT TWB IS REPLACED BY JP ; AND ALL TESTS ARE ACTIVE HIGH RATHER THAN ACTIVE LOW ; JP: EQU H#F ; UNCOND: EQU H#3 ; 1->RN; R0->QN DDMCR: EQU H#4 ; Mc->RN; R0->QN DLN.RECOVER: EQU H#5 ; MN->RN; R0->QN DDZR: EQU H#6 ; 0->RN;; ; WAITREQ: EQU B#0 ; NOWAITRQ: EQU B#1 ; ; READY: EQU B#0 ; NOTREADY: EQU B#1 ; ; INITIALIZE: EQU B#0 ; NOTHER WAY ; ; ORDER: 543 210 ZCNOVR CEM CEu ; Q# Q# H# B# B# ; ONELEVEL: EQU 12Q#0000 ; Y -> MSR; MSR -> U60ns AT 25MHz CLC: EQU Q#5 ; 5 200ns AT 25MHz CLD: EQU Q#7 ; 6 200ns AT 30MHz CLE: EQU Q#3 ; 7 280ns AT 25MHz CLF: NG SE.DIS: EQU B#1 ; DISABLE SHIFTING EJECT ; ; ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ITIONAL JUMP PIPELINE ; ; ; EXAMPLE SEQUENCER SUB STATEMENT ; SEQR: SUB 4VH#E, 3VQ#0, 12V$X ; ; INSTR MUX ADDR ; R0->QN DDZRQMC: EQU H#7 ; 0->RN; R0->QN; Q0->Mc SDROTMC: EQU H#8 ; ROT.R; R0->Mc; ROT.Q SDROTC: EQU H#9 ; ROT.R WITH Mc;O.INIT: EQU B#1 ; ; EJECT ; * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; Am2904 SHIFT INSTRUCTIONS (I9-I8-I7-I6SR SET.MSR: EQU 12Q#0101 ; SET MACRO STATUS ONLY SET.USR: EQU 12Q#0176 ; SET MICRO STATUS ONLY SWAP.REG: EQU 12Q#0200 ; MSR <EQU Q#2 ; 8 320ns AT 25MHz CLG: EQU Q#6 ; 9 300ns AT 30MHz CLH: EQU Q#4 ; 10 CLOCK PERIODS 322ns AT 31MHz ; (max c* * * ; Am2904 STATUS REGISTER INSTRUCTION CODES ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *  CONT ? # ; ; ; EJECT ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; Am2925 CYCLE LENGTH SELECT [21]  ROT.Q SDROT: EQU H#A ; ROT.R; ROT.Q SDIC: EQU H#B ; Ic->RN; R0->QN DDROTC: EQU H#C ; Mc->RN; R0->QN; Q0->Mc DDROTMC:  AND SE) ; I10 IS TIED TO I8 OF Am2903/29203 ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; ; DOWN SHIFTIN--> USR ; LOAD.MSR: EQU 12Q#2001 ; ALU STATUS -> MSR ; THE ABOVE IS ONE OF SEVERAL CODES - YOU DON'T NEED THEM ALL! ; LOAD.rystal frequency is 311MHz) ; ; OTHER CONTROL LINES FOR THE Am2925 ; INCOMPLETELY DEFINED AT PRESENT (IN THIS FILE) ; FI; ; MACHINE STATUS REGISTER INSTRUCTION CODES ; I5-I4-I3-I2-I1-I0 AND EZ-EC-EN-EOVR-CEM ENABLES ; MICRO STATUS REGISTER IN ; System Clock Generator and Driver ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; THE FOLLOWING ARE THE CYCEQU H#D ; Q0->RN; R0->QN; Q0->Mc DDINIOVR: EQU H#E ; IN EXOR IOVR -> RN; R0->QN DDROT: EQU H#F ; DOUBLE PRECISION ROTATE DG ; SDZRZQ: EQU H#0 ; Z->RN; Z->QN SDOROQ: EQU H#1 ; 1->RN; 1->QN SLN.RECOVER: EQU H#2 ; 0->RN; R0->Mc; MN->QN DDORUSR: EQU 12Q#2076 ; ALU STATUS -> USR ; DITTO! ; LOAD.BOTH: EQU 12Q#2000 ; ALU -> MSR, USR ; AGAIN DITTO! ; LDINVRTM: EQURST.25: EQU B#1 ; LAST.25: EQU B#0 ; ; HALT: EQU B#00 ; NOHALT: EQU B#00 ; ; SINGLSTP: EQU B#00 ; RUN: EQU B#00 STRUCTION CODES ; I5-I4-I3-I2-I1-I0 AND CEu ENABLE ; ; THE FOLLOWING TAKES THESE ALL TOGETHER - YOU MAY WISH TO DO THIS ANLE LENGTH CODES (PRELIM) ; EXAMPLE CYCLE (1 OF 4) CLA: EQU Q#0 ; 3 CLOCK PERIODS 100ns AT 30MHz CLB: EQU Q#1 ; 4 1OWN ; ; UP SHIFTING (INCOMPLETE) ; SURZQZ: EQU H#2 ; R0<-0; Q0<-0 ; ; SHIFT ENABLES ; SE.EN: EQU B#0 ; ENABLE SHIFTI   12Q#3001 ; ALU -> MSR; Ic INVERTED LDINVRTU: EQU 12Q#3076 ; ALU -> USR; Ic INVERTED LOAD.INVERT: EQU 12Q#3000 ; ALU -> MSR, UR] [R] ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; Am29203/2903 TWO ADDRESS OPERATION -  be substituted ; in the various variable fields. The reference is via [i]. The DEF statements ; are also documented by provthe effort required in using AMDASM by ; reducing the effort required to create a customized .DEF file. ; EJECT ; ; ; ADDQ#5677 ; TEST.IOVR: EQU 12Q#6677 ; TEST.IC: EQU 12Q#7277 ; ; ; ; TEST ENABLE ; OECTEN: EQU B#0 OECTDIS: EQU B#1 ; ;  [9] [10] [11] [19] [R] [R] ; [12] ; AM2910: DEF 4VH#E, 3VX, 12V$X, 45X ; DEFAULTS CONT SR; Ic INVERTED ; EJECT ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; Am2904 CONDITION CODE OUTPUT INSTRUCTNO EXPANDED MEMORY ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; AM29203: DEF 19X, 3VQ#0, 4VH#Fiding a comment on the default value given. ; ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ITIONAL EXAMPLE DEF STATEMENTS ; ; AM2904: DEF 42X, 12VQ#2001, 1VB#1, 1VB#0, 4VX, 1VB#1, 3X ; DEFAULTS LO; OUTPUT ENABLE ; OEYEN: EQU B#0 OEYDIS: EQU B#1 ; ; INSTRUCTION ENABLE ; IEN: EQU B#0 IENDIS: EQU B#1 ; ; ; COND # # ; [20] ; ; ; note: This file is written such that the AM2910, AM29203, and AM2904 DEF ; statements are overlaION CODES ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; caution! I5-I4-I3-I2-I1-I0 ARE ALSO USED FOR TESTING!, 4VH#C, 2VB#00, 4VH#0, 4VH#0, 1VB#0, 1VB#0, 22X ; DEFAULTS RAMAB OR YBUS NOCin R0 R0 IEN OEY.EN ; Am2901-BASED CPU ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; AM2901: DEF 19X, 3VQ#1, 3VQ#0, AD.MSR OECTDIS OEYEN X SE.DIS ; SHIFT: DEF 56X, 4VX, 1B#0, 3X ; SHIFT SE.EN TEST: DEF ITIONAL CODE MULTIPLEXER (DATA MONITOR) ; NOACK: EQU Q#0 COUT: EQU Q#1 PASS: EQU Q#7 ; EJECT ; ; Certain of the EQyed in the .SRC file. The user would add additional DEF ; definitions for his/her additional fields in the microword. Or, the!!! ; ENABLE TESTING VIA OEct ENABLE ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; TESTMZ: EQU 12Q#4477 ; [9] [13] [11] [19] [R] [R] ; [14] ; AM2903: DEF 19X, 3VQ#0, 4VH#F, 4VH3VQ#1, 2VB#00, 4VH#0, 4VH#0, 26X ; DEFAULTS AB ADD.01 NOP.01 NOCin R0 R0 ; [1] [2] [3] [19] [ 42X, 12VQ#7777, 1VB#0, 9X ; DISABLED OECTEN STATUS: DEF 42X, 12VQ#2001, B#1, 1VB#0, 4X, B#1, 3X ; U groupings are labeled by [i]. The following DEF statements ; are documented by referring to the group of mnemonics which may user can ; delete all DEF statements and begin anew. The intent of this file and all ; other MASTER files is to help reduce  NO STATUS OPERATION TESTMOVR: EQU 12Q#4677 ; NO STATUS OPERATION TESTMC: EQU 12Q#5277 ; NO STATUS OPERATION TESTMN: EQU 12#C, 2VB#00, 4VH#0, 4VH#0, 1VB#0, 1VB#0, 22X ; DEFAULTS RAMAB OR YBUS NOCin R0 R0 IEN OEY.EN ;   LOAD.MSR NO CT OEYEN SE.DIS ; ; ********************************************************************* o be released by AMD in early 1982. The source file ; is DISKCTLR.SRC. ; ; The major difference between this DEF file and thF; ; by adding DEF and EQU statements, deleting some others, and by ; changing the basic microword format. The bulk of the ef; EJECT ; ; WORD 80 ; ; ************************************************* ; GENERAL MNEMONICS ; ***********************APPLICATIONS or AMD CUSTOMER EDUCATION CENTER ; PO BOX 453 MS#70 PO BOX 453 MS#71 ; SUNNYVALE, CA 94086 490-; ADDED STATEMENTS FOR DATA MONITOR PROBLEM - USES Am2903 sans .03 ** ; ( This is for the EDSYS29 class - other users should dee CONTROLR.DEF file is ; the approach to the microprogramming. This file makes heavy use of ; DEF statement overlays while thfort required ; to create such a file was considerably reduced by beginning from the ; "master" file (CONTROLR.DEF) rather tha************************** ; ; BYTE - WORD MODE SELECT [M] <---------- referenced by DEF statements ; B: EQU 1B#0 ; BYTE MA LAKESIDE DRIVE ; SUNNYVALE, CA 94086 ; ; Advanced Micro Devices reserves the right to make changes in its product ;lete ) ; ********************************************************************* ; NOP2903: DEF 19X, Q#0, H#F, H#C, B#00, H#e other uses the comma-positional ; notation. The choice is a matter of preference. THE Am29116 MNEMONICS ; AND INSTRUCTION Ln typing a new file from scratch. ; ; This particular .DEF file was created for a specific Am29116-Am9520 ; disk controller, ODE W: EQU 1B#1 ; WORD MODE ; ; ; ************************************************* ; N SELECT [N] ; N0: EQU H#0 ; 0  without notice in order to improve design or performance characteristics. ; The company assumes no responsibility for the use 0, H#0, B#0, B#1, 22X ; CTRL: DEF 61X, 1VB#0, 1VB#0, 1VB#0 ; DATAin DATAout MEMORY MAP SELECT ; AYOUT ARE IDENTICAL IN THESE FILES. ; ; ; This file may also be used as a master file which the user can edit to ; suit his/described in the AMD application note: ; "A High-Performance Intelligent Disk Controller," by Otis Tabler and ; Brad Kitson, t N1: EQU H#1 ; N2: EQU H#2 ; N3: EQU H#3 ; N4: EQU H#4 ; N5: EQU H#5 ; N6: EQU H#6 ; N7: EQU H#7 ; N8: EQUTITLE AM29116 / AM9520 DISK CONTROLLER 9/81 Tabler-Kitson ; ; This .DEF file (DISKCTLR.DEF) was created by editing CONTROLR.DEof any circuits or ; programs described herein. ; ; ; Am29116 Mnemonics Copyright c 1982 Advanced Micro Devices, Inc. ;  CTRL CTRL FIRST QUADRANT END her application. ; ; Anyone finding an error in this file is requested to send a marked listing ; or portion thereof to: AMD   H#8 ; N9: EQU H#9 ; NA: EQU H#A ; NB: EQU H#B ; NC: EQU H#C ; ND: EQU H#D ; NE: EQU H#E ; NF: EQU H#F ; AD,OPCODE,SOURCE-DEST,REGISTER ; [M] [1] [2] [R] <---- refer to proper EQU groups ; **********************E-DESTINATION SELECT [2] ; SORA: EQU H#0 ; RAM ACC SORY: EQU H#2 ; RAM Y BUS SORS: EQU H#3 ; RAM STATUS SOAR: EQU H EQU H#8 ; R S NOR: EQU H#9 ; R + S OR: EQU H#A ; R + S EXNOR: EQU H#B ; R S ; ; ; SOURCE-DESTINATION [6] ; R 21 ; R22: EQU 5D#22 ; R23: EQU 5D#23 ; R24: EQU 5D#24 ; R25: EQU 5D#25 ; R26: EQU 5D#26 ; R27: EQU 5D#27 ; R2INATION ; [M] [1] [3] [4] ; *************************************************************** EJECT ; ; ; ; **EJECT ; ; *************************************************** ; 32 RAM REGISTERS [R] ; R0: EQU 5D#0 ; 00000 R1: EQU 5D************************************** EJECT ; ; SOURCE (R/S) [3] ; SOA: EQU H#4 ; ACC SOD: EQU H#6 ; D SOI: EQU H##4 ; ACC RAM SODR: EQU H#6 ; D RAM SOIR: EQU H#7 ; I RAM SOZR: EQU H#8 ; 0 RAM SOZER: EQU H#9 ; D(0E) RAM SOSER: ES DEST ; TORAA: EQU H#0 ; RAM ACC ACC TORIA: EQU H#2 ; RAM I ACC TODRA: EQU H#3 ; D RAM ACC TORAY: EQU H#8 ; RAM AC8: EQU 5D#28 ; R29: EQU 5D#29 ; R30: EQU 5D#30 ; R31: EQU 5D#31 ; ; EJECT ; ; ; ************************************************ ; TWO OPERAND INSTRUCTIONS ; *********************************** ; ; OPCODES [5] ; SUBR:#1 ; R2: EQU 5D#2 ; R3: EQU 5D#3 ; R4: EQU 5D#4 ; R5: EQU 5D#5 ; R6: EQU 5D#6 ; R7: EQU 5D#7 ; R8: EQU 5D#87 ; I SOZ: EQU H#8 ; 0 SOZE: EQU H#9 ; D(0E) SOSE: EQU H#A ; D(SE) ; ; DESTINATION [4] ; NRY: EQU D#0 ; Y BUS NRQU H#A ; D(SE) RAM SORR: EQU H#B ; RAM RAM ; ; ************************************************************ SOR: DEF 1V, C Y BUS TORIY: EQU H#A ; RAM I Y BUS TODRY: EQU H#B ; D RAM Y BUS TORAR: EQU H#C ; RAM ACC RAM TORIR: EQU H#E ; RAM ************** ; SINGLE OPERAND INSTRUCTIONS ; ***************************** ; ; OPCODES [1] ; MOVE: EQU H#C ; 1100 MOVE EQU H#0 ; S minus R SUBRC: EQU H#1 ; S minus R with carry SUBS: EQU H#2 ; R minus S SUBSC: EQU H#3 ; R minus S with  ; R9: EQU 5D#9 ; R10: EQU 5D#10 ; R11: EQU 5D#11 ; R12: EQU 5D#12 ; R13: EQU 5D#13 ; R14: EQU 5D#14 ; R15: A: EQU D#1 ; ACC NRS: EQU D#4 ; STATUS NRAS: EQU D#5 ; ACC,STATUS ; ; ************************************************ B#10,4V%D#, 4V%D#, 5V%D#,64X ; SINGLE OPERAND RAM ; \ \ \ \ ; MODE,QUI RAM TODRR: EQU H#F ; D RAM RAM ; ; ************************************************************ TOR1: DEF 1V, B#00,4V%D COMP: EQU H#D ; 1101 COMP INC: EQU H#E ; 1110 INC INCREMENT NEG: EQU H#F ; 1111 NEG INCREMENT COMP ; ; SOURCcarry ADD: EQU H#4 ; R plus S ADDC: EQU H#5 ; R plus S with carry AND: EQU H#6 ; R . S NAND: EQU H#7 ; R . S EXOR: EQU 5D#15 ; R16: EQU 5D#16 ; R17: EQU 5D#17 ; R18: EQU 5D#18 ; R19: EQU 5D#19 ; R20: EQU 5D#20 ; R21: EQU 5D#*************** SONR: DEF 1V, B#11,4V%D#, 4V%D#, 5V%D#,64X ; SINGLE OPERAND NON-RAM ; ; MODE,QUAD,OPCODE,SOURCE,DEST  #, 4V%D#, 5V%D#,64X ; TWO OPERAND RAM (1) ; ; MODE,QUAD,SOURCE-DEST,OPCODE,REGISTER ; [M] [6] [5V%D#,64X ; SHIFT RAM ; ; MODE,QUAD,SOURCE,DIRECT-INPT,REGISTER ; [M] [10] [9] [R] ; *******************NSTRUCTIONS ; ************************************************** ; ; DIRECTION AND INPUT [9] ; SHUPZ: EQU H#0 ; UP 0 SHU********************************** ROTR2: DEF 1V, B#01,4V%D#,4V%D#, 5V%D#,64X ; ROTATE RAM (2) ; ; MODE,QUAD,N,SOU*************************** ; ; SOURCE [8] R S ; TODA: EQU H#1 ; D ACC TOAI: EQU H#************** ; ; SOURCE-DESTINATION [12] ; RTRA: EQU H#C ; RAM ACC RTRY: EQU H#E ; RAM Y BUS RTRR: EQU H#F ; RAM5] [R] ; ************************************************************ EJECT ; ; ; SOURCE-DESTINATION [7] ********************************** ; ; ; SOURCE [11] ; SHA: EQU H#6 ; ACC SHD: EQU H#7 ; D ; ; ; ******************P1: EQU H#1 ; UP 1 SHUPL: EQU H#2 ; UP QLINK SHDNZ: EQU H#4 ; DOWN 0 SHDN1: EQU H#5 ; DOWN 1 SHDNL: EQU H#6 ; DOWNRCE-DEST,REGISTER ; [M] [N] [13] [R] ; ***************************************************** ; ; SOURCE DESTIN2 ; ACC I TODI: EQU H#5 ; D I ; ; *********************************************************** TONR: DEF 1V, B#11,4V%D#,  RAM ; ; ; ***************************************************** ROTR1: DEF 1V, B#00,4V%D#,4V%D#, 5V%D#,64X ; ROTA R S DEST ; TODAR: EQU H#1 ; D ACC RAM TOAIR: EQU H#2 ; ACC I RAM TODIR: EQU H#5 ; D I RAM ; ; *************************************** SHFTNR: DEF 1V, B#11,4V%D#, 4V%D#, 5V%D#,64X ; SHIFT NON-RAM ; ; MODE,QUAD,SOURC QLINK SHDNC: EQU H#7 ; DOWN QC SHDNOV: EQU H#8 ; DOWN QN QOVR ; ; ; SOURCE [10] ; SHRR: EQU H#6 ; RAM RAM SHDR: ATION [14] ; RTDY: EQU D#24 ; D Y BUS RTDA: EQU D#25 ; D ACC RTAY: EQU D#28 ; ACC Y BUS RTAA: EQU D#29 ; ACC ACC ; 4V%D#, 5V%D#,64X ; TWO OPERAND NON-RAM ; ; MODE, QUAD,SOURCE,OPCODE,DESTINATION ; [M] [8] [5] [4] ; ***TE RAM (1) ; ; MODE,QUAD,N,SOURCE-DEST,REGISTER ; [M] [N] [12] [R] ; ************************************************************************************************ TOR2: DEF 1V, B#10,4V%D#, 4V%D#, 5V%D#,64X ; TWO OPERAND E,DIRECT-INP,DESTINATION ; [M] [11] [9] [4](NRY; NRA ONLY) ; *************************************************** EQU H#7 ; D RAM ; ; ; ***************************************************** SHFTR: DEF 1V, B#10,4V%D#, 4V%D#,  ; ; ***************************************************** ROTNR: DEF 1V, B#11,4V%D#,H#C, 5V%D#,64X ; ROTATE NON-RAM ******************************************************** EJECT ; ************************************************** ; SHIFT I************* ; ; SOURCE-DESTINATION [13] ; RTAR: EQU H#0 ; ACC RAM RTDR: EQU H#1 ; D RAM ; ; ; *******************RAM (2) ; ; MODE,QUAD,SOURCE-DEST,OPCODE,REGISTER ; [M] [7] [5] [R] ; *********************************** EJECT ; ; ************************************************** ;ROTATE INSTRUCTIONS ; ************************************   ; ; MODE,QUAD,N,FIXED CODE,DESTINATION ; [M] [N] [14] ; *************************************************************** BONR: DEF 1V, B#11,4V%D#,B#1100, 5V%D#,64X ; BIT ORIENTED NON-RAM ; ; MODE,QUAD,N,FIXED CODE,OPCODE ;BIT N RSTNA: EQU D#1 ; RESET ACC, BIT N SETNA: EQU D#2 ; SET ACC, BIT N A2NA: EQU D#4 ; ACC + 2^N -- ACC S2NA: EQU D CRAI: EQU H#5 ; RAM ACC I ; ; ; ******************************************** ROTC: DEF 1V, B#01,4V%D#,4V%D#, ******************************* ; ; ; OPCODES [16] ; LD2NR: EQU H#C ; 2^N --- RAM LDC2NR: EQU H#D ; 2^N --- RAM A2NR:************************************ ROTM: DEF 1V, B#01,4V%D#,4V%D#, 5V%D#,64X ;ROTATE AND MERGE ; ; MODE,QUAD,N,SO****** EJECT ; *************************************************** ; BIT ORIENTED INSTRUCTIONS ; *************************** [M] [N] [17] ; ********************************************************* EJECT ; **************************#5 ; ACC - 2^N --ACC LD2NA: EQU H#6 ; 2^N -- ACC LDC2NA: EQU D#7 ; 2^N -- ACC TSTND: EQU D#16 ; TEST D, BIT N RSTND:  5V%D#,64X ; ROTATE AND COMPARE ; ; MODE,QUAD,N,SOURCE-DEST-MASK,REGISTER ; [M] [N] [19] [R] ; ******** EQU H#E ; RAM + 2^N - RAM S2NR: EQU H#F ; RAM - 2^N - RAM ; ; ; *******************************************************URCE-DEST,REGISTER ; [M] [N] [18] [R] ; ********************************************************** ; ; ****************************** ; ; OPCODES [15] ; SETNR: EQU H#D ; SET RAM, BIT N RSTNR: EQU H#E ; RESET RAM, BIT N TSTNR: ************************ ; ROTATE AND MERGE ; ************************************************** ; ; SOURCE-DEST SELECT [U,SEQU D#17 ; RESET D, BIT N SETND: EQU D#18 ; SET D, BIT N A2NDY: EQU D#20 ; D + 2^N -- Y BUS S2NDY: EQU D#21 ; D - 2^N ************************************* EJECT ; ************************************************** ; PRIORITIZE ; ************* BOR2: DEF 1V, B#10,4V%D#,4V%D#, 5V%D#,64X ; BIT ORIENTED RAM (2) ; ; MODE,QUAD,N,OPCODE,REGISTER ; [M] [N] [16******************************************** ; ROTATE AND COMPARE ; ************************************************** ; ; REQU H#F ; TEST RAM, BIT N ; ; ; ******************************************************** BOR1: DEF 1V, B#11,4V%D#,4V%D#, ,MASK-DEST] [18] ; ; ROT NON-ROT MASK-DEST MDAI: EQU H#7 ; D ACC I MDAR: EQU H#8 ; D ACC RAM MDRI: EQU H#9 -- Y BUS LD2NY: EQU D#22 ; 2^N -- Y BUS LDC2NY: EQU D#23 ; 2^N -- Y BUS ; ; ; ******************************************************************************* ; ; SOURCE [20] ; PRT1A: EQU H#7 ; ACC PR1D: EQU H#9 ; D ; ; ; DESTINATION [2] [R] ; ******************************************************** EJECT ; ; OPCODES [17] ; TSTNA: EQU D#0 ; TEST ACC, OT.SRC(U)-NON ROT.SRC(S)/DEST-MASK(S)[19] ; CDAI: EQU H#2 ; D ACC I CDRI: EQU H#3 ; D RAM I CDRA: EQU H#4 ; D RAM ACC  5V%D#,64X ; BIT ORIENTED RAM (1) ; ; MODE,QUAD,N,OPCODE,REGISTER ; [M] [N] [15] [R] ; *************************; D RAM I MDRA: EQU H#A ; D RAM ACC MARI: EQU H#C ; ACC RAM I MRAI: EQU H#E ; RAM ACC I ; ; ; ********************** 1] ; PR1A: EQU H#8 ; ACC PR1Y: EQU H#A ; Y BUS PR1R: EQU H#B ; RAM ; ; ************************************************************************************** ; ; ******************************************* CRCR: DEF B#11001101001,5V%D#,64X D ; ; ; ********************************************** PRTNR: DEF 1V, B#11,4V%D#, 4V%D#, 5V%D#,64X ; PRIORITIZE NON-R ; RESET STATUS ; ; OPCODE ; [27] ; **************************************************** ; ; *****************SK,DEST,REG-SOURCE ; [M] [22] [23] [R] ; *********************************************** EJECT ; SOURCE (R) [24] ET FLAG 2 SF3: EQU 5D#10 ; SET FLAG 3 ; ; ; ************************************************** SETST: DEF B#011,H#BA,5V%D** PRT1: DEF 1V, B#10,4V%D#, 4V%D#, 5V%D#,64X ; RAM ADDR MASK(S) ; ; MODE,QUAD,DESTINATION,SOURCE,REG-MASK ; [; REVERSE ; ******************************************* ; ; ******************************************** ; ; NOOP ; ; ***AM ; ; MODE,QUAD,MASK,SOURCE,DESTINATION ; [M] [22] [25] [4](NRY,NRA ONLY) ; **************************************************************** SVSTR: DEF 1V, B#10,H#7A, 5V%D#,64X ; SAVE STATUS-RAM ; ; MODE,QUAD,FIXED,RAM ADDRE; PR3R: EQU H#3 ; RAM PR3A: EQU H#4 ; ACC PR3D: EQU H#6 ; D ; ; ; *********************************************** P#,64X ; SET STATUS ; ; OPCODE ; [26] ; ************************************************** EJECT ; ; OPCODE [2M] [21] [20] [R] ; *********************************************** ; ; ; DESTINATION [23] ; PR2A: EQU H#0 ;***************************************** NOOP: DEF H#7140,64X ; NO OPERATION ; ******************************************** ***************** EJECT ; ; ********************************************** ; CYCLIC REDUNDANCY CHECK ; ********************SS/DEST ; [M] [R] ; **************************************************** ; ; ;**************************************RT3: DEF 1V, B#10,4V%D#, 4V%D#, 5V%D#,64X ; PRIORITIZE RAM ; ; MODE,QUAD,MASK,SOURCE,REG-DEST ; [M] [22] [24] 7] ; RONCZ: EQU D#3 ; RESET OVR,N,C,Z RL: EQU D#5 ; RESET LINK RF1: EQU D#6 ; RESET FLAG 1 RF2: EQU D#9 ; RESET FLA ACC PR2Y: EQU H#2 ; Y BUS ; ; MASK (S) [22] ; PRA: EQU H#8 ; ACC PRZ: EQU H#A ; 0 PRI: EQU H#B ; I ; ; ; ****EJECT ; ; ************************************************ ; STATUS ; ************************************************ ; ;************************** ; ; ******************************************* CRCF: DEF B#11001100011,5V%D#,64X ; FORWARD ; ***************** SVSTNR: DEF 1V, B#11,H#7A, 5V%D#,64X ; SAVE STATUS NON-RAM ; ; MODE,QUAD,FIXED,DESTINATION ; [M] [R] ; *********************************************** ; ; ; SOURCE (R) [25] ; PRTA: EQU H#4 ; ACC PRTD: EQU H#6 ; G 2 RF3: EQU D#10 ; RESET FLAG 3 ; ;***************************************************** RSTST: DEF B#011,H#AA,5V%D#,64X ******************************************* PRT2: DEF 1V, B#10,4V%D#, 4V%D#, 5V%D#,64X ; PRIORITIZE RAM ; ; MODE,QUAD,MA OPCODE [26] ; SONZC: EQU 5D#3 ; SET OVR,N,C,Z SL: EQU 5D#5 ; SET LINK SF1: EQU 5D#6 ; SET FLAG 1 SF2: EQU 5D#9 ; S  [4](NRY,NRA ONLY) ; **************************************************** EJECT ; ; *************************************, H#0, 10V$D#1023, 42X CJS: DEF 24X, H#1, 10V$D#1023, 42X JS: DEF 24X, H#1, 10V$D#1023, 6Q#36, 36X ; UNCONDITIONAL JUMP TO SU ; SRE: DEF 20X, B#1, 59X NOSRE: DEF 20X, B#0, 59X ; ; OUTPUT ENABLE Y ; OEY: DEF 21X, B#0, 58X NOOEY: DEF 21X, B#1, 58X OR FLAG CT16: EQU 5Q#11: ; AM29116 CONDITIONAL TEST FLAG EP20: EQU 5Q#12: ; AM9520 ERROR PATTERN FLAG ER20: EQU 5Q#13: ; ATEST: DEF B#011,H#9A,5V%D#,64X ; TEST STATUS ; ; FIXED, OPCODE ; [CT] ; ************************************** 24X, H#C, 10V$D#1023, 42X LOOP: DEF 24X, H#D, 10V$D#1023, 42X CONT: DEF 24X, H#E, 10V$D#1023, 42X TWB: DEF 24X, H#F, 10V$D#1************ ; TEST STATUS ; ************************************************* ; ; OPCODE (CT) ; TNOZ: EQU D#0 ; TEST (NBR. JMAP: DEF 24X, H#2, 10V$D#1023, 42X CJP: DEF 24X, H#3, 10V$D#1023, 42X JP: DEF 24X, H#3, 10V$D#1023, 6Q#36, 36X ; UNCOND ; ; INSTRUCTION ENABLE ; IEN: DEF 22X, B#0, 57X NOIEN: DEF 22X, B#1, 57X ; ; D-I-LATCH ENABLE ; DLE: DEF 23X, B#1, 56X M9520 ERROR DETECTED FLAG FAIL: EQU 5Q#14: ; UNCONDITIONAL FAILURE OF "TEST" RDYI: EQU 5Q#15: ; NOT READY INPUT (DATA UNAVAI*************** EJECT ; ; added DEF and EQU statements ;******************************** ; ; IMMEDIATE OPERAND ; IMME: D023, 42X ; ^ ; | ; | ; NOTE: For proper assembly, a "$" must be used in any  OVR) + Z TNO: EQU D#2 ; TEST N OVR TZ: EQU D#4 ; TEST Z TOVR: EQU D#6 ; TEST OVR TLOW: EQU D#8 ; TEST LOW TC: EQUITIONAL JUMP PUSH: DEF 24X, H#4, 10V$D#1023, 42X JSRP: DEF 24X, H#5, 10V$D#1023, 42X CJV: DEF 24X, H#6, 10V$D#1023, 42X JRP: NODLE: DEF 23X, B#0, 56X EJECT ; ; ; ;-------------------------------------------------- ; Am2910 COMMANDS AND BRANCHLABLE FROM FIFOS) RDYO: EQU 5Q#16: ; NOT READY OUTPUT (FIFOS FULL) SUCC: EQU 5Q#17: ; UNCONDITIONAL SUCCESS OF "TEST" ATTN:EF 16V%D#, 64X ; ; CT MULTIPLEXER CONTROL ; CT: DEF 16X, 4V%D#, 60X NOZ: EQU H#0 NO: EQU H#1 Z: EQU H#2 OVR: EQU H#3 LOfield which ; will be used to accept a symbolic address in the SRC file. ; ; ; EJECT ; ; ; ; ; Am2910 CONDITION CO D#10 ; TEST C TZC: EQU D#12 ; TEST Z + C TN: EQU D#14 ; TEST N TL: EQU D#16 ; TEST LINK TF1: EQU D#18 ; TEST FLAG  DEF 24X, H#7, 10V$D#1023, 42X RFCT: DEF 24X, H#8, 10V$D#1023, 42X RPCT: DEF 24X, H#9, 10V$D#1023, 42X CRTN: DEF 24X, H#A, 10 ADDRESSES ; note use of DEF statements - overlay in SRC file ;-------------------------------------------------- JZ: DEF 24X EQU 5Q#20: ; ATTENTION BACK: EQU 5Q#21: ; BUS ACKNOWLEDGE BUSY: EQU 5Q#22: ; BUSY INDX: EQU 5Q#23: ; INDEX SAMD: EQU 5QW: EQU H#4 C: EQU H#5 ZC: EQU H#6 N: EQU H#7 L: EQU H#8 F1: EQU H#9 F2: EQU H#A F3: EQU H#B ; ; STATUS REGISTER ENABLE DE SELECTIONS ; IF: DEF 38X, 5V%D#, B#0, 36X IFNOT: DEF 38X, 5V%D#, B#1, 36X ; ; AE20: EQU 5Q#10: ; AM9520 ALIGNMENT ERR1 TF2: EQU D#20 ; TEST FLAG 2 TF3: EQU D#22 ; TEST FLAG 3 ; ; ; ***************************************************** V$D#1023, 42X RTN: DEF 24X, H#A, 10V$D#1023, 6Q#36, 36X ; UNCONDITIONAL RETURN CJPP: DEF 24X, H#B, 10V$D#1023, 42X LDCT: DEF #24: ; SECTOR / ADDRESS MARK DETECTED PM2: EQU 5Q#25: ; AM9520 PATTERN MATCH 2 FLAG PM3: EQU 5Q#26: ; AM9520 PATTERN MATCH FROM 9520 PM BITS PF03: DEF 70X, B#0, 9X ; PARALLEL FETCH FROM 9403AS PL03: DEF 71X, B#0, 8X ; PARALLEL LOAD INTO 9403AS PREQLOCK PULSE (ACTUAL WAVEFORM) FOR AM9520 CREQ: DEF 60X, B#0, 19X ; COMMAND REQUEST INPT: DEF 61X, B#0, 18X ; INPUT SERIAL DATA plication. Documentation on the Am29116 ; instruction set can be found in the data sheet and in "The Am29116", ; a CUSTOMER  B#0, 28X ; (DISK) BUS DIRECTION OUT (FROM CONTROLLER) BT03: DEF 52X, B#0, 27X ; MEMORY BUS TO 9403AS BT16: DEF 53X, B#0, 26X  3 FLAG PM4: EQU 5Q#27: ; AM9520 PATTERN MATCH 4 FLAG EJECT ; ; MISCELLANEOUS CONTROL SIGNALS ; ADMC: DEF 44X, B#0, 35X : DEF 72X, B#0, 7X ; PARAMETER REQUEST RDGA: DEF 73X, B#0, 6X ; READ GATE RFIF: DEF 74X, B#0, 5X ; RESET FIFO SAST: DEF 75X, TO 9403AS JMPI: DEF 62X, B#01, 16X ; JUMP INDIRECT AM29116 REGISTER NOJMPI: DEF 62X, B#10, 16X ; NO INDIRECT JUMP MADR: DEF 6EDUCATION CENTER publication, revised to include this file ; and its companion, CONTROLR.SRC, a test file. ; ; ; The file DI; MEMORY BUS TO AM29116 BT2L: DEF 54X, B#0, 25X ; MEMORY BUS TO AM9520 - LOWER BYTE BT2U: DEF 55X, B#0, 24X ; MEMORY BUS TO AM; ADDRESS MARK CONTROL BFCB: DEF 45X, B#0, 34X ; MEMORY BUS FROM DRIVE CONTROL BUS BFTP: DEF 46X, B#0, 33X ; MEMORY BUS FROM TB#0, 4X ; SELECT / ATTENTION STROBE WRGA: DEF 76X, B#0, 3X ; WRITE GATE ; ASCEBC: EQU Q#0 ; ASCII TO EBCDIC SUBSET PREFIX B4X, B#0, 15X ; MEMORY ACCESS MREA: DEF 65X, B#0, 14X ; MEMORY ADDRESS MWRT: DEF 66X, B#0, 13X ; MEMORY WRITE OUPT: DEF 67X, BSKCTLR.DEF was created by editing this file; DISKCTLR.SRC ; provides an example of disk controller microroutines. ; ; This fi9520 - UPPER BYTE BT20: DEF 56X, B#0, 23X ; MEMORY BUS TO AM9520 - CONTROL INFORMATION CE2L: DEF 57X, B#0, 22X ; CLOCK ENABLE ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; TITLE * * * * AM29116.DEF FILE - D. E. WHITE - JANUARY 12, 19RANSLATE PROM BF03: DEF 47X, B#0, 32X ; MEMORY BUS FROM 9403AS BF16: DEF 48X, B#0, 31X ; MEMORY BUS FROM AM29116 BF2L: DEF 49CDEBC: EQU Q#1 ; BCD TO EBCDIC SUBSET PREFIX EBCASC: EQU Q#2 ; EBCDIC SUBSET TO ASCII PREFIX EBCBCD: EQU Q#3 ; EBCDIC SUBSE#0, 12X ; OUTPUT SERIAL DATA FROM 9403AS PENB: DEF 68X, B#0, 11X ; PARAMETER ENABLE PFPM: DEF 69X, B#0, 10X ; SET 9520 P BITS le was created for use in AMD CUSTOMER EDUCATION CENTER seminars. ; ; Advanced Micro Devices reserves the right to make changeAM9520 TO LOWER-BYTE BUS INT. CE20: DEF 58X, B#0, 21X ; CLOCK ENABLE MEMORY BUS TO AM9520 TRANSFER CP20: DEF 59X, B#0, 20X ; C82 * * * ; ; ; ; ; This file was created as a master file from which the user can create ; a .DEF file for a particular apX, B#0, 30X ; MEMORY BUS FROM AM9520 - LOWER BYTE BF2U: DEF 50X, B#0, 29X ; MEMORY BUS FROM AM9520 - UPPER BYTE BOUT: DEF 51X,T TO BCD PREFIX ; XLAT: DEF 77X, 3V%D# ; TRANSLATE PREFIX ; ; END  s in its product ; without notice in order to improve design or performance characteristics. ; The company assumes no responsi***************************** ; N SELECT [N] constant for Am29116 ; ************************************************* ; N0: ; ROTATE & MERGE [18] ; ROTATE & COMPR [19] ; PRIORITIZE [20], [21], [22], [23], [24], [25] ; CYCLIC REDUNDANCY CHECR31: EQU 5D#31 ; EJECT ; ************************* ; Am2910 INSTRUCTION SET ; Microprogram Controller ; ************ts included are: Am2910 (SUB STATEMENT) ; Am29116 - ALL VALID COMBINATIONS ; Am2914 ; Am2940 ; Am2942 ;  R5: EQU 5D#5 ; R6: EQU 5D#6 ; R7: EQU 5D#7 ; R8: EQU 5D#8 ; R9: EQU 5D#9 ; R10: EQU 5D#10 ; R11: EQU 5D#11bility for the use of any circuits or ; programs described herein. ; ; Am29116 Mnemonics Copyright c 1982 Advanced Mi EQU H#0 ; 0 N1: EQU H#1 ; N2: EQU H#2 ; N3: EQU H#3 ; N4: EQU H#4 ; N5: EQU H#5 ; N6: EQU H#6 ; N7: EQU KS ; NOOP ; STATUS [26], [27] ; TEST STATUS [CT] ; EJECT ; ************************************************* ************ ; JZ: EQU H#0 ; JUMP ZERO - RESET CJS: EQU H#1 ; COND JUMP SUBROUTINE - PIPELINE JMAP: EQU H#2 ; JUMP MAP (DEC Am2904 - PARTIAL ONLY! (2**22 POSSIBLE VARIATIONS) ; Am2925 - CYCLE SELECT, OTHER CONTROLS DRAFTED ONLY ; Am2950 ;  ; R12: EQU 5D#12 ; R13: EQU 5D#13 ; R14: EQU 5D#14 ; R15: EQU 5D#15 ; R16: EQU 5D#16 ; R17: EQU 5D#17 ; R18:cro Devices, Inc. EJECT ; ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; WORD 64 ; ASSUMED LAYOUTH#7 ; N8: EQU H#8 ; N9: EQU H#9 ; NA: EQU H#A ; NB: EQU H#B ; NC: EQU H#C ; ND: EQU H#D ; NE: EQU H#E ; NF ; GENERAL MNEMONICS ; ************************************************* ; ; **************************** ; BYTE - WORD MODODE) CJP: EQU H#3 ; COND JUMP PIPELINE PUSH: EQU H#4 ; PUSH, COND LOAD CNTR & CONTINUE JSRP: EQU H#5 ; COND JUMP SUBROUTINE -; INDEX TO Am29116 INSTRUCTIONS - [i] REFERS TO ALLOWED MNEMONICS GROUP ; ; SINGLE OPERAND [1], [2], [3], [4] ; TWO OPERAN EQU 5D#18 ; R19: EQU 5D#19 ; R20: EQU 5D#20 ; R21: EQU 5D#21 ; R22: EQU 5D#22 ; R23: EQU 5D#23 ; R24: EQU 5 - CHANGE AS NEEDED ; ; This file contains the EQUs and DEFs for a "typical" Am29116 controller ; ; CREATED APRIL 21, 1981 : EQU H#F ; EJECT ; ; *************************************************** ; 32 RAM REGISTERS [R] ; **********************E SELECT [M] ; **************************** ; B: EQU 1B#0 ; BYTE MODE W: EQU 1B#1 ; WORD MODE ; ; ******************** REGISTER OR PIPELINE CJV: EQU H#6 ; COND JUMP VECTOR MAP JRP: EQU H#7 ; COND JUMP REGISTER OR PIPELINE RFCT: EQU H#8 ; REPED [5], [6], [7], [8] ; SHIFT [9], [10], [11] ; ROTATE [12], [13], [14] ; BIT-ORIENTED [15], [16], [17] D#24 ; R25: EQU 5D#25 ; R26: EQU 5D#26 ; R27: EQU 5D#27 ; R28: EQU 5D#28 ; R29: EQU 5D#29 ; R30: EQU 5D#30 ; ; UPDATED JAN 12, 1982 DEW ; ; INDEX: ; BYTE-WORD MODE SELECT [M] ; NUMBER [N] ; RAM REGISTERS [R] ; Par***************************** ; R0: EQU 5D#0 ; 00000 R1: EQU 5D#1 ; R2: EQU 5D#2 ; R3: EQU 5D#3 ; R4: EQU 5D#4 ; AT LOOP, ADDR ON STACK, COUNT DOWN COUNTER RPCT: EQU H#9 ; REPEAT LOOP, ADDR IN PIPELINE, COUNT DOWN COUNTER CRTN: EQU H#A ; CNEEDED TO COMPLETE THE MICROWORD ; THE "SLEEPER" APPEARS IN ALL Am29116 INSTRUCTION DEF STATEMENTS ; EJE#0 ; SRE.EN: EQU B#0 ; STATUS REGISTER ENABLE SRE.DIS: EQU B#1 ; IEN: EQU B#0 ; INSTRUCTION ENABLE IDIS: EQU B#1 ; D(SE) ; ; DESTINATION [4] ; NRY: EQU D#0 ; Y BUS NRA: EQU D#1 ; ACC NRS: EQU D#4 ; STATUS NRAS: EQU D#5 ; ACC,ST*************************************** ; ; THE AM2910 FIELDS ARE GROUPED AS A SUB STATEMENT WHICH APPEARS IN ALL Am29116 ; D D(0E) RAM SOSER: EQU H#A ; D(SE) RAM SORR: EQU H#B ; RAM RAM ; ; ******************************************************OND RETURN FROM SUBROUTINE CJPP: EQU H#B ; COND JUMP PIPELINE AND POP STACK LDCT: EQU H#C ; LOAD COUNTER AND CONTINUE LOOP: ECT ; ***************************** ; SINGLE OPERAND INSTRUCTIONS ; ***************************** ; ; OPCODES [1] ; MOVE:  ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ZZZZZ: SUB 1VB#0, 1VB#1, 1VB#0, 1VB#0, 1VB#0, 24X ; ATUS ; ; *************************************************************** SONR: DEF AM2910,1V, B#11,4V, 4V, 5V%, ZZZZZ EF STATEMENTS. THE ACTUAL FIELDS REQUIRED CAN BE ALTERED AS NEEDED ; ; EJECT ; * * * * * * * * * * * * * * * * * ; Am2911****** SOR: DEF AM2910,1V, B#10,4V, 4V, 5V%, ZZZZZ;SINGLE OPERAND RAM ; ; MODE,QUAD,OPCODE,SOURCE-DEST,REGISTER QU H#D ; REPEAT LOOP UNTIL TEST TRUE; ADDR ON STACK CONT: EQU H#E ; CONTINUE TWB: EQU H#F ; DEAD-MAN TIMER, REPEAT LOOP, ADD EQU H#C ; 1100 MOVE COMP: EQU H#D ; 1101 COMP INC: EQU H#E ; 1110 INC INCREMENT NEG: EQU H#F ; 1111 NEG INCRE; OEYEN DLE.EN OETDIS SRE.EN IEN MISC ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; SINGLE OPERAND NON-RAM ; ; MODE,QUAD,OPCODE,SOURCE,DESTINATION ; [M] [1] [3] [4] ; *************************6 CONTROL LINES ; 16-Bit Bipolar Microprocessor ; * * * * * * * * * * * * * * * * * ; OEYEN: EQU B#0 ; Y BUS ENABLE OEY ; [M] [1] [2] [R] ; ************************************************************ ; ; SOURCE (R/S) [3] R ON STACK, FAIL ; ADDR IN PIPELINE, COUNT-DOWN COUNTER (3-WAY) ; ; *****************************************************MENT COMP ; ; SOURCE-DESTINATION SELECT [2] ; SORA: EQU H#0 ; RAM ACC SORY: EQU H#2 ; RAM Y BUS SORS: EQU H#3 ; RAM  ; ; THE "SLEEPER" CONTAINS THE Am29116 CONTROL LINES AND 24 DON'T CARE POSITIONS ; WHICH THE USER CAN DEFINE TO BE WHATEVER ************************************** EJECT ; *********************************** ; TWO OPERAND INSTRUCTIONS ; ************DIS: EQU B#1 ; DLE.EN: EQU B#1 ; DATA LATCH ENABLE DLE.DIS: EQU B#0 ; OETEN: EQU B#1 ; T BUS ENABLE OETDIS: EQU B ; SOA: EQU H#4 ; ACC SOD: EQU H#6 ; D SOI: EQU H#7 ; I SOZ: EQU H#8 ; 0 SOZE: EQU H#9 ; D(0E) SOSE: EQU H#A ;******************* AM2910: SUB 4VH#E,3VX,12V$X ; AM2910-COND MUX-BRANCH/COUNTER FIELDS ; *********************************STATUS SOAR: EQU H#4 ; ACC RAM SODR: EQU H#6 ; D RAM SOIR: EQU H#7 ; I RAM SOZR: EQU H#8 ; 0 RAM SOZER: EQU H#9 ; *********************** ; ; OPCODES [5] ; SUBR: EQU H#0 ; S minus R SUBRC: EQU H#1 ; S minus R with carry SUBS: EQU ST,OPCODE,REGISTER ; [M] [7] [5] [R] ; ************************************************************ ; ; THE BYTE-WORD SELECT. ; EXAMPLE: THE ALLOWED OPCODE SUBSTITUTIONS IN TOR1 COME FROM GROUP [5] ; WHILE THE ALLOWED SOURCE-DESTID,SOURCE,DIRECT-INPT,REGISTER ; [M] [10] [9] [R] ; ***************************************************** ; R: EQU H#C ; RAM ACC RAM TORIR: EQU H#E ; RAM I RAM TODRR: EQU H#F ; D RAM RAM ; ; ************************************************************* ; ; DIRECTION AND INPUT [9] ; SHUPZ: EQU H#0 ; UP 0 SHUP1: EQU H#1 ; UP 1 SHUPL: EQU H#2 H#2 ; R minus S SUBSC: EQU H#3 ; R minus S with carry ADD: EQU H#4 ; R plus S ADDC: EQU H#5 ; R plus S with carry AND:SOURCE [8] R S ; TODA: EQU H#1 ; D ACC TOAI: EQU H#2 ; ACC I TODI: EQU H#5 ; D I ; *NATIONS COME FROM GROUP [6]. ; EJECT ; ; ; ; ; ; SOURCE-DESTINATION [7] R S DEST ; TODA ; ; SOURCE [11] ; SHA: EQU H#6 ; ACC SHD: EQU H#7 ; D ; ; ; ***************************************************************************** TOR1: DEF AM2910,1V, B#00,4V, 4V, 5V%, ZZZZZ ; TWO OPERAND RAM (1) ; ; MODE,QUAD,SOURC; UP QLINK SHDNZ: EQU H#4 ; DOWN 0 SHDN1: EQU H#5 ; DOWN 1 SHDNL: EQU H#6 ; DOWN QLINK SHDNC: EQU H#7 ; DOWN QC SHD EQU H#6 ; R . S NAND: EQU H#7 ; R . S EXOR: EQU H#8 ; R S NOR: EQU H#9 ; R + S OR: EQU H#A ; R + S EXNOR: EQU********************************************************** TONR: DEF AM2910,1V, B#11,4V, 4V, 5V%, ZZZZZ ; TWO OPERAND NR: EQU H#1 ; D ACC RAM TOAIR: EQU H#2 ; ACC I RAM TODIR: EQU H#5 ; D I RAM ; ; **************************************** SHFTNR: DEF AM2910,1V, B#11,4V, 4V, 5V%, ZZZZZ ; SHIFT NON-RAM ; ; MODE,QUAD,SOURCE,DIRECT-INP,DESTINATION ; [M] E-DEST,OPCODE,REGISTER ; [M] [6] [5] [R] ; ************************************************************ NOV: EQU H#8 ; DOWN QN QOVR ; ; ; SOURCE [10] ; SHRR: EQU H#6 ; RAM RAM SHDR: EQU H#7 ; D RAM ; ; ; ************ H#B ; R S ; ; ; SOURCE-DESTINATION [6] ; R S DEST ; TORAA: EQU H#0 ; RAM ACC ACC TORIA: EQU H#2 ; RAM I ACC TODRON-RAM ; ; MODE, QUAD,SOURCE,OPCODE,DESTINATION ; [M] [8] [5] [4] ; *************************************************************** TOR2: DEF AM2910,1V, B#10,4V, 4V, 5V%, ZZZZZ ; TWO OPERAND RAM (2) ; ; MODE,QUAD,SOURCE-DE [11] [9] [4](NRY; NRA ONLY) ; ***************************************************** ; EJECT ; *****************; ; THE [i] IN THE COMMENT BELOW THE VARIABLE-FIELD REFERS TO THE ALLOWED ; MNEMONIC GROUP. EXAMPLE: MODE REFERS VIA [M] TO ***************************************** SHFTR: DEF AM2910,1V, B#10,4V, 4V, 5V%, ZZZZZ ; SHIFT RAM ; ; MODE,QUAA: EQU H#3 ; D RAM ACC TORAY: EQU H#8 ; RAM ACC Y BUS TORIY: EQU H#A ; RAM I Y BUS TODRY: EQU H#B ; D RAM Y BUS TORA***************** EJECT ; ************************************************** ; SHIFT INSTRUCTIONS ; ************************ ********************************* ;ROTATE INSTRUCTIONS ; ************************************************** ; ; SOURCE-DESTIED RAM (1) ; ; MODE,QUAD,N,OPCODE,REGISTER ; [M] [N] [15] [R] ; *************************************************CODE,DESTINATION ; [M] [N] [14] ; ***************************************************** EJECT ; ************* BONR: DEF AM2910,1V, B#11,4V,B#110, 5V%, ZZZZZ ; BIT ORIENTED NON-RAM ; ; MODE,QUAD,N,FIXED CODE,OPCODE ; [M]  ROTR2: DEF AM2910,1V, B#01,4V,4V, 5V%, ZZZZZ ; ROTATE RAM (2) ; ; MODE,QUAD,N,SOURCE-DEST,REGISTER ; [M] [NA: EQU D#1 ; RESET ACC, BIT N SETNA: EQU D#2 ; SET ACC, BIT N A2NA: EQU D#4 ; ACC + 2^N -- ACC S2NA: EQU D#5 ; ACC - NATION [12] ; RTRA: EQU H#C ; RAM ACC RTRY: EQU H#E ; RAM Y BUS RTRR: EQU H#F ; RAM RAM ; ; ; **************************** ; ; ; OPCODES [16] ; LD2NR: EQU H#C ; 2^N --- RAM LDC2NR: EQU H#D ; 2^N --- RAM A2NR: EQU H#E ; RAM + 2^N -******************************************* ; BIT ORIENTED INSTRUCTIONS ; ***************************************************  [N] [17] ; ********************************************************* EJECT ; **********************************] [13] [R] ; ***************************************************** ; ; SOURCE DESTINATION [14] ; RTDY: EQU D#2^N --ACC LD2NA: EQU H#6 ; 2^N -- ACC LDC2NA: EQU D#7 ; 2^N -- ACC TSTND: EQU D#16 ; TEST D, BIT N RSTND: EQU D#17 ;******************************** ROTR1: DEF AM2910,1V, B#00,4V,4V, 5V%, ZZZZZ ; ROTATE RAM (1) ; ; MODE,QUAD,N,SOUR RAM S2NR: EQU H#F ; RAM - 2^N - RAM ; ; ; ******************************************************** BOR2: DEF AM2910,1V,  ; ; OPCODES [15] ; SETNR: EQU H#D ; SET RAM, BIT N RSTNR: EQU H#E ; RESET RAM, BIT N TSTNR: EQU H#F ; TEST RAM, BIT **************** ; ROTATE AND MERGE ; ************************************************** ; ; SOURCE-DEST SELECT [U,S,MASK-DE24 ; D Y BUS RTDA: EQU D#25 ; D ACC RTAY: EQU D#28 ; ACC Y BUS RTAA: EQU D#29 ; ACC ACC ; ; ; ********************** RESET D, BIT N SETND: EQU D#18 ; SET D, BIT N A2NDY: EQU D#20 ; D + 2^N -- Y BUS S2NDY: EQU D#21 ; D - 2^N -- Y BUS LCE-DEST,REGISTER ; [M] [N] [12] [R] ; ***************************************************** ; ; SOURCE-DESTINA B#10,4V,4V, 5V%, ZZZZZ ; BIT ORIENTED RAM (2) ; ; MODE,QUAD,N,OPCODE,REGISTER ; [M] [N] [16] [R] ; ***********N ; ; ; ******************************************************** BOR1: DEF AM2910,1V, B#11,4V,4V, 5V%, ZZZZZ ; BIT ORIENTST] [18] ; ; ROT NON-ROT MASK-DEST MDAI: EQU H#7 ; D ACC I MDAR: EQU H#8 ; D ACC RAM MDRI: EQU H#9 ; D RAM ******************************* ROTNR: DEF AM2910,1V, B#11,4V,H#C, 5V%, ZZZZZ ; ROTATE NON-RAM ; ; MODE,QUAD,N,FIXED D2NY: EQU D#22 ; 2^N -- Y BUS LDC2NY: EQU D#23 ; 2^N -- Y BUS ; ; ; ****************************************************TION [13] ; RTAR: EQU H#0 ; ACC RAM RTDR: EQU H#1 ; D RAM ; ; ; ************************************************************************************************** EJECT ; ; ; ; ; ; OPCODES [17] ; TSTNA: EQU D#0 ; TEST ACC, BIT N RSTN I MDRA: EQU H#A ; D RAM ACC MARI: EQU H#C ; ACC RAM I MRAI: EQU H#E ; RAM ACC I ; ; ; ******************************B ; I ; ; ; *********************************************** PRT2: DEF AM2910,1V, B#10,4V, 4V, 5V%, ZZZZZ ; PRIORITIZE RAMDESTINATION [21] ; PR1A: EQU H#8 ; ACC PR1Y: EQU H#A ; Y BUS PR1R: EQU H#B ; RAM ; ; ********************************* CRCF: DEF AM2910,B#11001100011,5V%, ZZZZZ ; FORWARD ; ******************************************* ; ; ; ****************D RAM ACC CRAI: EQU H#5 ; RAM ACC I ; ; ; ******************************************** ROTC: DEF AM2910,1V, B#01,4V,4V, A: EQU H#4 ; ACC PRTD: EQU H#6 ; D ; ; ; ********************************************** PRTNR: DEF AM2910,1V, B#11,4V**************************** ROTM: DEF AM2910,1V, B#01,4V,4V, 5V%, ZZZZZ ;ROTATE AND MERGE ; ; MODE,QUAD,N,SOURCE-DE ; ; MODE,QUAD,MASK,DEST,REG-SOURCE ; [M] [22] [23] [R] ; *********************************************** EJECT **************** PRT1: DEF AM2910,1V, B#10,4V, 4V, 5V%, ZZZZZ ; RAM ADDR MASK(S) ; ; MODE,QUAD,DESTINATION,SOURCE*************************** CRCR: DEF AM2910,B#11001101001,5V%, ZZZZZ ; REVERSE ; *******************************************  5V%, ZZZZZ ; ROTATE AND COMPARE ; ; MODE,QUAD,N,SOURCE-DEST-MASK,REGISTER ; [M] [N] [19] [R] , 4V, 5V%, ZZZZZ ; PRIORITIZE NON-RAM ; ; MODE,QUAD,MASK,SOURCE,DESTINATION ; [M] [22] [25] [4](NRY,NRAST,REGISTER ; [M] [N] [18] [R] ; ********************************************************** ; ; ; ; ; ; ; ; ; ; SOURCE (R) [24] ; PR3R: EQU H#3 ; RAM PR3A: EQU H#4 ; ACC PR3D: EQU H#6 ; D ; ; ; ******************,REG-MASK ; [M] [21] [20] [R] ; *********************************************** ; ; ; DESTINATION [23] ; ; ; ; ; ; ; ******************************************** ; ; NOOP ; ; ******************************************* ; ********************************************* EJECT ; ; ************************************************** ; PRIORITIZE  ONLY) ; ********************************************** EJECT ; ; ; ; ; ; ********************************************** ; ************************************************** ; ROTATE AND COMPARE ; ***************************************************************************** PRT3: DEF AM2910,1V, B#10,4V, 4V, 5V%, ZZZZZ ; PRIORITIZE RAM ; ; MODE,QUAD,MASK,SOURCE,R PR2A: EQU H#0 ; ACC PR2Y: EQU H#2 ; Y BUS ; ; MASK (S) [22] ; PRA: EQU H#8 ; ACC PRZ: EQU H#A ; 0 PRI: EQU H#* NOOP: DEF AM2910,H#7140, ZZZZZ ; NO OPERATION ; ******************************************** ; EJECT ; ****************; ************************************************** ; ; SOURCE [20] ; PRT1A: EQU H#7 ; ACC PR1D: EQU H#9 ; D ; ; ;  ; CYCLIC REDUNDANCY CHECK ; ********************************************** ; ; ; ******************************************* ; ; ROT.SRC(U)-NON ROT.SRC(S)/DEST-MASK(S)[19] ; CDAI: EQU H#2 ; D ACC I CDRI: EQU H#3 ; D RAM I CDRA: EQU H#4 ; EG-DEST ; [M] [22] [24] [R] ; *********************************************** ; ; ; SOURCE (R) [25] ; PRT ******************************** ; STATUS ; ************************************************ ; ; OPCODE [26] ; SONZC: EQUD#8 ; TEST LOW TC: EQU D#10 ; TEST C TZC: EQU D#12 ; TEST Z + C TN: EQU D#14 ; TEST N TL: EQU D#16 ; TEST LINK TF1:************************** SVSTNR: DEF AM2910,1V, B#11,H#7A, 5V%, ZZZZZ ; SAVE STATUS NON-RAM ; ; MODE,QUAD,FIXED,T LDM: EQU H#E ; LOAD MASK REGISTER ENIN: EQU H#F ; ENABLE INTERRUPT REQUEST ; EJECT ; * * * * * * * * * * * * * * * * * * 10 ; RESET FLAG 3 ; ;***************************************************** RSTST: DEF AM2910,B#011,H#AA,5V%, ZZZZZ ; RESET STAR ALL INTERRUPTS CLRMB: EQU H#2 ; CLEAR INTERRUPTS FROM M-BUS CLRMR: EQU H#3 ; CLEAR INTERRUPTS FROM MASK REGISTER CLRVC: EQ 5D#3 ; SET OVR,N,C,Z SL: EQU 5D#5 ; SET LINK SF1: EQU 5D#6 ; SET FLAG 1 SF2: EQU 5D#9 ; SET FLAG 2 SF3: EQU 5D#10  EQU D#18 ; TEST FLAG 1 TF2: EQU D#20 ; TEST FLAG 2 TF3: EQU D#22 ; TEST FLAG 3 ; ; ; *******************************DESTINATION ; [M] [4](NRY,NRA ONLY) ; **************************************************** ; ; ; ************** ; ; Am2940 DMA CONTROL UNIT ; DMA Address Generator ; TO USE - DELETE THE .40 AND DELETE THE Am2942 INSTRUCTION SET ; DUATUS ; ; OPCODE ; [27] ; **************************************************** EJECT ; ; ; ******************U H#4 ; CLEAR INTERRUPT FROM LAST VECTOR READ RDVC: EQU H#5 ; READ VECTOR RDSTA: EQU H#6 ; READ STATUS REGISTER RDM: EQU H#7 ; SET FLAG 3 ; ; ; ************************************************** SETST: DEF AM2910,B#011,H#BA,5V%, ZZZZZ ; SET STATUS ********************** TEST: DEF AM2910,B#011,H#9A,5V%, ZZZZZ ; TEST STATUS ; ; FIXED, OPCODE ; [CT] ; ******************************************* ; TEST STATUS ; ************************************************* ; ; OPCODE (CT) ; TE TO DUPLICATE MNEMONICS ; ; * * * * * * * * * * * * * * * * * * * ; INSTRUCTIONS ; WRCR.40: EQU Q#0 ; WRITE CONTROL REGIS********************************** SVSTR: DEF AM2910,1V, B#10,H#7A, 5V%, ZZZZZ ; SAVE STATUS-RAM ; ; MODE,QUAD,FIXE; READ MASK REGISTER SETM: EQU H#8 ; SET MASK REGISTER LDSTA: EQU H#9 ; LOAD STATUS REGISTER BCLRM: EQU H#A ; BIT CLEAR MASK ; ; OPCODE ; [26] ; ************************************************** ; ; ; ; OPCODE [27] ; RONCZ: EQU********************************************** EJECT ; * * * * * * * * * * * * * * * * ; ; Am2914 INSTRUCTION SET ; VectorNOZ: EQU D#0 ; TEST (N OVR) + Z TNO: EQU D#2 ; TEST N OVR TZ: EQU D#4 ; TEST Z TOVR: EQU D#6 ; TEST OVR TLOW: EQU TER RDCR.40: EQU Q#1 ; READ CONTROL REGISTER RDWC.40: EQU Q#2 ; READ WORD COUNTER RDAC.40: EQU Q#3 ; READ ADDRESS COUNTER RED,RAM ADDRESS/DEST ; [M] [R] ; **************************************************** ; ; ;***************************REGISTER BSETM: EQU H#B ; BIT SET MASK REGISTER CLRM: EQU H#C ; CLEAR MASK REGISTER DISIN: EQU H#D ; DISABLE INTERRUPT REQUES D#3 ; RESET OVR,N,C,Z RL: EQU D#5 ; RESET LINK RF1: EQU D#6 ; RESET FLAG 1 RF2: EQU D#9 ; RESET FLAG 2 RF3: EQU D#ed Priority Interrupt Controller ; ; * * * * * * * * * * * * * * * * ; MCLR: EQU H#0 ; MASTER CLEAR CLRIN: EQU H#1 ; CLE IN.40: EQU Q#4 ; REINITIALIZE COUNTERS LDAD.40: EQU Q#5 ; LOAD ADDRESS LDWC.40: EQU Q#6 ; LOAD WORD COUNT ENCT.40: EQU Q#7 ;  LWCT: EQU H#E ; LOAD WORD COUNT, T/C REWC: EQU H#F ; REINITIALIZE WORD COUNTER ; ; TIMER/COUNTER INSTRUCTIONS - INSTRUCTIO ADDRESS LDWC: EQU H#6 ; LOAD WORD COUNT ENCT: EQU H#7 ; ENABLE COUNTERS ; ; DMA INSTRUCTION - INSTRUCTION ENABLE = HIGH ; ; UP SHIFTING (INCOMPLETE) ; SURZQZ: EQU H#2 ; R0<-0; Q0<-0 ; EJECT ; SHIFT ENABLES ; SE.EN: EQU B#0 ; ENABLE SHIF WCOD.40: EQU 8Q#7% ; WORD CNTR CARRY OUT, DECREMENT ADDR CNTR EJECT ; ********************************** ; Am2942 INSTRUCTIO#3 ; 1->RN; R0->QN DDMCR: EQU H#4 ; Mc->RN; R0->QN DLN.RECOVER: EQU H#5 ; MN->RN; R0->QN DDZR: EQU H#6 ; 0->RN; R0->QN ENABLE COUNTERS ; ;CONTROL MODE BYTE ;NOTE - BITS 3 THROUGH 7 ARE DON'T CARE ; WC1I.40: EQU 8Q#0% ; WORD COUNT EQUALS ONE, N ENABLE = HIGH ; ; ALL OF THE ABOVE T/C INSTRUCTIONS BECOME INSTRUCTION DISABLE, T/C ; EJECT ; ***************************; ; ALL OF THE ABOVE BECOME INSTRUCTION DISABLE ; ; TIMER/COUNTER INSTRUCTIONS - INSTRUCTION ENABLE = LOW ; WCRT: EQU H#8 TING SE.DIS: EQU B#1 ; DISABLE SHIFTING ; ; ; ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * N SET ; Programmable Timer/Counter ; DMA Address Generator ; ********************************* ; ; DMA INSTRUCTIONS - ALSO DDZRQMC: EQU H#7 ; 0->RN; R0->QN; Q0->Mc SDROTMC: EQU H#8 ; ROT.R; R0->Mc; ROT.Q SDROTC: EQU H#9 ; ROT.R WITH Mc; ROT.Q INCREMENT ADDR CNTR WCCI.40: EQU 8Q#1% ; WORD COUNT COMPARE, INCREMENT ADDR CNTR ADCI.40: EQU 8Q#2% ; ADDR COMPARE, INCREMENT *********************************************** ; ; Am2904 INSTRUCTION SET - PARTIAL ONLY!!!!! ; BUILD ONLY WHAT YOU NEE ; WRITE CONTROL REGISTER, T/C REAC: EQU H#9 ; REINITIALIZE ADDRESS COUNTER RWCT: EQU H#A ; READ WORD COUNTER, T/C RACT: E* * ; Am2904 STATUS REGISTER INSTRUCTION CODES ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ;  REQUIRES INSTRUCTION ENABLE = LOW ; WRCR: EQU H#0 ; WRITE CONTROL REGISTER RDCR: EQU H#1 ; READ CONTROL REGISTER RDWC: ESDROT: EQU H#A ; ROT.R; ROT.Q SDIC: EQU H#B ; Ic->RN; R0->QN DDROTC: EQU H#C ; Mc->RN; R0->QN; Q0->Mc DDROTMC: EQU H#D ADDR CNTR WCOI.40: EQU 8Q#3% ; WORD CNTR CARRY OUT, INCREMENT ADDR CNTR WC1D.40: EQU 8Q#4% ; WORD COUNT EQUALS ONE, DECREMENT D!!! ; Status and Shift Control Unit ; ; * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; ; DOWN SHIFTING ; SDQU H#B ; READ ADDRESS COUNTER, T/C RAWC: EQU H#C ; REINITIALIZE ADDRESS AND WORD COUNTERS LDAT: EQU H#D ; LOAD ADDRESS, T/C  ; MACHINE STATUS REGISTER INSTRUCTION CODES ; I5-I4-I3-I2-I1-I0 AND EZ-EC-EN-EOVR-CEM ENABLES ; MICRO STATUS REGISTER INSTQU H#2 ; READ WORD COUNTER RDAC: EQU H#3 ; READ ADDRESS COUNTER REIN: EQU H#4 ; REINITIALIZE COUNTERS LDAD: EQU H#5 ; LOAD ; Q0->RN; R0->QN; Q0->Mc DDINIOVR: EQU H#E ; IN EXOR IOVR -> RN; R0->QN DDROT: EQU H#F ; DOUBLE PRECISION ROTATE DOWN ; ADDR CNTR WCCD.40: EQU 8Q#5% ; WORD COUNT COMPARE, DECREMENT ADDR CNTR ADCD.40: EQU 8Q#6% ; ADDR COMPARE, DECREMENT ADDR CNTR ZRZQ: EQU H#0 ; Z->RN; Z->QN SDOROQ: EQU H#1 ; 1->RN; 1->QN SLN.RECOVER: EQU H#2 ; 0->RN; R0->Mc; MN->QN DDOR: EQU H RUCTION CODES ; I5-I4-I3-I2-I1-I0 AND CEu ENABLE ; ; THE FOLLOWING TAKES THESE ALL TOGETHER - YOU MAY WISH TO DO THIS ANOT SHIFT SE.EN TEST.04: DEF 42X, 12VQ#7777, 1VB#0, 9X ; DISABLED OECTEN STATUS.04: DEF O STATUS OPERATION TESTMOVR: EQU 12Q#4677 ; NO STATUS OPERATION TESTMC: EQU 12Q#5277 ; NO STATUS OPERATION TESTMN: EQU 12Q#READY: EQU B#0 ; NOTREADY: EQU B#1 ; ; INITIALZE: EQU B#0 ; NO.INIT: EQU B#1 ; ; EJECT ; * * * * * * * * * * * * * *2Q#3001 ; ALU -> MSR; Ic INVERTED LDINVRTU: EQU 12Q#3076 ; ALU -> USR; Ic INVERTED LOAD.INVERT: EQU 12Q#3000 ; ALU -> MSR, USREQU Q#7 ; 6 200ns AT 30MHz CLE: EQU Q#3 ; 7 280ns AT 25MHz CLF: EQU Q#2 ; 8 320ns AT 25MHz CLG: EQU Q#6 ; 9 300ns AT HER WAY ; ; ORDER: 543 210 ZCNOVR CEM CEu ; Q# Q# H# B# B# ; ONELEVEL: EQU 12Q#0000 ; Y -> MSR; MSR -> USR42X, 12VQ#2001, B#1, 1VB#0, 4X, B#1, 3X ; LOAD.MSR NO CT OEYEN SE.DIS EJECT ; * * * * * * * * * * *5677 ; TEST.IOVR: EQU 12Q#6677 ; TEST.IC: EQU 12Q#7277 ; ; ; ; TEST ENABLE ; OECTEN: EQU B#0 OECTDIS: EQU B#1 ; ; ;  * * * * * * * ; ; Am2950/51 ; ; Eight-Bit Bidirectional I/O Ports ; ; * * * ; ; END ; Ic INVERTED ; EJECT ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; Am2904 CONDITION CODE OUTPUT INSTRUCTIO30MHz CLH: EQU Q#4 ; 10 CLOCK PERIODS 322ns AT 31MHz ; (max crystal frequency is 31MHz) ; ; OTHER CONTROL LINES FOR SET.MSR: EQU 12Q#0101 ; SET MACRO STATUS ONLY SET.USR: EQU 12Q#0176 ; SET MICRO STATUS ONLY SWAP.REG: EQU 12Q#0200 ; MSR <-- * * * * * * * * * * * * * * * * * * * * * * * * ; ; Am2925 CYCLE LENGTH SELECT ; System Clock Generator and Driver ; ; * *INSTRUCTION ENABLE ; IEN.04: EQU B#0 IENDIS: EQU B#1 ; EJECT AM2904: DEF 42X, 12VQ#2001, 1VB#1, 1VB#0, 4VX, 1VB#1, N CODES ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; caution! I5-I4-I3-I2-I1-I0 ARE ALSO USED FOR TESTING!!! THE Am2925 ; INCOMPLETELY DEFINED AT PRESENT (IN THIS FILE) ; FIRST.25: EQU B#1 ; LAST.25: EQU B#0 ; ; HALT: E> USR ; LOAD.MSR: EQU 12Q#2001 ; ALU STATUS -> MSR ; THE ABOVE IS ONE OF SEVERAL CODES - YOU DON'T NEED THEM ALL! ; LOAD.US * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; ; THE FOLLOWING ARE THE CYCLE LENGTH CODES (PRELIM) ; 3X ; DEFAULTS LOAD.MSR OECTDIS OEYEN X SE.DIS ; SHIFT.04: DEF 56X, 4VX, 1B#0, 3X ; ! ; ENABLE TESTING VIA OEct ENABLE ; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; TESTMZ: EQU 12Q#4477 ; NQU B#00 ; NOHALT: EQU B#00 ; ; SINGLSTP: EQU B#00 ; RUN: EQU B#00 ; ; WAITREQ: EQU B#0 ; NOWAITRQ: EQU B#1 ; ; R: EQU 12Q#2076 ; ALU STATUS -> USR ; DITTO! ; LOAD.BOTH: EQU 12Q#2000 ; ALU -> MSR, USR ; AGAIN DITTO! ; LDINVRTM: EQU 1 CLA: EQU Q#0 ; 3 CLOCK PERIODS 100ns AT 30MHz CLB: EQU Q#1 ; 4 160ns AT 25MHz CLC: EQU Q#5 ; 5 200ns AT 25MHz CLD:  16H#C001 ; CRCF POLYNOMIAL MASK CRCNIT: EQU 16 ; CRCF NUMBER OF ITERATIONS (D#16 <-- default base) NSPASS: EQU 64 ; NUMBER O ; LSB OF TRACK NUMBER IN MSB OF R2 ; ; SECTOR NUMBER IN LSB OF R2 ; ; START ADDRESS OF RAM SECTOR BUFFER IN R3 ; EJEC WRITTEN. ; SECTIO: BOR2 W,0,S2NR,R0 / &NODLE &NOIEN &NOOEY &NOSRE ;<------ note use of overlayed / &CT Z &NOJMPI ;hout notice in order to improve design or performance ; characteristics. The company assumes no responsibility for the ; use IG. WORD) A3LSW: EQU H#D530 ; A3' CONS.(LEAST SIG. WORD) A4LSW: EQU H#A928 ; A4' CONS.(LEAST SIG. WORD) ; KL128: EQU H#710F SECTOR PASSES (SET THIS EQUAL ; TO THE NUMBER OF SECTORS PER TRACK.) RDITCT: EQU 65 ; READ ITERATION COUNT, EQUAL TO T ; ; OUTPUT: ; ; R0 CONTAINS: ; ; 0 IF THE FUNCTION SPECIFIED WAS COMPLETED ; EITHER WITHOUT ERROR OR WITH A ;  DEF statements / &IFNOT CT16 &CJP CFCODE ; signified by "&" ; ; ; RESET THE AM9520 AND THEN PLACE IT IN COMPUTE CHof any circuits or programs described herein. ; ; Am29116 Mnemonics Copyright c 1982 Advanced Micro Devices ; ; ; ; EJE0 ; K(LEAST SIG. WORD) SHIFTED UP ; BY SEVEN PLACES KM128: EQU H#0477 ; K(MOST SIG. WORD) SHIFTED UP ; BY SEVEN PLA TITLE AM29116 / AM9520 - BASED DISK CONTROLLER ; ; CREATED 9/81 TABLER-KITSON ; ; ; ; This SRC file was created for the ATHE NUMBER ; ; OF 16-BIT WORDS (DATA PLUS MODIFIED FIRE ; ; CODE) PER SECTOR, DIVIDED BY TWO, MINUS 1. PF1: EQU 22 ; P SUCCESSFULLY CORRECTED READ ERROR ; ; +1 IF THE SECTOR'S HEADER IS BAD ; ; +2 IF AN UNCORRECTABLE ERROR WAS DETECTED INECK BITS MODE. ; INITIALIZE COUNTER FOR CHECK BITS PRECALCULATION LOOP. ; SONR W,MOVE,SOI,NRY / &NODLE &NOIEN &OEY &NOSRE CT ; ; SECTOR READ / WRITE SUBROUTINE ;****************************************** ; ; INPUTS: ; ; FUNCTION CODE IN R0CES. KLSW: EQU H#EEE2 ; K(LEAST SIG. WORD) KMSW: EQU 8 ; K(MOST SIG. WORD) ; EJECT ; ; ; IF THE FUNCTION CODE IN R0 EQUMD application note: ; "A High-Performance Intelligent Disk Controller" ; by Otis Tabler and Brad Kitson. ; ; Mnemonics and ERIOD FACTOR ONE PF2: EQU 13 ; PERIOD FACTOR TWO PF3: EQU 89 ; PERIOD FACTOR THREE PF4: EQU 23 ; PERIOD FACTOR FOUR ; A1 ; READING THE SECTOR'S DATA SEGMENT EJECT ; ; ADDITIONAL MNEMONICS ; ********************* ; ; CRCMSK: EQU / &NOJMPI / &CONT ; IMME H#0000 / &NODLE &NOIEN &OEY &NOSRE / &BT20 &NOJMPI / &CONT ; SONR W,MOVE,SOI,NRY / &NODLE &N: ; ; 0 TO READ SECTOR ; ; +1 TO WRITE SECTOR ; ; HEAD NUMBER IN MSB OF R1 ; ; MSB OF TRACK NUMBER IN LSB OF R1 ;ALS +1 (WRITE SECTOR), PRECALCULATE ; THE MODIFIED FIRE CODE'S PARTIAL CHECKSUM FOR THE FIRST HALF OF ; THE DATA SEGMENT TO BEword format are defined in DISKCTLR.DEF ; ; Advanced Micro Devices reserves the right to make changes in its ; product witLSW: EQU H#E723 ; A1 CONSTANT(LEAST SIG. WORD) A1MSW: EQU 6 ; A1 CONS.(MOST SIG. WORD) A2LSW: EQU H#BFA8 ; A2 CONS.(LEAST S OIEN &OEY &NOSRE / &NOJMPI / &CONT ; IMME H#0010 / &NODLE &NOIEN &OEY &NOSRE / &BT20 &NOJMPI / &LDCT 127 ; ; ; (R3) TIEN &NOOEY &NOSRE / &NOJMPI / &CONT ; ; ; CLOCK OUT NEXT MODIFIED FIRE CODE BYTE TO THE ; MORE-SIGNIFICANT MEMORY BUS INTE,NRY / &NODLE &NOIEN &OEY &NOSRE / &NOJMPI / &CONT ; IMME H#0011 / &NODLE &NOIEN &OEY &NOSRE / &BT20 &NOJMPI / &LDCT 2 ESS. ; CFCODE: SONR W,MOVE,SOI,NRA / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; IMME BRTABL / &NODLE &IEN &NOOEY &NO ; ; NOOP FOR TIMING PURPOSES ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &NOJMPI / &CONT ; ; ; CLOCK THE MORE SIGNIFICANT ; SOR W,MOVE,SOZR,R5 / &NODLE &IEN &NOOEY &NOSRE / &CP20 &NOJMPI / &CONT ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &CE2L O R4 ; SOR W,MOVE,SORY,R3 / &DLE &NOIEN &OEY &NOSRE / &NOJMPI / &CONT ; SOR W,MOVE,SODR,R4 / &NODLE &IEN &NOOEY &NOSRERFACE REGISTER. ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &CP20 &NOJMPI / &CONT ; ; ; NOOP FOR TIMING PURPOSES ; NOOP  ; ; ; BEGIN STORE CHECK BITS IN BUFFER LOOP. ; (R4) TO THE MAR. ; CLOCK OUT NEXT MODIFIED FIRE CODE BYTE TO THE ; LESS-SIGSRE / &NOJMPI / &CONT ; TOR1 W,ADD,TORAA,R0 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; ; ; CRCF POLYNOMIAL MASK BYTE OF ((MAR)) INTO THE AM9520. ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &BT2U &NOJMPI / &CONT ; ; ; INCREMENT (R4). ; &NOJMPI / &CONT ; SOR B,MOVE,SODR,R5 / &DLE &IEN &NOOEY &NOSRE / &BF2L &BT16 &NOJMPI / &CONT ; ; ; (R4) TO MAR. ; S / &NOJMPI / &CONT EJECT ; ; BEGIN CHECK BITS PRECALCULATION LOOP. ; (R4) TO THE MAR. ; PCPREL: SOR W,MOVE,SORY,R4 / &N/ &NODLE &NOIEN &NOOEY &NOSRE / &NOJMPI / &CONT ; EJECT ; (BUS INTERFACE REGISTER PAIR) TO (MAR). ; INCREMENT (R4). ; ENDNIFICANT MEMORY BUS INTERFACE REGISTER. ; SCBIBL: SOR W,MOVE,SORY,R4 / &NODLE &NOIEN &OEY &NOSRE / &CP20 &MADR &NOJMPI / &CTO ACC. ; SONR W,MOVE,SOI,NRA / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; IMME CRCMSK / &NODLE &IEN &NOOEY END CHECK BITS PRECALCULATION LOOP. ; SOR W,INC,SORR,R4 / &NODLE &IEN &NOOEY &NOSRE / &CP20 &NOJMPI / &RPCT PCPREL EJECT OR W,MOVE,SORY,R4 / &NODLE &NOIEN &OEY &NOSRE / &MADR &NOJMPI / &CONT ; ; ; (R5) TO (MAR). ; SOR W,MOVE,SORY,R5 / &NODODLE &NOIEN &OEY &NOSRE / &MADR &NOJMPI / &CONT ; ; ; CLOCK THE LESS SIGNIFICANT BYTE OF ((MAR)) INTO THE AM9520. ; NOOP STORE CHECK BITS IN BUFFER LOOP. ; SOR W,INC,SORR,R4 / &NODLE &IEN &NOOEY &NOSRE / &BF2L &BF2U &MWRT &NOJMPI / &RPCT SCBIONT ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &CE2L &NOJMPI / &CONT ; ; ; NOOP FOR TIMING PURPOSES ; NOOP / &NODLE &NO&NOSRE / &NOJMPI / &CONT ; ; ; CLEAR REGISTER USED TO ACCUMULATE CRCF. ; SOR W,MOVE,SOZR,R4 / &NODLE &IEN &NOOEY &NOSRE ; ; PLACE THE AM9520 IN WRITE CHECK BITS MODE. ; INITIALIZE COUNTER FOR STORE CHECK BITS IN BUFFER LOOP. ; SONR W,MOVE,SOILE &NOIEN &OEY &NOSRE / &BF16 &MWRT &NOJMPI / &CONT ; EJECT ; ; CONVERT THE FUNCTION CODE IN R0 TO A MICROCODE BRANCH ADDR / &NODLE &NOIEN &NOOEY &NOSRE / &BT2L &NOJMPI / &CONT ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &CP20 &NOJMPI / &CONT ; BL ; ; ; ZERO THE UPPER BYTE OF (R5) AND THEN CLOCK THE 7TH AND LAST ; BYTE OF THE MODIFIED FIRE CODE INTO ITS LOWER BYTE.   / &NOJMPI / &CONT ; ; ; COPY HEAD BYTE AND TRACK BYTE 1 TO R5. ; SET CRCF LOOP COUNTER. ; SOR W,MOVE,SORY,R1 / &DLE UMBER ; TO R5 AND D-LATCH. ; PASS WHEN INPUT AVAILABLE FROM FIFO ARRAY. ; SOR W,MOVE,SODR,R5 / &DLE &IEN &NOOEY &NOSRE / YTE SYNC ACQUISITION CIRCUITRY AND FIFO ARRAY. ; SECTL1: NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &ADMC &INPT &NOJMPI &RDGA &RFICIFIED BY R0. ; OTHERWISE, ASSUME BAD HEADER, TRUE ID UNKNOWN, ; AND CONTINUE LOOP. ; TOR1 W,EXOR,TODRR,R4 / &NODLE &NOIEN / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; ; ; SHIFT R5 AND SET QLINK. ; CRCFL2: SHFTR W,SHUPZ,SHRR,R5 / &NODLE &IY &NOSRE / &BF03 &BT16 &INPT &NOJMPI &RDGA / &IFNOT RDYI &CJP $ EJECT ; ; COMPARE THE CONTENTS OF R2 AND R5; ; IF THEY DIS&IEN &NOOEY &NOSRE / &NOJMPI / &LDCT CRCNIT ; SOR W,MOVE,SODR,R5 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT EJECT ;&BF03 &BT16 &INPT &NOJMPI &RDGA / &IFNOT RDYI &CJP $ ; ; ; COMPARE THE CONTENTS OF R1 AND R5. ; IF THEY DISAGREE, EXAMINE TF / &CONT ; ; ; PASS WHEN ADDRESS MARK DETECTED. ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &ADMC &INPT &NOJMPI &RDGA / &I &NOOEY &SRE &CT Z / &INPT &NOJMPI &RDGA / &IF CT16 &CJP MATCH1 ; ; ; TURN OFF READ GATE. ; LEAVE INPUT MODE. ; END SECTOEN &NOOEY &NOSRE / &NOJMPI / &CONT ; ; ; ACCUMULATE CRCF. ; CRCF R4 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &RPCT CRCAGREE, EXAMINE THE NEXT SECTOR. ; TOR1 W,EXOR,TODRR,R2 / &NODLE &NOIEN &NOOEY &SRE &CT Z / &PF03 &INPT &NOJMPI &RDGA / &IF ; SHIFT R5 AND SET QLINK. ; CRCFL1: SHFTR W,SHUPZ,SHRR,R5 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; ; ; ACCUMULAHE NEXT SECTOR. ; TOR1 W,EXOR,TODRR,R1 / &NODLE &NOIEN &NOOEY &SRE &CT Z / &INPT &NOJMPI &RDGA / &IF CT16 &CJP SECTL2 ; FNOT SAMD &CJP $ ; ; ; TURN OFF ADDRESS MARK CONTROL. ; PASS WHEN INPUT AVAILABLE FROM FIFO ARRAY. ; NOOP / &NODLE &NOIER PASS LOOP. ; NOTICE WE HAVE THREE MICROINSTRUCTION CLOCKS LEFT BEFORE ; IT IS TIME TO BEGIN WRITING OR RE-SYNC AND BEGIN REAFL2 EJECT ; ; INITIALIZE SECTOR PASS LOOP COUNTER. ; ENTER INPUT MODE. ; TURN ON READ GATE. ; ; NOOP / &NODLE &NOIEN & CT16 &CJP SECTL2 ; ; ; INPUT RECORDED CRCF BYTES 1 AND 0 TO R5 AND D-LATCH. ; SOR W,MOVE,SODR,R5 / &DLE &IEN &NOOEY &NOSTE CRCF. ; CRCF R4 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &RPCT CRCFL1 ; ; ; COPY TRACK BYTE 2 AND SECTOR BYTE TO R5. ; ; INPUT LSB OF RECORDED TRACK NUMBER AND RECORDED SECTOR NUMBER ; TO R5 AND D-LATCH. ; PASS WHEN INPUT AVAILABLE FROM FIFO N &NOOEY &NOSRE / &INPT &NOJMPI &RDGA / &IFNOT RDYI &CJP $ EJECT ; ; INPUT RECORDED HEAD NUMBER AND MSB OF RECORDED TRACK NDING. ; SECTL2: SOR W,MOVE,SORY,R0 / &NODLE &NOIEN &NOOEY &NOSRE / &NOJMPI / &RPCT SECTL1 ; ; ; IF SECTOR SEARCH COUNT ENOOEY &NOSRE / &INPT &NOJMPI &RDGA / &LDCT NSPASS ; ; ; BEGIN SECTOR PASS LOOP. ; TURN ON ADDRESS MARK CONTROL. ; RESET BRE / &BF03 &BT16 &INPT &NOJMPI &RDGA / &CONT ; ; ; COMPARE THE TWO CRCFS. ; IF THEY AGREE, PROCEED TO READ OR WRITE AS SPE ; SET CRCF LOOP COUNTER. ; SOR W,MOVE,SORY,R2 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI / &LDCT CRCNIT ; SOR W,MOVE,SODR,R5 ARRAY. ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &PF03 &INPT &NOJMPI &RDGA / &CONT ; SOR W,MOVE,SODR,R5 / &DLE &IEN &NOOE XHAUSTED, LOAD +1 INTO R0 AND RETURN ; BOR2 W,LD2NR,0,R0 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &RTN EJECT ; ; SUCCESSOP / &NODLE &NOIEN &NOOEY &NOSRE / &BF03 &INPT &NOJMPI &MWRT &RDGA / &IFNOT RDYI &CJP $ ; ; ; INCREMENT (R5) AND TRANSFER / &INPT &NOJMPI &RDGA / &CONT ; IMME H#0003 / &NODLE &NOIEN &OEY &NOSRE / &INPT &NOJMPI &RDGA / &CONT ; SONR W,MOVE,SO RDITCT EJECT ; ; BEGIN READ HIGH SPEED COMPLETION LOOP. ; INCREMENT (R5) AND TRANSFER THIS TO THE MAR. ; RDSEC3: SOR W,INFFER. THE SECOND HALF OF THE BUFFER ; IS PROCESSED BY THE AM9520 IN THE READ HIGH SPEED COMPLETION LOOP. ; RDSEC1: SOR W,NEG&IFNOT RDYI &CJP $ EJECT ; ; TRANSFER (R5) TO THE MAR AGAIN. ; SOR W,MOVE,SORR,R5 / &NODLE &IEN &OEY &NOSRE / &INPT &NOFUL MATCH. ; MATCH1: SOR W,MOVE,SORY,R0 / &NODLE &NOIEN &OEY &NOSRE / &JMPI / &CONT ; BRTABL: SOR W,NEG,SORA,R3 / &NODLETHIS TO THE MAR. ; SOR W,INC,SORR,R5 / &NODLE &IEN &OEY &NOSRE / &INPT &NOJMPI &MADR &RDGA / &CONT ; ; ; CLOCK LESS SIGI,NRY / &NODLE &NOIEN &OEY &NOSRE / &INPT &NOJMPI &RDGA / &CONT ; IMME H#0013 / &NODLE &NOIEN &OEY &NOSRE / &BT20 &INPT C,SORR,R5 / &NODLE &IEN &OEY &NOSRE / &NOJMPI &MADR / &CONT ; ; ; NOOP FOR TIMING PURPOSES ; NOOP / &NODLE &NOIEN &NOO,SOAR,R4 / &NODLE &IEN &OEY &NOSRE / &INPT &NOJMPI &MADR &RDGA &RFIF / &LDCT RDITCT ; ; ; (R3) - 1 TO R5. ; PASS WHEN INPJMPI &MADR &RDGA / &CONT ; ; ; THIS TIME, CLOCK THE MORE SIGNIFICANT BYTE OF ((MAR)) ; INTO THE AM9520. ; END READ DATA SE &IEN &NOOEY &NOSRE / &NOJMPI &RFIF / &JP RDSEC1 ; SOR W,NEG,SORA,R3 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI &RFIF / &JP WNIFICANT BYTE OF ((MAR)) INTO THE AM9520. ; INCREMENT (R4) AND TRANSFER THIS TO THE MAR. ; SOR W,INC,SORR,R4 / &NODLE &IEN &NOJMPI &RDGA / &CONT ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &INPT &NOJMPI &PF03 &RDGA / &CONT EJECT ; ; BEGIN READ DAEY &NOSRE / &NOJMPI / &CONT ; ; ; CLOCK LESS SIGNIFICANT BYTE OF ((MAR)) INTO THE AM9520. ; NOOP / &NODLE &NOIEN &NOOEYUT AVAILABLE FROM FIFO ARRAY. ; SOR W,COMP,SOAR,R5 / &NODLE &IEN &NOOEY &NOSRE / &INPT &NOJMPI &RDGA / &IFNOT RDYI &CJP $ GMENT LOOP. ; SOR W,INC,SORR,R4 / &NODLE &IEN &OEY &NOSRE / &BT2U &CP20 &INPT &NOJMPI &MADR &MREA &PF03 &RDGA / &RPCT RDSERSEC1 EJECT ; ; READ SECTOR ; ; (R3) TO R4 AND MAR. ; ENTER INPUT MODE AGAIN. ; TURN READ GATE BACK ON. ; INITIALIZE COU&OEY &NOSRE / &BT2L &CP20 &INPT &NOJMPI &MADR &MREA &PF03 &RDGA / &CONT ; ; ; TRANSFER NEXT WORD FROM FIFO ARRAY TO (MAR). TA SEGMENT LOOP. ; TRANSFER NEXT WORD FROM FIFO ARRAY TO (MAR). ; PASS WHEN FIFO INPUT AGAIN BECOMES AVAILABLE. ; RDSEC2: NO &NOSRE / &BT2L &CP20 &NOJMPI &MREA / &CONT ; ; ; NOOP FOR TIMING PURPOSES ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &NOJ EJECT ; ; RESET THE AM9520 AND THEN PLACE IT IN READ HIGH SPEED MODE. ; SONR W,MOVE,SOI,NRY / &NODLE &NOIEN &OEY &NOSRE C2 ; ; ; INITIALIZE COUNTER FOR READ HIGH SPEED COMPLETION LOOP. ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &NOJMPI / &LDCTNTER FOR READ DATA SEGMENT LOOP. ; DURING THAT LOOP, AM9520 READ HIGH SPEED IS PERFORMED ON THE ; FIRST HALF OF THE SEGMENT BU ; PASS WHEN FIFO INPUT AGAIN BECOMES AVAILABLE. ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &BF03 &INPT &NOJMPI &MWRT &RDGA /  MPI / &CONT ; ; ; NOOP FOR TIMING PURPOSES ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &NOJMPI / &CONT EJECT ; ; CLOCK MLE &IEN &NOOEY &SRE / &NOJMPI &CP20 / &IF AE20 &CJP AE ; ; ; AE NOT PRESENT, ; ADD 8 TO R8. ; BOR2 W,3,A2NR,R8 / &NODL6 / &CONT ; ; ; CLEAR R8(M1). ; SOR W,MOVE,SOZR,R8 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; ; ; PERIOD FACTOJMPI / &CONT ; ; ; JUMP TABLE ADDRESS(TAB1) TO R12. ; SOR W,MOVE,SOI,R12 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONTHE CORRECT HIGH SPEED EQUATION: ; ; L=NK - (M1A1 + M2A2 + M3A3 + M4A4) ; ; WHERE K,A1,A2,A3,A4 ARE CONSTANTS ; AND M1,; ; PERIOD FACTOR 2(PF2) TO R9(M2). ; PERIOD FACTOR 3(PF3) TO R10(M3). ; PERIOD FACTOR 4(PF4) TO R11(M4). ; M234I: SOR W,MOORE SIGNIFICANT BYTE OF ((MAR)) INTO THE AM9520. ; END READ HIGH SPEED COMPLETION LOOP. ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE &IEN &NOOEY &NOSRE / &NOJMPI / &JP LINK ; ; ; AE PRESENT; ; INC R8. ; AE: BOR2 W,0,A2NR,R8 / &NODLE &IEN &NOOEY &NOSRR 1(PF1) TO ACC. ; SONR W,MOVE,SOI,NRA / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; IMME PF1 / &NODLE &IEN &NOOEY & ; IMME TAB1 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; ; ; JUMP INDIRECT TO TAB1 VIA PM2-4. ; ROTM W,15,MDRI,RM2,M3,M4 MUST BE CALCULATED. ; ; THE ERROR IS CORRECTED BY PERFORMING AN EXOR ; FUNCTION ON THE BURST ERROR IN MEMORY WITH AVE,SOI,R9 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; IMME PF2 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT EJECTE / &BT2U &CP20 &NOJMPI &MREA / &RPCT RDSEC3 ; ; ; WAS AN ERROR DETECTED BY THE AM9520? ; NOOP / &NODLE &NOIEN &NOOEY &E / &NOJMPI / &CONT EJECT ; ; TEST FOR PERIOD FACTOR EXCEEDED (UNCORRECTABLE ERROR). ; LINK: NOOP / &NODLE &NOIEN &NOOEYNOSRE / &NOJMPI / &CONT EJECT ; ; TEST FOR ERROR PATTERN PRESENT. ; M1: NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &NOJMPI 12 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &PFPM &BF2U &BT16 / &CONT ; IMME H#0007 / &NODLE &IEN &OEY &NOSRE / &JMPI &PFPM &N ; ERROR PATTERN(EP) PROVIDED BY THE BEP(9520). ; ; INITIALIZE CORRECT HIGH SPEED,SET P0=1,& REP=1 EJECT RDSEC4: SONR W,MO SOR W,MOVE,SOI,R10 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; IMME PF3 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / NOSRE / &NOJMPI / &IF ER20 &CJP RDSEC4 ; ; ; NO; LOAD 0 INTO R0 AND RETURN. ; SOR W,MOVE,SOZR,R0 / &NODLE &IEN &NOOEY & &NOSRE &CT N / &NOJMPI / &IFNOT CT16 &CJP M1 ; ; ; PERIOD FACTOR EXCEEDED (UNCORRECTABLE ERROR); ; SET R0 = 2. ; RETURN./ &IF EP20 &CJP M234I ; ; ; EP NOT PRESENT, ; DECREMENT ACC. ; TEST FOR ALIGNMENT EXCEPTION(AE). ; BONR W,0,S2NA / &NODBF2U &BT16 / &JP $ EJECT ; ; R9 = PF2 - R9. ; MFIX: TOR1 W,TORIR,SUBR,R9 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT VE,SOI,NRY / &NODLE &NOIEN &OEY &NOSRE / &NOJMPI / &CONT ; IMME H#001F / &NODLE &NOIEN &OEY &NOSRE / &NOJMPI &BT20 &BF1&CONT ; SOR W,MOVE,SOI,R11 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; IMME PF4 / &NODLE &IEN &NOOEY &NOSRE / &NONOSRE / &NOJMPI / &RTN ; ; ; YES; IF THE ERROR IS A CORRECTABLE ONE, LOCATE AND CORRECT IT. ; THE ERROR IS LOCATED USING T ; ERR: BOR2 W,1,LD2NR,R0 / &NODLE &IEN &OEY &NOSRE / &NOJMPI &BT20 &BF16 / &RTN ; ; ; EP PRESENT, CALCULATE M2,M3,M4.   ; IMME PF2 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; ; ; R10 = PF3 - R10. ; TOR1 W,TORIR,SUBR,R10 / &NODLE &I&NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &LDCT 4 ; ; ; R11 TO D. ; LAC = LAC + M4A4. ; SOR W,MOVE,SORY,R11 / &DLE &NOIENC + M2A2. ; SOR W,MOVE,SORY,R9 / &DLE &NOIEN &OEY &NOSRE / &NOJMPI / &JS MUL ; ; ; A3'(A3 - 4K) TO R12,R13. ; M3A3: IME H#0FFF / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; ; ; MASK UPPER 12 BITS OF R6 TO OBTAIN FIRST BIT OF ; BURST ERR / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; SOR W,MOVE,SOI,R13 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; I &CONT ; IMME KMSW / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; ; ; 0 TO R8. ; XORMEM: SOR W,MOVE,SOZR,R8 / &NODEN &NOOEY &NOSRE / &NOJMPI / &CONT ; IMME PF3 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; ; ; R11 = PF4 - R11.  &OEY &NOSRE / &NOJMPI / &JS MUL ; ; ; PRESHIFTED DIVISOR(K) TO R12,R13,D. ; LAC = REM(M1A1 + M2A2 + M3A3 + M4A4) / K. ; MME A3LSW / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; BOR2 W,1,LD2NR,R13 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &LOR AND STORE IN R6. ; TOR1 W,TORIR,AND,R6 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; IMME H#000F / &NODLE &IEN &NMME A1MSW / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &LDCT 4 ; ; ; R8 TO D. ; LAC = M1A1, MULTIPLY M1A1. ; SOR W,MOVE,SORLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; ; ; 0 TO R9. ; SOR W,MOVE,SOZR,R9 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &; TOR1 W,TORIR,SUBR,R11 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; IMME PF4 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPILAC = -L + K. ; IMME KL128 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; SOR W,MOVE,SOI,R13 / &DLE &IEN &OEY &NOSRE DCT 6 ; ; ; R10 TO D. ; LAC = LAC + M3A3. ; SOR W,MOVE,SORY,R10 / &DLE &NOIEN &OEY &NOSRE / &NOJMPI / &JS MUL EJECT OOEY &NOSRE / &NOJMPI / &CONT ; ; ; JUMP INDIRECT TO TAB2 VIA R6. ; TOR1 W,TORIR,ADD,R6 / &NODLE &IEN &NOOEY &NOSRE / Y,R8 / &DLE &NOIEN &OEY &NOSRE / &NOJMPI / &JS MUL EJECT ; ; A2 TO R12,R13. ; M2A2: IMME A2LSW / &NODLE &IEN &NOOEY &NOCONT ; ; ; 0 TO ACC. ; SOR W,MOVE,SORA,R9 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT EJECT ; ; ROTATE R6 DOWN BY  / &CONT EJECT ; ; 0 TO R7 (LOCATION ACC MSW,LAC). ; M1A1: SOR W,MOVE,SOZR,R7 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / & / &NOJMPI / &LDCT 6 ; IMME KM128 / &DLE &IEN &OEY &NOSRE / &NOJMPI / &JS DIV EJECT ; ; L = LAC = K - LAC. ; SUBK: ; ; A4'(A4 - 4K) TO R12,R13. ; M4A4: IMME A4LSW / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; BOR2 W,3,LD2NR,R13 / &NOJMPI / &CONT ; IMME TAB2 / &NODLE &IEN &OEY &NOSRE / &JMPI / &CONT EJECT ; ; MADR = ACC = R4 - ACC. ; XOR: TOR1 WSRE / &NOJMPI / &CONT ; BOR2 W,3,LD2NR,R13 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &LDCT 3 ; ; ; R9 TO D. ; LAC = LAFOUR TO OBTAIN WORD ADDRESS ; AND STORE IN ACC. ; ROTM W,12,MRAI,R6 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; IMCONT ; ; ; A1 TO R12(LSW),R13(MSW). ; SOR W,MOVE,SOI,R12 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; IMME A1LSW IMME KLSW / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; TOR1 W,TORIR,SUBRC,R7 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / ,TORAA,SUBS,R4 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; BONR W,0,S2NA / &NODLE &IEN &OEY &NOSRE / &MADR &NOJMPI OR W,MOVE,SOZR,R6 / &NODLE &IEN &NOOEY &SRE / &NOJMPI &PFPM / &JP MFIX EJECT TM34: NOOP / &NODLE &NOIEN &NOOEY &NOSRE / ; BOR2 W,0,S2NR,R11 / &NODLE &IEN &NOOEY &SRE / &NOJMPI &CP20 &PFPM / &JP TM34 ; BOR2 W,0,S2NR,R9 / &NODLE &IEN &NOOEY &CJP PM1 ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &NOJMPI / &JP ERR ; ; ; TABLE 2 IS USED FOR ROTATING MEMORY WORD(S) ;  &NOJMPI &MWRT &BF16 / &CONT ; ; ; 0 TO R0 (ERROR CORRECTED FLAG). ; RETURN. ; SOR W,MOVE,SOZR,R0 / &NODLE &IEN &OEY & / &NOJMPI &CP20 &PFPM / &IF CT16 &CJP ERR ; PM1: ROTM W,15,MDRI,R12 / &DLE &IEN &NOOEY &NOSRE &CT N / &NOJMPI &PFPM &BT16/ &CONT ; ; ; R8 = R8 XOR MEM. ; TOR1 W,TODRR,EXOR,R8 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 / &CONT ; ; ; R8 TO &NOJMPI &CP20 &PFPM / &JP PM34 ; TM24: NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &NOJMPI &CP20 &PFPM / &JP PM24 ; TM23: NOOP &SRE / &NOJMPI &CP20 &PFPM / &JP TM24 ; BOR2 W,0,S2NR,R11 / &NODLE &IEN &NOOEY &SRE / &NOJMPI &CP20 &PFPM / &JP TM1 ; VIA ROTATE AND MERGE INSTRUCTI0N(S) SO THAT ; BURST ERRORS CAN BE ALIGNED WITH THE ERROR ; PATTERN PROVIDED BY THE BEP(9520). NOSRE / &NOJMPI &BT20 &BF16 / &RTN EJECT ; ; TABLE 1 IS USED TO CALCULATE ; M2,M3,M4 AND DETECT UNCORRECTABLE ERRORS. ;  &BF2U / &IF CT16 &CJP LINK ; IMME H#0007 / &NODLE &IEN &OEY &NOSRE / &JMPI &PFPM &BT16 &BF2U / &JP $ EJECT PM24: BOR2MEMORY. ; SOR W,MOVE,SORY,R8 / &NODLE &NOIEN &OEY &NOSRE / &NOJMPI &MWRT &BF16 / &CONT ; ; ; MADR = ACC + 1. ; SONR  / &NODLE &NOIEN &NOOEY &NOSRE / &NOJMPI &CP20 &PFPM / &JP PM23 ; TM1: NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &NOJMPI &CP20  BOR2 W,0,S2NR,R10 / &NODLE &IEN &NOOEY &SRE / &NOJMPI &CP20 &PFPM / &JP TM23 ; BOR2 W,0,S2NR,R10 / &NODLE &IEN &NOOEY  ; TAB2: ROTM W,9,MDRI,R8 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP1 ; ROTM W,10,MDRI,R8 / &DLE &EACH MICROINSTRUCTION PATH DECREMENTS THE ; APPROPRIATE REGISTER(S) AND CHECKS FOR VALUES ; EXCEEDING THE 56-BIT POLYNOMIAL PE W,0,S2NR,R11 / &NODLE &IEN &NOOEY &SRE &CT N / &NOJMPI &CP20 &PFPM / &IFNOT CT16 &CJP PM1 ; NOOP / &NODLE &NOIEN &NOOEY W,INC,SOA,NRY / &NODLE &NOIEN &OEY &NOSRE / &NOJMPI &MADR / &CONT ; ; ; R9 = R9 XOR MEM. ; TOR1 W,TODRR,EXOR,R9 / &DLE&PFPM / &CONT ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &NOJMPI &CP20 &PFPM / &JP PM1 ; PM234: BOR2 W,0,S2NR,R11 / &NODLE&SRE / &NOJMPI &CP20 &PFPM / &JP TM1 ; BOR2 W,0,S2NR,R9 / &NODLE &IEN &NOOEY &SRE / &NOJMPI &CP20 &PFPM / &JP TM1 ; SIEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP2 ; ROTM W,11,MDRI,R8 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BRIOD ; FACTOR LIMITS. ; ALIGN 8 ; TAB1: BOR2 W,0,S2NR,R9 / &NODLE &IEN &NOOEY &SRE / &NOJMPI &CP20 &PFPM / &JP PM234 &NOSRE / &NOJMPI / &JP ERR ; PM23: BOR2 W,0,S2NR,R9 / &NODLE &IEN &NOOEY &SRE &CT N / &NOJMPI &CP20 &PFPM / &IFNOT CT16  &IEN &NOOEY &NOSRE / &NOJMPI &BT16 / &CONT EJECT ; ; R9 TO MEMORY. ; SOR W,MOVE,SORY,R9 / &NODLE &NOIEN &OEY &NOSRE / &IEN &NOOEY &SRE &CT N / &NOJMPI &CP20 &PFPM / &IF CT16 &CJP ERR ; PM34: BOR2 W,0,S2NR,R10 / &NODLE &IEN &NOOEY &SRE &CT N  F2U &BF2L / &JP REP3 ; ROTM W,12,MDRI,R8 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP4 EJECT ROTM WMME H#003F / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP RM6 EJECT REP7: IMME H#007F / &DLE &IEN &NOOEY &NOSEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP16 REP1: IMME H#0001 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U BF2U &BF2L / &JP REP18 ; RM3: ROTM W,11,MDRI,R9 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP19 ; RM4:U &BF2L / &JP REP10 ; ROTM W,3,MDRI,R8 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP11 ; ROTM W,4,MDFFE / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP XOR ; REP14: IMME H#3FFC / &DLE &IEN &NOOEY &NOSRE / &NOJ,13,MDRI,R8 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP5 ; ROTM W,14,MDRI,R8 / &DLE &IEN &NOOEY &NOSRRE / &NOJMPI &BT16 &BF2U &BF2L / &JP RM7 ; REP8: IMME H#00FF / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP &BF2L / &JP RM1 ; REP2: IMME H#0003 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP RM2 ; REP3: IMME H#0007  ROTM W,12,MDRI,R9 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP20 ; RM5: ROTM W,13,MDRI,R9 / &DLE &IEN RI,R8 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP12 ; ROTM W,5,MDRI,R8 / &DLE &IEN &NOOEY &NOSRE / &MPI &BT16 &BF2U &BF2L / &JP XOR ; REP15: IMME H#7FF8 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP XOR EJECE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP6 ; ROTM W,15,MDRI,R8 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JPRM8 ; REP9: IMME H#01FF / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP RM9 ; REP10: IMME H#03FF / &DLE &IEN / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP RM3 ; REP4: IMME H#000F / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &&NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP21 ; RM6: ROTM W,14,MDRI,R9 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &NOJMPI &BT16 &BF2U &BF2L / &JP REP13 EJECT ROTM W,6,MDRI,R8 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP RT REP16: IMME H#FFF0 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP XOR ; RM1: ROTM W,9,MDRI,R9 / &DLE &IEN  REP7 ; ROTM W,0,MDRI,R8 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP8 ; ROTM W,1,MDRI,R8 / &DLE &I &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP RM10 ; REP11: IMME H#07FF / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2UBT16 &BF2U &BF2L / &JP RM4 ; REP5: IMME H#001F / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP RM5 ; REP6: IBF2U &BF2L / &JP REP22 ; RM7: ROTM W,15,MDRI,R9 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP23 ; RM8:EP14 ; ROTM W,7,MDRI,R8 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP15 ; ROTM W,8,MDRI,R8 / &DLE &I&NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP17 ; RM2: ROTM W,10,MDRI,R9 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &EN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP9 ; ROTM W,2,MDRI,R8 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2 &BF2L / &JP RM11 ; REP12: IMME H#0FFF / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP XOR ; REP13: IMME H#1!  ROTM W,0,MDRI,R9 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP24 EJECT RM9: ROTM W,1,MDRI,R9 / &DLE &IEHE MAIN PROGRAM THE SUBROUTINE ; INITIATES AN IMMEDIATE MOVE TO R12. ; MUL: SHFTR W,SHDR,SHDNZ,R8 / &NODLE &IEN &NOOEY &SRE  / &NOJMPI &BT16 &BF2U &BF2L / &JP XOR ; REP26: IMME H#C000 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP XO,TORAR,SUBS,R6 / &NODLE &IEN &NOOEY &SRE / &NOJMPI / &CONT ; TOR1 W,TODRR,SUBSC,R7 / &NODLE &IEN &NOOEY &SRE / &NOJMPI &JP XOR ; REP20: IMME H#FF00 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP XOR ; REP21: IMME H#FE00 / &DLERR,SHDNZ,R8 / &NODLE &IEN &NOOEY &SRE / &NOJMPI / &RPCT CYC ; SOR W,MOVE,SOI,R12 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI N &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP25 ; RM10: ROTM W,2,MDRI,R9 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 / &NOJMPI / &CONT ; SOR W,MOVE,SORY,R13 / &DLE &NOIEN &OEY &NOSRE / &NOJMPI / &CONT ; CYC: SOR W,MOVE,SORA,R12 / &NODR ; REP27: IMME H#8000 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP XOR EJECT ; ; SUBROUTINE MULTIPLY ;/ &CONT ; NOOP / &NODLE &IEN &NOOEY &NOSRE &CT N / &NOJMPI / &IFNOT CT16 &CJP POS ; TOR1 W,TORAR,ADD,R6 / &NODLE &IEN &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP XOR ; REP22: IMME H#FC00 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &/ &RTN EJECT ; ; SUBROUTINE DIVIDE ; THIS SUBROUTINE DIVIDES A DOUBLE PRECISION ; NUMBER BY A DOUBLE PRECISION NUMBER LEAVI &BF2U &BF2L / &JP REP26 ; RM11: ROTM W,3,MDRI,R9 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP REP27 ; RELE &IEN &NOOEY &NOSRE &CT L / &NOJMPI / &IFNOT CT16 &CJP NOTQ ; TOR1 W,TORAR,ADD,R6 / &NODLE &IEN &NOOEY &SRE / &NOJMPI  ; THIS SUBROUTINE MULTIPLIES A DOUBLE PRECISION ; WORD BY A SINGLE PRECISION WORD AND ASSUMES ; A DOUBLE PRECISION ANSWER.  &NOOEY &SRE / &NOJMPI / &CONT ; TOR1 W,TODRR,ADDC,R7 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT EJECT POS: SHFTR WBF2U &BF2L / &JP XOR EJECT REP23: IMME H#F800 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP XOR ; REP24: ING ; ONLY A REMAINDER. THE DIVISOR IS IN R12,R13,D ; AND THE DIVIDEND/REMAINDER APPEARS IN R6,R7. ; NOTE, UPON RETURN AN IMMP17: IMME H#FFE0 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP XOR ; REP18: IMME H#FFC0 / &DLE &IEN &NOOEY & / &CONT ; TOR1 W,TODRR,ADDC,R7 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT EJECT NOTQ: SHFTR W,SHRR,SHUPZ,R12 / &NODTHE MULTIPLIER ; IS IN D, THE MULTIPLICAND IS IN R12,R13, AND ; THE ANSWER APPEARS IN R6,R7(LAC). NOTE, UPON ; RETURNING TO T,SHRR,SHDNZ,R13 / &DLE &IEN &OEY &SRE / &NOJMPI / &CONT ; SHFTR W,SHA,SHDNL,R12 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI /MME H#F000 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP XOR ; REP25: IMME H#E000 / &DLE &IEN &NOOEY &NOSRE EDIATE SUBTRACT IS ; INITIATED. ; DIV: SOR W,MOVE,SORA,R12 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &CONT ; CYC1: TOR1 WNOSRE / &NOJMPI &BT16 &BF2U &BF2L / &JP XOR ; REP19: IMME H#FF80 / &DLE &IEN &NOOEY &NOSRE / &NOJMPI &BT16 &BF2U &BF2L / LE &IEN &NOOEY &SRE / &NOJMPI / &CONT ; SHFTR W,SHRR,SHUPL,R13 / &DLE &IEN &OEY &NOSRE / &NOJMPI / &CONT ; SHFTR W,SH"  &RPCT CYC1 ; TOR1 W,TORIR,SUBR,R6 / &NODLE &IEN &NOOEY &SRE / &NOJMPI / &RTN EJECT ; ; WRITE SECTOR ; ; (R3) TO R4 APL03 &WRGA / &RPCT WRSEC4 ; ; ; CLEAR (R4). ; INITIALIZE COUNTER FOR WRITE DATA POSTAMBLE LOOP. ; SOR W,MOVE,SOZR,R4 / RSEC3 ; SONR W,MOVE,SOD,NRY / &NODLE &NOIEN &OEY &NOSRE / &BF16 &BT03 &NOJMPI &OUPT &PL03 &WRGA / &CONT EJECT ; ; BEGINA / &CONT ; ; ; END WRITE DATA PREAMBLE LOOP. ; SONR W,MOVE,SOZ,NRY / &NODLE &NOIEN &OEY &NOSRE / &BF16 &BT03 &NOJMPI &F WRITE GATE. ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &NOJMPI &OUPT / &CONT ; ; ; THEN LEAVE OUTPUT MODE. (TURNS OFF WRIND MAR. ; ENTER OUTPUT MODE. (TURNS ON WRITE CLOCK.) ; INITIALIZE COUNTER FOR OUTPUT DATA PREAMBLE LOOP. ; WRSEC1: SOR W,NEG&NODLE &IEN &NOOEY &NOSRE / &NOJMPI &OUPT &WRGA / &LDCT 1 EJECT ; ; BEGIN WRITE DATA POSTAMBLE LOOP. ; OUTPUT H#0000 TO FI WRITE DATA SEGMENT LOOP. ; (R4) TO MAR. ; WRSEC4: SOR W,MOVE,SORY,R4 / &NODLE &NOIEN &OEY &NOSRE / &MADR &NOJMPI &OUPT &WROUPT &PL03 &WRGA / &RPCT WRSEC2 ; ; ; OUTPUT LAST DATA PREAMBLE BYTE AND THE H#FE DATA SYNC BYTE. ; INITIALIZE COUNTER FOR TE CLOCK.) ; LOAD 0 INTO R0. ; RETURN. ; SOR W,MOVE,SOZR,R0 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI / &RTN ; END ,SOAR,R4 / &NODLE &IEN &NOOEY &NOSRE / &MADR &NOJMPI &OUPT / &LDCT 5 ; ; ; BEGIN WRITE DATA PREAMBLE LOOP. ; TURN ON WRITFO ARRAY. ; WRSEC5: SOR W,MOVE,SORY,R4 / &NODLE &NOIEN &OEY &NOSRE / &NOJMPI &OUPT &WRGA / &IFNOT RDYO &CJP $ ; SOR W,MOGA / &CONT ; ; ; INCREMENT (R4). ; SOR W,INC,SORR,R4 / &NODLE &IEN &NOOEY &NOSRE / &NOJMPI &OUPT &WRGA / &CONT ; ;  TITLE SAMPLE CODE FOR THE Am29203 1/20/82 - DEW ; ; ; SAMPLE CODE FOR THE Am29203 - FOR USE IN ED2900A AND ED2900B SEMINWRITE DATA SEGMENT LOOP. ; PASS WHEN FIFO ARRAY AGAIN READY FOR OUTPUT. ; WRSEC3: SONR W,MOVE,SOI,NRY / &DLE &NOIEN &OEY &NO E GATE. ; PASS WHEN FIFO ARRAY READY FOR OUTPUT. ; WRSEC2: NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &NOJMPI &OUPT &WRGA / &IFNVE,SORY,R4 / &NODLE &NOIEN &OEY &NOSRE / &BF16 &BT03 &NOJMPI &OUPT &PL03 &WRGA / &CONT ; ; ; (NOOP FOR TIMING PURPOSES) ;; ((MAR)) TO FIFO ARRAY. ; END WRITE DATA SEGMENT LOOP. ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &BT03 &MREA &NOJMPI &OUPT &ARS ; ===================================================================== ; ; This file was originally created for the Am29SRE / &NOJMPI &OUPT &WRGA / &LDCT 131 ; IMME H#FE00 / &DLE &NOIEN &OEY &NOSRE / &NOJMPI &OUPT &WRGA / &IFNOT RDYO &CJP WOT RDYO &CJP $ ; ; ; OUTPUT H#0000 TO FIFO ARRAY. ; SONR W,MOVE,SOZ,NRY / &NODLE &NOIEN &OEY &NOSRE / &NOJMPI &OUPT &WRG END WRITE DATA POSTAMBLE LOOP. ; NOOP / &NODLE &NOIEN &NOOEY &NOSRE / &NOJMPI &OUPT &WRGA / &RPCT WRSEC5 ; ; ; TURN OF# 03. There are a few ; subtle changes necessary for proper operation of the Am29203 due ; to the bidirectional DA port. RAMABLINE TO MUX ; ; ; * * * * * ; SAMPLE Am29203 OPERATIONS FROM THE ED2900A CLASS NOTES ; THE 2900 FAMILY STUDY GUIDE ; ristics. ; The company assumes no responsibility for the use of any circuits or ; programs described herein. ; ; EJECT ; - ; 17. FIRMWARE BYTE SWAP ;--------------------------------------------------------------------------- AM2910 LDCT,, H#2 &e source ; equates must also be given careful consideration. ; ; ; This file was created for study. ; It does not contain aD THIRD REG FIELD ; ;---------------------------------------------------------------------------- ; 18. INCREMENT R15 AND OU CANNOT be used as the source for ; INCRR - RAMAQ or DAQ is required, for example. The original draft ; of the file did not THE ED2900B CLASS NOTES ; * * * * * ;------------------------------------------------------------------------- ; 15. DA +  ; ; ; ; ------------------------------------------------------------------- ; EDITED JAN 12, 1982 ; ; ADDED EQUATES - CON AM29203 , ADD, RAMUPL, IC, R15, R15 & SHIFT SDROT LA: AM2910 RPCT,, LA & AM29203 , ADD, RAMUPL, IC, R15, R15 & SHIFT SDROT ; complete microword. ; ; Anyone finding errors in this file is requested to send a marked listing ; or portion thereof to: AMTPUT ITS ORIGINAL VALUE ;---------------------------------------------------------------------------- AM2910 & AM29203 RAMAQ, catch these changes - although the DEF file was ; properly flagged. For users who are switching from one CPU to the ; other DB --> Yi ;-------------------------------------------------------------------------- AM2910 & AM29203 DADB, ADD, YBUS, NOCARDITIONAL CODE MULTIPLEXER ; ZERO: EQU Q#0 ; Z STATUS LINE TO MUX ;COUT: EQU Q#1 ; ALREADY DEFINED (note that this is a comm ;---------------------------------------------------------------------------- ; HARDWARE-ASSISTED BYTE SWAP ;---------------D CUSTOMER EDUCATION CENTER ; 490-A LAKESIDE DRIVE ; PO BOX #453 MS #71 ; SUNNYVALE, CA 94086 ; ; ; Advanced Micr INCRR, RAM, CARRY, R15, R15 ; ; THE AM2903 WOULD USE RAMAB (000) WHILE THE AM29203 REQUIRES ; RAMAQ (010) BE USED WITH THE I- be sure to proof your code for the changes shown in the ; Am29203 function table (normal functions, see the data book). ; ThRY ; ;-------------------------------------------------------------------------- ; 16. RA + RB --> RC (ANY THREE REGISTERS) ent) ;PASS: EQU Q#7 ; ALREADY DEFINED OVR: EQU Q#2 ; OVERFLOW STATUS LINE TO MUX NOVR: EQU Q#5 ; INVERTED OVERFLOW STATUS ------------------------------------------------------------ AM2910 & AM29203 DAQ, INCRR, RAM, NOCARRY, , R15 ; OR... AM291o Devices reserves the right to make changes in its product ; without notice in order to improve design or performance characteNCRR FUNCTION. SEE THE DATA SHEET. ; EJECT ; ; ;--------------------------------------------------------------------------e major problems will be encountered in selecting the proper source ; field to work with a given function field. The don't car;--------------------------------------------------------------------------- AM2910 & AM29203 , ADD, RAM, NOCARRY, R0, R1 ; AD$ 0 & AM29203 RAMAB, , RAM, , , R15, , OEYDIS ; ; **DAQ MUST BE CODED AS 101** ;------------------------------------------------------------ AM2910 & AM29203 , INCRS, RAMQDL, , , R2 & SHIFT DDZR ; ;-----------------------------2) ;--------------------------------------------------------------------------- AM2910 LDCT ,, H#E & AM29203 RAMAQ, INCRR, LOINCRS, QD, NOCARRY AM2910 & AM29203 , SPECL, DECRMNT, CARRY, , R4 AM2910 & AM29203 RAMAQ, INCRS, RAM, NOC RAMAQ, INCRR, RAMUPA, CARRY, R2, R2 & SHIFT SURZQZ ; ;----------------------------------------------------------------------- END, R4 HAS EXPONENT ; 16-BIT ALU ;--------------------------------------------------------------------------- NORMR0---------------------------------------------------- ; 19. DA --> Q ;------------------------------------------------------------------------------------------------------- ; 24. PERFORM 4*R2 --> Q IN ONE MICROCYCLE ;-----------------------------------ADQ, NOCARRY, R2 LC: AM2910 RPCT ,, LC & AM29203 , SPECL, TWOMULT, NOCARRY, R1, R0 /& SHIFT DDOR AM2910 ARRY, R6 LBLA: FF 64X ; PLACEHOLDER ABORT: FF 64X ; PLACEHOLDER ; ; load R6 into Q register ; test for Zi = 1 <==---- ; 21. UNSIGNED 16 BIT MULTIPLY (R1*R2) ;--------------------------------------------------------------------------- AM2: AM2910 & AM29203 RAMAQ, INCRR, LOADQ, NOCARRY, R6 AM2910 CJP, ZERO, ABORT & AM29203 , SPECL, SLN, , , , IENDIS AM------------------ AM2910 & AM29203 DAQ, INCRR, LOADQ, NOCARRY ; ;-------------------------------------------------------------------------------------------------- AM2910 & AM29203 , ADD, RAMQUPA, NOCARRY, R2, R2 & SHIFT SURZQZ AM2910 & AM29203 ,  & AM29203 , SPECL, TWOLAST, Z, R1, R0 /& SHIFT DDOR EJECT ; ;-------------------------------------------------> Qi = 0, all i; execute SLN with Ien disabled to set up ; special status pins ; test Cout = 1 <==> Q3 exor Q2 on MSS = 1; 910 LDCT ,, H#F & AM29203 RAMAQ, INCRR, LOADQ, NOCARRY, R2 LB: AM2910 RPCT ,, LB & AM29203 , SPECL, MULT, NOCARRY, R1, R2910 CJP, COUT, LBLA & AM29203 RAMAQ, INCRR, RAM, NOCARRY, R7, R4 AM2910 CJP, OVR, LBLA & AM29203 , SPECL, SLN, C----------------- ; 20. OUTPUT R2 AND PERFORM 2*(R2+1) --> R2 IN ONE MICROCYCLE ;---------------------------------------------INCRS, LOADQ, NOCARRY, , R2 ; ; *************** REQUIRES TWO MICROCYCLES! ******************************* EJECT; ; ; ;----------------------------- ; 23. PERFORM A DOUBLE PRECISION DOWN SHIFT USING R2 AND Q ;--------------------------------------already normalized; set-up exponent ; register R4 with existing exponent of number in R6 (or zero it out) ; test Ovr = 1 <=0 ; ;--------------------------------------------------------------------------- ; 22. TWO'S COMPLEMENT 16 BIT MULTIPLY (R1*RARRY, R4, R4 LBL4: AM2910 CJP, NOVR, LBL4 & AM29203 , SPECL, SLN, CARRY, R4, R4 AM2910 & AM29203 , ------------------------------ AM2910 & AM29203 RAMAQ, INCRR, RAMUPL, CARRY, R2, R2 & SHIFT SURZQZ ; OR... AM2910 & AM29203------------------------------------------------------------------------- ; 27. SINGLE LENGTH NORMALIZE OF R6 (16 BIT ALU) - AT% => Q2 exor Q1 on MSS = 1; normalized after this step; execute ; SLN with Ien enabled; SLN shifts Q AND increments the exponIGN MAGNITUDE CONVERSION OF R8 INTO TWO'S COMPLEMENT ;-------------------------------------------------------------------------------------- AM2910 & AM29203 DADB, NAND, YBUS ; YBUS REPEATED FOR CLARITY ; ;--------------------------------------------U) ;--------------------------------------------------------------------------- ;- NOT CODED YET -------- 1/20/82 EJECT ; D, NOCARRY, R4, R3 ; ;--------------------------------------------------------------------------- ; DECREMENT R2 BY 2 ( R2 <-ent register ; test for no Ovr; loop until overflow occurs (number is normalized); SLN ; recover Q since status lags behind tr-- AM2910 & AM29203 , SPECL, SGNTWO, Z, , R2 ; ;--------------------------------------------------------------------------- ------------------------------- ; SIGN EXTEND R2 ;--------------------------------------------------------------------------- ;--------------------------------------------------------------------------- ; ADD R1 + R2 -> R2 ;---------------------------- R2 - 2 ) ;--------------------------------------------------------------------------- AM2910 & AM29203 , SPECL, DECRMNT, NOCue state (ED2900A/ED2900B/C seminars) ; by down shifting Q register ; decrement the exponent register by -1 (NOTE: unique  ; INCREMENT R2 BY 2 ( R2 <- R2 + 2 ) ;--------------------------------------------------------------------------- AM2910 & A AM2910 & AM29203 , SPECL, SIGNEXT, NOCARRY, , R2 ; ; NOTE: ADD 1-BIT FIELD FOR I5 FOR RAMEXT ; FIRST TWO SLICES RECEI----------------------------------------------- AM2910 & AM29203 , ADD, RAM, , R1, R2 ; ;-----------------------------------ARRY, , R2 ; ;--------------------------------------------------------------------------- EJECT ; ; ; ; ; END to Am29203) ; put -> ; ; REFERENCE: Am2900 FAMILY STUDY GUIDE AND TEACHER'S MANUAL; CEC.PUB-29-3 ($18.00) EJECT M29203 , SPECL, INCRMNT, CARRY, , R2 ; ;--------------------------------------------------------------------------- ; BCD ADVE RAMEXT, LAST TWO SLICES RECEIVE SIGNEXT ; ;--------------------------------------------------------------------------- ; S---------------------------------------- ; NAND DA, DB -> YBUS ;-------------------------------------------------------------- ;--------------------------------------------------------------------------- ; 28. DOUBLE LENGTH NORMALIZE OF R6.R7 (16 BIT ALD R3 + R4 -> R3 ;--------------------------------------------------------------------------- AM2910 & AM29203 , SPECL, BCD.AD& TITLE DEMO SRC FILE FOR AM29116.DEF - D. E. WHITE - JAN 12, 1982 EDIT ; ; D.E.WHITE OCT. 17, 1980 ; EDITED DEC. 30, 1981 ; ; ; TWO OPERAND INSTRUCTIONS ; ; TOR1 ,,, W, TODRR, SUBS, R31 ; R31 <- R31- ; TOR1 ,,, W, TORIY, AND, R ,,, W, INC, SORA, R31 ; R31 <- R31 + 1 SOR ,,, W, NEG, SORA, R31 ; ACC <- NOT R31 + 1 SOR ,,, W, COMP, SORA, R31 ; ACCH#E, RTDA ; ACC <- DATA LATCH ; ; ; ; BIT-ORIENTED INSTRUCTIONS ; ; BOR1 ,,, W, H#6, SETNR, R10 ; SET BIT 6 BOR1 ,. ; ; ; ; ; EJECT ; ; ; ; FREE FORMAT CONSTANTS ; FF1: EQU 4H#E ; AM2910 CONTINUE FF4: EQU 5B#01000 ; AM29116 ENAEJECT ; SINGLE BIT SHIFT INSTRUCTIONS ; ; SHFTR ,,, W, SHRR, SHUP1, R10 ; SHIFT R10 <- 1 SHFTR ,,, W, SHRR, SHUPL, R10 ; EDITED JAN. 12, 1982 ; ; ; ; This file was created just to debug the master file, CONTROLR.DEF. It ; exercises the Am290 ; Y <- R0 AND IMMEDIATE FF FF1, 15X, H#ABCD, FF4, 24X ; DATA FOR ABOVE ; TOR1 ,,, B, TORAA, ADD, R31 ; ACC <- R31 + A <- NOT R31 ; SONR ,,, W, MOVE, SOI, NRS ; STATUS <- NEXT WORD FF H#E, 15X, H#0123, B#01000, 24X ; DATA FOR ABOVE ; SO,, W, H#8, RSTNR, R10 ; RESET BIT 8 BOR1 ,,, W, H#F, TSTNR, R31 ; TEST BIT 15 ; BOR2 ,,, W, H#C, S2NR, R31 ; R31 <- BLES ; ; Additional mnemonics may be defined in the .SRC file as needed so that the ; .DEF file does not need to be re-asse; SHIFT R10 <- QLINK SHFTR ,,, W, SHRR, SHDNZ, R10 ; SHIFT 0 -> R10 ; SHFTNR ,,, W, SHA, SHDNOV,NRA ; SHIFT QN XOR QOVR 116 DEF statements to demonstrate their usage. ; ; ; ; ; ; Advanced Micro Devices reserves the right to make changes in CC ; TOR2 ,,, W, TODIR, SUBS, R0 ; R0 <- DATA - IMMEDIATE FF FF1, 15X, H#0002, FF4, 24X ; DATA FOR THE ABOVE ; TOR2 ,,,NR ,,, W, NEG, SOI, NRA ; ACC <- NOT I + 1 FF H#E, 15X, H#0000, B#01000, 24X ; DATA FOR ABOVE ; ; The above is an eR31 - 2**12 ; BONR ,,, W, H#3, RSTNA ; RESET BIT 3 IN ACC BONR ,,, W, H#C, LD2NA ; ACC <- 2**12 BONR ,,, mbled. This should be minimized for ; proper documentation ; ; NOTE: the below is a BLANK line - AMDASM accepts it ;->ACC ; ; ; ; ROTATE INSTRUCTIONS ; ; ROTR1 ,,, W, H#8, RTRA, R10 ; ACC <- R10 ROTR1 ,,, W, H#F, RTRR, R31 ; R31its product ; without notice in order to improve design or performance characteristics. ; The company assumes no responsibilit W, TODAR, EXOR, R30 ; R30 <- D EXOR ACC ; TONR ,,, W, TOAI, ADDC, NRA ; ACC <= ACC + I + CIN FF FF1, 15X, H#5555, FF4, xample of the free-format executable statement. ; It supplies data for the two-microcycle immediate data instructions. EJECT W, H#3, RSTND ; RESET BIT 3, DATA LATCH ; EJECT ; ROTATE AND MERGE INSTRUCTIONS ; ; ; R6 <- ACC AND R6 NO OPERATION ; NOOP ; EJECT ; ; ; ; SINGLE OPERAND INSTRUCTIONS ; ; SOR ,,, W, MOVE, SORA, R10 ; ACC <- R10 SOR <- R31 ; ROTR2 ,,, W, H#3, RTAR, R10 ; R10 <- ACC ; ROTNR ,,, W, H#5, RTAA ; ACC <- ACC ROTNR ,,, W, y for the use of any circuits or ; programs described herein. ; ; Am29116 Mnemonics Copyright c Advanced Micro Devices, Inc24X ; DATA FOR ABOVE ; TONR ,,, W, TODA, AND, NRA ; ACC <- D AND ACC TONR ,,, B, TODA, SUBS, NRA ; ACC <- D - ACC ; '  OR NOT ACC AND D (ROTATED) ; ROTM ,,, W, H#6, MDRA, R6 ; ROTM ,,, W, H#B, MARI, R6 FF FF1, 15X, H#AAAA, FF4, 24X ; designs (Am2901-2903 or 29203) RALUs + misc other parts in comma-positional  ; ; SETST ,,, SONZC ; SET ALU STATUS SETST ,,, SF3 ; SET FLAG 3 ; RSTST ,,, RF2 ; RESET FLAG 2 RSTST at is discussed in the application note, "A High Performance Intelligent Dis ; ; ; ROTATE AND COMPARE INSTRUCTIONS ; ; ROTC ,,, W, H#6, CDAI, R5 ; D ACC I (R?) FF FF1, 15X, H#1874, FF4, 24X :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: DISK.DOC --------- This diskette shoul notation. Am29203.SRC Sample source code for an Am29203 CPU (Am2910 sequence,,, RONCZ ; RESET ALU STATUS ; SVSTR ,,, W, R6 ; R6 <- STATUS SVSTNR ,,, W, NRA ; ACC <- STATUS ; ; ; ; TEk Controller" by O. Tabler and B. Kitson. This file is in DEF statement-over; ROTC ,,, W, H#C, CRAI, R6 FF FF1, 15X, H#5656, FF4, 24X ; ; ; ; PRIORITIZE INSTRUCTIONS ; ; PRT1 ,,, W, PR1A, Pd contain 6 additional files: CONTROLR.DEF The "master" .DEF file for the Am29116 + misr). (Uses Am29CPU.DEF) These AMDASM.DEF files are provided as a service to AmSYS29 customers. They are intended ST STATUS INSTRUCTIONS ; ; TEST ,,, TZ ; TEST Z TEST ,,, TF1 ; TEST FLAG 1 TEST ,,, TNO ; TEST N EXOR OVR TESlay format. DISKCTLR.SRC The source code for the disk controller. RT1A, R6 ; PRT2 ,,, W, PRA, PR2A, R6 ; PRT3 ,,, W, PRA, PR3R, R6 ; PRTNR ,,, W, PRA, PRTA, NRY ; EJECT ; CRC Ic other parts in comma-positional notation. CONTROLR.SRC A test SRC file (partial microto provide a basis from which the customer may select those equates, subs and definitions appropriate to a given dT ,,, TC ; TEST C ; ; ; ; ; ; END  (This file assembles to a 92K P2L file.) Am29CPU.DEF The "MASTER" .DEF file for RALU-based NSTRUCTIONS (SINGLE CALL) ; ; CRCF ,,, R6 ; CRC FORWARD ; CRCR ,,, R6 ; CRC REVERSE ; ; ; ; STATUS INSTRUCTIONSword). DISKCTLR.DEF The .DEF file for the Am29116-Am9520 (BEP) based disk controller th( esign problem. It is intended that the customer edit a copy of one or more .DEF files to produce the desired .DEF filo DEF statements and the SUB deleted to convert the control line specification to overlays. The required usage  SUB statement, all of the other DEF statements can be altered. This means that any of the three fields can be altered or efine the Am2904 by defining only what is required for a given design. There are no standard mnemonics. Am2925 Equatetion provides an effective index to the file. The various EQU groups of the Am29116 instructions are indexed ([i]) for croquires a RAM register address ([R]). Am2914 The instruction set only is defined. Am2940 The instruction set one. The .SRC files are provided as a reference. The microword will probably not match the customer's requirements.  and personal preference are the deciding factors in the approach. Instructions Pages 8-20 are the Am29116 instructioeven eliminated by editing one statement. Control_lines Several of the control lines for the Am29116 are presented ins for cycle length codes plus place-holders (incomplete definition) for control lines are provided. Again, DEF state ss reference by the DEF statements. Each instruction type has its own DEF statement. The Am2910 instructions, withly is defined. The instruction set is flagged by ".40" to avoid duplicate mnemonics with the Am2942. Am2942 The in CONTROLR.DEF ------------- Originally created as a master file for study, it has been edited into one application, "DISns. Each class is defined by first defining the mnemonics and then the DEF statement. The mnemonics are taken directly a second SUB statement. Note that not all of the Am29116 lines appear (the Ti lines, for example, were not input).  ments may be used instead. Am2950/51 A comment only. CONTROLR.SRC ------------ This source file is for debugout any of the additional control lines (OEy, RLD, CCEN) are presented with a SUB statement. The Am2910, a 3-bit condstruction set only is defined. Am2904 The Am2904 instruction set is very powerful and extensive. Some ideas for mnemKCTLR.DEF". It is recommended that the user compare these two .DEF files for similarities and differences. T from the Am29116 data sheet. For example, SOR, the single operand-RAM instruction format (page 5 of the Am29116 data  This manner of definition requires comma positional substitution in the source file. These lines can be edited int of the preceding .DEF file. It was prepared primarily for study. Page 3 provides calls to the single operand instructionitional MUX field, and a 12-bit variable address field are part of each of the following DEF statements. By editing theonics are given for shift control and various other commands and some sample DEF statements are included. The user must dhe file includes a number of parts which may or may not appear in a controller. The first page after the WORD declarasheet) has a choice of word-byte mode ([m]), 1 of 4 op codes ([1]), 1 of 10 source-destination pair selects ([2]), and re) s. SONR requires an immediate data word and it is provided via a free format (FF) statement. Example: SOR  The choice here was to use overlay in the source file; therefore, all Am2910 instructions were defined as DEF statemer was created by editing the "master" file. The Am29116 instructions were left basically intact; the major change waster Enable 21 1 Ouput Enable - Yi 22 1 Instruction Enable ddress field for AMDASM, i.e. 12V$X, 6V$X, etc. Note on microword: This incomplete microword was laid out for study  the basic 16 instructions. Misc_Control_Signals All of the remaining control signals appear as DEF statements for o,,, W, MOVE, SORA, R10 SONR ,,, W, MOVE, SOI, NRS FF H#E, 15X, H#0123, B#01000, 24X Note the commas. Thisents rather than equates. Immediate_Operand The study file used FF statements in the .SRC file to provide data fors the deletion of the Am2910 and ZZZZZ SUB statements. The length of the microword was also increased from 64 to 80 b 23 1 Data Latch (D-I-Latch) Enable 24-27 4 Am2910 Instruction of the Am29116 and will not necessarily match an actual microword format for a controller. The 24 don't cares would be verlay in the source file. The_Microword_-_DISKCTLR.DEF Bit_Position________#_________Function________ can be avoided by the use of overlays. (Note that this is an incomplete microword.) CONTROLR.DEF_+_CONTROLR.SRC_MICRO immediate data operand instructions. Here, IMME is a DEF statement which can be overlayed with other DEF statements to its. A global substitution (under ED, the editor) replaced Am2910 by nothing and ZZZZZ by 64X. The instruction sets f 28-37 10 Branch Address 38-42 5 Condition Code Selections 43  replaced by other controls and the microword might be larger than 64 bits. DISKCTLR.DEF ------------ An _____________ 0-15 16 Am29116 Instruction 0-15 16 Immediate Data OpeWORD 2910 COND BR 29116 INSTR MUX ADDR CTLs OPEN 4 3 build a microword. Control_Lines Control lines for the Am29116 are defined in DEF statements for overlay. Am291or all other parts were deleted. Beginning on page 19, EQUs and DEFs were added according to the design requirements.  1 Parity 44 1 Address Mark Control 45 1 Mem AMD application note is being prepared which discusses a high performance disk controller. The .DEF file for the controllrand 16-19 4 CT Multiplexer Control (Ti Lines) 20 1 Status Regi 12 16 24 = 64 bits Note on address fields: To avoid problems, use $ as the attribute in a0 The Am2910 command are defined in DEF statements. Note the use of JS, JP, RTN, IF and IF NOT which have been added to* ory Bus from Drive Control Bus 46 1 Memory Bus from Translate PROM 47  67 1 Output Serial Data from 9403AS 68 1 Parameter Enable  59 1 Clock Pulse (Actual Waveform) for Am9520 60 h positional substitutions minimized (primarily appears in the Am29116 instructions). The code is commented. Am29Cto Am9520 - LSB 55 1 Memory Bus to Am9520 - MSB Bit_Position________#_________Funix Example_Source_Code_Lines SOR W, MOVE, SORY, R4 & NODLE & NOIEN \ & OEY & NOSRE & MADR & N1 Memory Bus from 9403AS 48 1 Memory Bus from Am29116 49 1  69 1 Set 9520 P Bits from 9520 PM Bits 70 1 Parallel Fetch from 940 1 Command Request 61 1 Input Serial Data to 9403AS 62-63 PU.DEF ------------- The original AmSYS29 software included a library file, AM2900.LIB, which provided the ction______________________ 56 1 Memory Bus to Am9520 - Control OJMPI & CONT ; MOVE R4 TO MAR SOR W, MOVE, SOZR, R0 & NODLE & IEN \ & NOOEY & NOSRE & NOJMPI & RTN ;  Memory Bus from Am9520 - LSB 50 1 Memory Bus from Am9520 - MSB 51 3AS 71 1 Parallel Load into 9403AS 72 1 Parameter Request  2 Jump Indirect Am29116 Register 62-63 2 No Indirect Jump 64 1user with a source of predefined mnemonics for various parts. The AM29CPU.DEF file is the latest descendant of that origin Information 57 1 Clock Enable Am9520 to Lower- Byte Bu Load 0 into R0 and return DISKCTLR.SRC -------------- This file, a very large one, was prepared for 1 (Disk) Bus Direction out from Controller 52 1 Me 73 1 Read Gate 74 1 Reset FIFO 75 1  Memory Access 65 1 Memory Address 66 1 Memory Write al file. The AM29CPU.DEF file provides mnemonics for a number of parts considered to be likely to appear in a CPU desigs Int. 58 1 Clock Enable Memory Bus to Am9520 Transfer  the AMD application note, "A High Performance Disk Controller". The code is written using overlaid DEF statements witmory Bus to 9403AS 53 1 Memory Bus to Am29116 54 1 Memory Bus  Select/Attention Strobe 76 1 Write Gate 77-79 3 Translate Pref+ n, as opposed to a controller design. This includes the Am2901, Am2903 and Am29203 RALUs. Flags are used to  Register [R] All RALUs use 4-bit addresses for the on-board registers. Carry A few not-inclusive definitions  two parts. The differences are in the function set and the special functions. While many of the equates in these actuas which may be substituted in a given variable field in place of the default value. DEF statements for the Am2904s included Am2930 Only the instruction set is included Am2932 Only the instruction set is iovide ideas. The customer must create his or her own definitions for equates and DEF statements. There are no standard  differentiate duplicate mnemonics. (The Am29203 is given priority.) The user must edit a version of this file to completare provided. This is not programming for the Am2904. Am2910_-_Am29811 The instruction set for the Am2910 is lly were the same, there were enough differences to flag that separate definitions were felt to be clearer. Exp are given as well as statements specific to a particular .SRC file. This was done for demonstration -- one DEncluded. The instruction set is flagged by ".32" to differentiate it from that of the Am2930. Am2940 Only the instrmnemonics. DEF_Statements Comma positional within the part and overlay are used to create the microword. e a .DEF file for a particular application. Most of the equate groups are indexed ([i]) for cross reference from DEF a provided. The Am29811 differs only in the last mnemonic, substituting JP for TWB. An example SUB statement is provideanded_Memory The Am2903 and Am29203 have expandable registers. The Am29705/ 29707 2-port memories allow groups of 16 reF file may be used with more than one SRC file. The .DEF file is then the main or master mnemonic reference for auction set is included. Am2902_-_Am29203 The instruction set is flagged by ".03" in cases where it dThe DEF statements are intended to demonstrate typical ALU and sequencer definitions. The balance of the micro word is undnd SUB statements. Am2901 The oldest RALU, the function and destination fields are flagged, by .01. Example SUB std. Am2925 Cycle length codes and an indication of control lines are provided. The control line definitions argisters to be added. This changes the microword source fields. Example mnemonics are provided for a particular diagram.  set of source programs. Am29203.SRC This file, developed from one that was originally prepared for the Am29uplicates that of the Am29203. Certain equate groups (source select and destination for example) are the same for the efined. Note the use of commented default line plus the index reference [i]. The reference identifies equate mnemonicatements are included following the equates. The mnemonics are from the data sheet. Am2914 Only the instruction set ie incomplete. Am2904 As in the CONTROLR.DEF file -- incomplete as far as total Am2904 capabilities. Intended to pr, 03 (AM2903.SRC) was prepared to demonstrate how to program the Am29203. The microword is in a conceptual, standard foLR.DEF = 5FE1 D:DISKCTLR.SRC = 603F AM2910 & AM29203 ,ADD,RAMQUPA,NOCARRY,R2,R2 & SHIFT SUR2Q2 Since the code was prepared for study, it is more detailed rmat: 2 9 1 0 2 9 2 0 3 2 9 0 4 2910 COND BR SOURCE FUNC DEST CARRNOOEY &NOSRE / &NOJMPI &OUPT / &CONT ; ; ; THEN LEAVE OUTPUT MODE. (TURNS OFF WRIthan might otherwise be necessary; i.e., defaults are resubstituted occasionally, etc. Improvements in readability couldY Ra Rd Ien 0ey Shift SE INSTR MUX ADDR A L U IN ADDR ADDR en INSTR en 4 3 12  be obtained by the use of specialized DEF statements and increased use of overlays. 3 4 4 2 4 4 1 1 14x 4 1 3x 47 bits + 17 don't cares = 64 bit word SamplD:AM29203 .SRC = 32AA D:AM29CPU .DEF = 9A84 D:CONTROLR.DEF = 3027 D:CONTROLR.SRC = D714 D:DISK .DOC = 851D D:DISKCTe_Code_Lines AM2910 RPCT, ,LB & AM29203 ,SPECL, MULT, NOCARRY, R1, R0 AM2910 & AM29202 RAMAB, ,RAM,,,R15,,OENDIS - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L